SiLab C8051F064, SPI, 3/4 wire, P0.3, NSSMD problem
Bill Davy
========================================
Commissioning new board which has used P0.3 for a chip select for an SPI
device (MAX3420 being USB target).The 8051 is the SPI master. In the past
we used P3.7 for chip select (with SPI in three wire mode) and all worked
well.
First approach was to use P0.3 as a GPIO pin. Wanted to do this as we had
previously used 3-wire SPI without any problem.
With the following setting, P0.3 does not change:
P0MDOUT = 0x0D
SPIOCN = 0x03 meaning NSSMD = 00b so three wire SPI, leaving P0.3 as a GPIO
pin.
XBR0 = 0x02
XBR1 = 0x31
XBR2 = 0x40 (set last, so XBARE=1 is final part of set-up)
XBR3 = 0x08
Setting and clearing P0.3 has no effect on the output pin (confirmed with a
�scope).
The SPI is set up before enabling the cross bar because that was recommended
(though cannot find the reference now) and as I say, it has and does work
well like that.
Second approach was to use 4-wire SPI (NSSMD1=1) and use NSSMD0 to wiggle
the wire that was P0.3 and hooray, the wire does wiggle (proving it is
soldered up right). But now we have another problem. It is a bit hard to
explain, but the MISO line which should be coming from the MAX3420 sometimes
seems to be being pulled down so the 8051 does not reliably see 1's. This
can happen while the byte is being shifted out, and even with all interrupts
disabled and the processor just waiting for the shift register to empty.
If we use a wire link from P3.7 to CS everything works fine which suggests
the wiring and software is hunky dory (USB connects, etc).
Desperate to use P0.3 as there are 18 boards made up :-(
TIA,
Bill Davy
Gene S. Berkowitz
Bi...@SynectixLtd.com says...
> SiLab C8051F064, SPI, 3/4 wire, P0.3, NSSMD problem:
>
> device (MAX3420 being USB target).The 8051 is the SPI master. In the past
> we used P3.7 for chip select (with SPI in three wire mode) and all worked
> well.
>
> First approach was to use P0.3 as a GPIO pin. Wanted to do this as we had
> previously used 3-wire SPI without any problem.
>
> With the following setting, P0.3 does not change:
>
> P0MDOUT = 0x0D
> SPIOCN = 0x03 meaning NSSMD = 00b so three wire SPI, leaving P0.3 as a GPIO
> pin.
> XBR0 = 0x02
>
> XBR1 = 0x31
>
> XBR2 = 0x40 (set last, so XBARE=1 is final part of set-up)
>
> XBR3 = 0x08
>
> Setting and clearing P0.3 has no effect on the output pin (confirmed with a
> ?scope).
I would check your crossbar configuration again; I think you
might have P0.3 configured as MISO.
> The SPI is set up before enabling the cross bar because that was recommended
> (though cannot find the reference now) and as I say, it has and does work
> well like that.
>
> Second approach was to use 4-wire SPI (NSSMD1=1) and use NSSMD0 to wiggle
> the wire that was P0.3 and hooray, the wire does wiggle (proving it is
> soldered up right). But now we have another problem. It is a bit hard to
> explain, but the MISO line which should be coming from the MAX3420 sometimes
> seems to be being pulled down so the 8051 does not reliably see 1's. This
> can happen while the byte is being shifted out, and even with all interrupts
> disabled and the processor just waiting for the shift register to empty.
MISO is likely configured as open-drain. Are you relying only on
the weak internal pullup? Try something stiffer.
Bill Davy
news:MPG.2579ed48b...@news.giganews.com...
In article <7n9ugmF...@mid.individual.net>,
Bi...@SynectixLtd.com says...
> SiLab C8051F064, SPI, 3/4 wire, P0.3, NSSMD problem:
>
> Commissioning new board which has used P0.3 for a chip select for an SPI
> device (MAX3420 being USB target).The 8051 is the SPI master. In the past
> we used P3.7 for chip select (with SPI in three wire mode) and all worked
> well.
>
> First approach was to use P0.3 as a GPIO pin. Wanted to do this as we had
> previously used 3-wire SPI without any problem.
>
> With the following setting, P0.3 does not change:
>
> P0MDOUT = 0x0D
> SPIOCN = 0x03 meaning NSSMD = 00b so three wire SPI, leaving P0.3 as a
> GPIO
> pin.
> XBR0 = 0x02
>
> XBR1 = 0x31
>
> XBR2 = 0x40 (set last, so XBARE=1 is final part of set-up)
>
> XBR3 = 0x08
>
> Setting and clearing P0.3 has no effect on the output pin (confirmed with
> a
> ?scope).
I would check your crossbar configuration again; I think you
might have P0.3 configured as MISO.
SPIOCN = 0x03 meaning NSSMD = 00b so three wire SPI
XBR0 = 0x02 (SPIOEN)
XBR1 = 0x31 (CP1E, INT1E, T2E)
XBR2 = 0x40 (set last, so XBARE=1 is final part of set-up)
XBR3 = 0x08 (CP2E)
So I would expect to see:
P0.0 = SCK
P0.1 = MISO
P0.2 = MOSI
P0.3 = CP1
P0.4 = CP2
P0.5 = INT1
P0.6 = T2
> The SPI is set up before enabling the cross bar because that was
> recommended
> (though cannot find the reference now) and as I say, it has and does work
> well like that.
>
> Second approach was to use 4-wire SPI (NSSMD1=1) and use NSSMD0 to wiggle
> the wire that was P0.3 and hooray, the wire does wiggle (proving it is
> soldered up right). But now we have another problem. It is a bit hard to
> explain, but the MISO line which should be coming from the MAX3420
> sometimes
> seems to be being pulled down so the 8051 does not reliably see 1's. This
> can happen while the byte is being shifted out, and even with all
> interrupts
> disabled and the processor just waiting for the shift register to empty.
MISO is likely configured as open-drain. Are you relying only on
the weak internal pullup? Try something stiffer.
OK, I will look into that.
>
> If we use a wire link from P3.7 to CS everything works fine which suggests
> the wiring and software is hunky dory (USB connects, etc).
>
>
> Desperate to use P0.3 as there are 18 boards made up :-(
>
>
>
> TIA,
>
> Bill Davy
Bill
PS Sorry, do not see how to make Outlook Express include original message
shifted over.