i2c master
pachu
i have one doubt related to i2c master concept.
Assume i have 3 chips (A, B, and C) all having the capability to
receive and send.
How does one decide who is the master ?
Will there be a single master at all instance of time or the one who
starts the communication is called as the master ?
Say for instance.
1) A wants to read from B...
2) so A puts the START signal, address of B on the bus and the read
bit on the Bus.
3) B knows that A has addressed and will send the data requested on
the bus.
4) A will send a STOP signal.
Here i guess A is the master. Now after some time B want to read from
A
1) B wants to read from A...
2) so B puts the START signal, address of A on the bus and the read
bit on the Bus.
3) A knows that B has addressed and will send the data requested on
the bus.
4) B will send a STOP signal.
I guess here B is the master.
Now tell me, both A and B can behave as masters depending on the
situation.
Is my understanding correct ? or am i wrong.
Thanks all regards
pachu
Hans-Bernhard Broeker
> How does one decide who is the master ?
In what ever way one likes to decide. Flip a coin, if nothing else
helps ;-)
> Will there be a single master at all instance of time or the one who
> starts the communication is called as the master ?
More of the latter. I2C is multi-master capable, i.e. as far as the
bus is concerned, any device could become the master, at some point in
time. Read the specs for yourself to see how the protocol resolves
collisions between multiple nodes trying to become bus master at the
same time.
Usually, only processors are capable of being the bus master, though.
Most "I2C peripherals" are slave-only.
--
Hans-Bernhard Broeker (bro...@physik.rwth-aachen.de)
Even if all the snow were burnt, ashes would remain.
simon
A master won't try to use the bus if it is busy
A problem arises only when 2 masters start right at the same time.
Then they both write away. At some point one of them will write a 1,
when the other writes a 0
The 0 wins being open drain drive, and the 1 master abandons the
attempt. ie masters must detect that SDA is low, when they expect it
to be high, and back off until the bus is free again
Simon
pach...@hotmail.com (pachu) wrote in message news:<c985418f.03052...@posting.google.com>...
pachu
Ok good , my understood by reading the specs was right...Now to
the next part of the question.
Consider the following senario. ( we are still at the design stage so
no specific hardware info is available)
There is one board, which has he following hooked to the I2C bus
1) A microcontroller with some gpio pins.
2) A serial EEPROM (ATMEL - AT24C01A )
I2C has been implemented as software using the microcontrollers gpio
pins to read and write to the EEPROM.
Now we have a client who would want to add one more chip on to the I2C
bus to communicate with the microcontroller.
Now i guess there could be two ways our client could have implemented
I2C.
1) his chip has a inbuilt hardware i2c implementation or
2) he too has used software implementation of i2c.
On our side the design is fixed and it will be software
implementation of I2C using the GPIO pins of our microcontroller.
Now keeping in mind the two possible ways of our clients i2c
implementation how could we modify our code...any suggestions ?
I ask this because i read somewhere that is I2C has been implemented
as software then there can be only a single master....why is this...
thanks and regards
pachu
623...@despammed.com (simon) wrote in message news:<7a8b3e34.0305...@posting.google.com>...
Robert Lacoste
conected to the bus as a slave ! Your current master could poll this new
slave for any request from time to time. That way you will not need to
change your master biitbanging firmware to implement a multimaster mode.
Moreover writing a slave I2C firmware, with or without dedicated hardware,
is not too complex.
Hope that will be helpfull,
Cheers,
Robert Lacoste - ALCIOM
http://www.alciom.com
"pachu" <pach...@hotmail.com> a écrit dans le message de news:
c985418f.03052...@posting.google.com...
Eyck Jentzsch
you are correct, both may be the master. Arbitration is done using the
slave address. The master having the first '1' bit in the address where
the other has a '0' looses the bus. This is explained in the I2C
documentation from Phillips (it can be found on the Phillips website)...
-Eyck
Hans-Bernhard Broeker
> I ask this because i read somewhere that is I2C has been implemented
> as software then there can be only a single master....why is this...
I see no particularly compelling reason why that statement you read
"somewhere" should be true. For almost any completely nonsense
statement imaginable, there's bound to be a place you could read it,
esp. in the days of the Internet.
That set aside, of course it'll be a whole lot easier to implement
only a subset of the actual specification, if you're going to have to
do it yourself. Which may well mean that some implementations you'll
find out there won't support multi-master operation at all. Some of
them may even be honest enough to document that limitation right on
the advertisement...
Implementing an I2C slave-only node in software is bound to be simpler
than one that can be both master or slave. And implementing a
strictly single-master node is a good deal easier than implementing
one that can correctly coexist with other masters on the bus.
It may eat up more resources, too. You may need two uC pins per wire
to be able to handle arbitration loss correctly, for starters.