Alternate PHY Usage

[Michael Karas]

[This followup was posted to comp.arch.embedded and a copy was sent to the cited author.]

Does anyone have any comments about an idea to utilize RMII PHY chips to
create a custom data link between two end points without using an
Ethernet MAC as the end point terminations. Is it feasible that an FPGA
design could be used to create a simple real time high speed protocol
between the two locations? Standard RJ45 MagJacks and Cat 6 cables could
be used for the connectivity.

--

Michael Karas
Carousel Design Solutions
http://www.carousel-design.com

[Michael Karas]

[This followup was posted to comp.arch.embedded and a copy was sent to
the cited author.]

In article <0fOdnSsAQqSYljDS...@lyse.net>,
da...@westcontrol.removethisbit.com says...
>
> I can't tell you the details here, but I might be able to give some
> hints as to what to look for.
>
> Auto link negotiation is handled by the PHY by sending particular
> patterns on the link - you may want to specifically disable this using
> the MDIO interface to the PHY.
>
> Other than that, there are probably rules regarding runs of equal bits
> and DC bias which you may need to consider.
>


Yes, the AutoLink option needs to be turned off via the MDIO interface.
Along with that the protocol would be forced to 100Mb by the same access
method.

The apparent beauty of using the PHY is that much of the low level
details are handled in the component. The typical RMII PHY has these
things in its signal path. A 100 MB PHY will implement the following
steps on the Tx path - parallel to serial conversion, 4B/5B encoding,
scrambling, NRZ-to-NRZI conversion and MLT3 encoding and transmission to
the magnetics in the MagJack. On the Rx path the PHY does the opposite
including - adaptive equalization, DC restoration (also referred to as
baseline wander compensation), MLT3-to-NRZI conversion, de-scrambling,
4B/5B decoding, and serial to parallel conversion.