ADS1251 and 8051 Code
Bill Davy
Has anyone done this who can share the code? Just to save me time.
Any gotchas?
I'd also quite like not to take every sample so I can use just the ADS1251
to interrupt so it is both my clock and a data ready interrupt. I suppose
it would be best to at least take one bit of the result.
TIA,
Bill
Vladimir Vassilevsky
Bill Davy wrote:
> ADS1251 and 8051 Code
> Has anyone done this who can share the code? Just to save me time.
Yes.
> Any gotchas?
Time is money.
> I'd also quite like not to take every sample so I can use just the ADS1251
> to interrupt so it is both my clock and a data ready interrupt. I suppose
> it would be best to at least take one bit of the result.
Anything you like.
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
Joey.G
What Vladimir is trying to say is a project has 4 factors, quality,
cost, time and experience.... changing only one of these factors
effects the other factors
Hence if you are in a hurry and have little experience and good
quality is required.....expect to pay money for an answer or support
from Vladimir.
Joe
Bill Davy
news:d4f2700e-0868-4b6d...@m38g2000yqd.googlegroups.com...
Joe
------------------------------
In the past I have posted source code because when I started the Internet
was a community not a marketplace. If Vladimir wishes to advertise his
services or make snide remarks, perhaps he could find a different place (a
kindergarten).
I have been programming in assembler since 1972. I believe it is better to
work as a team (but I am the only programmer on this project). I believe we
see further if we stand on another's shoulders. I believe the Good
Samaritan is still a good parable for society.
Wanders off, shaking head sadly.
Bill Davy
news:7m4mt3F...@mid.individual.net...
Well, I have cobbled something together to get timing. Assuming Keil
compiler (though only using assembler). Two ADS1251 share an SCLK line but
have separate Data Ready lines.
Oh, and no cahrge for this.
Bill
sbit SCLK = P0^0 ;
sbit DOR_A = P0^1 ;
sbit DOR_B = P0^2 ;
u8 ADC_A[4]; // little-endian
void ReadADS1251(void)
{
#pragma asm
;
; Build ADC_A in (R0,R1,R2) and ADC_B in (R3,R4,R5).
; Use R6 to count 8 bits in.
;
;
; This loop shifts eight bits in from each ADC, building the two values in
; the accumulator and the register which will hold the ADC_B byte.
; There is no need to initialise either as all old bits are
; shifted out.
;
mov R6,#8 ; 2 cycles
Loop_0_3:
setb SCLK ; 2 cycles
mov c,DOR_A ; 2 cycles
rlc a ; 1 cycle
xch a,r3 ; 1 cycle
mov c,DOR_B ; 2 cycles
rlc a ; 1 cycle
xch a,r3 ; 1 cycle
clr SCLK ; 2 cycles
djnz r6,Loop_0_3 ; 3 cycles
; Total = 15 cycles * 8 = 120
mov r0,a ; 1 cycle
; Total for two bytes = 123 cycles
Loop_1_4: ; etc
Loop_2_5: ; etc
; Total for six bytes = 369 cycles.
; At 24 MHz, 369 cycles is 15.375 us.
;
; Now let us imagine that is done and we have a four byte (signed) value at
ADC_A
; and we want to add the (sign extended) value at (R0,R1,R2) to it.
;
mov a,r0 ; 1 cycle
mov c,acc.7 ; 2 cycles
clr a ; 1 cycle
subb a,#0 ; 2 cycles
mov r7,a ; 1 cycle
;
; Now we have the value (R7,R0,R1,R2) to add to ADC_A
;
mov DPTR,#ADC_A ; 3 cycles
movx a,@DPTR ; 3 cycles
add a,r2 ; 1 cycle
movx @DPTR,a ; 3 cycles
inc DPTR ; 1 cycle
movx a,@DPTR ; 3 cycles
addc a,r1 ; 1 cycle
movx @DPTR,a ; 3 cycles
inc DPTR ; 1 cycle
movx a,@DPTR ; 3 cycles
addc a,r0 ; 1 cycle
movx @DPTR,a ; 3 cycles
inc DPTR ; 1 cycle
movx a,@DPTR ; 3 cycles
addc a,r7 ; 1 cycle
movx @DPTR,a ; 3 cycles
; Total cycles: 41 cycles
;
; So, to read both values in, and accumulate them, is 369+2*41 cycles, or
; 18.75 us.
;
; Of course, when this is debugged it may be found to take a bit longer.
;
#pragma endasm
}
Niklas Holsti
> Well, I have cobbled something together to get timing
...
> void ReadADS1251(void)
> {
> #pragma asm
...
> mov R6,#8 ; 2 cycles
> Loop_0_3:
> setb SCLK ; 2 cycles
Bill, I am curious to know which 8051 chip you assumed for your number
of cycles per each instruction. Can you tell us?
--
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
. @ .
Bill Davy
news:4afd649c$0$6254$4f79...@news.tdc.fi...
Hi,
Yes, I'm workng with a SiLab C8051F064. The clock is typically 24.5 MHz so
24.5 cycles per microsecond.
http://www.keil.com/dd/docs/datashts/silabs/c8051f06x.pdf (see page 126 for
clocks/instruction).
HTH,
Bill
Mark Moulding
"Bill Davy" <Bi...@SynectixLtd.com> wrote in message
news:7m4mt3F...@mid.individual.net...
>>
>> Yes.
>>
>> > Any gotchas?
>>
>> Time is money.
>>
>>
>> Vladimir Vassilevsky
>> DSP and Mixed Signal Design Consultanthttp://www.abvolt.com
>
> What Vladimir is trying to say is a project has 4 factors, quality,
> cost, time and experience.... changing only one of these factors
> effects the other factors
>
> Hence if you are in a hurry and have little experience and good
> quality is required.....expect to pay money for an answer or support
> from Vladimir.
>
> Joe
>
>
> ------------------------------
>
>
> In the past I have posted source code because when I started the Internet
> was a community not a marketplace. If Vladimir wishes to advertise his
> services or make snide remarks, perhaps he could find a different place (a
> kindergarten).
Vladimir seems to be a fairly regular poster here, and I seen several thing
go by to convince me that his "chops" are pretty substantial. He's given a
lot of advice to a lot of people here, for free. Conversely, he rarely
sugar-coats things, and if he chooses to charge for his time, that's OK with
me at least. Actually, I'm not sure (considering the brevity of his reply)
that he was rejecting your request outright...
--
Mark Moulding
Jon Kirwan
Seems that they can't be daisy-chained, so that is the only easy way
to go for two and minimum pin count to the micro.
>Oh, and no cahrge for this.
>
>Bill
I assume you have means by which you are elsewhere detecting the fact
that the data is indeed ready (examining /DRDY, clearly.)
><snip>
That approach seems fine and fast. Your total is slightly wrong,
though, isn't it? (The execution time for a pair of bytes from each
converter is 15*7+14+2+1 which equals 122 cycles, not 123. You forgot
that although the DJNZ is executed 8 times, one of those times it only
requires 2 cycles, not 3, since the jump doesn't take place.)
Some thoughts might be to also consider either an exact 50% duty cycle
for SCLK or else to arrange it so that the initial value of SCLK
before entering the loop doesn't matter (allowing you to 'play', if
you want.)
Shooting for 50% SCLK duty cycle requires an extra cycle per loop. In
this case:
.
.
.
; Assume DOR_A and DOR_B are valid upon entry.
; SCLK assumed LOW to start and is operated at
; a very clean 50% duty cycle (8 cycles low
; and 8 cycles high.)
mov r7, #8 ; reserved for bottom byte loop
mov r6, #8 ; used for top and middle byte loops
top_loop:
mov c, DOR_A
rlc a
setb SCLK
xch a, r3
mov c, DOR_B
rlc a
xch a, r3
mov r0, a
clr SCLK
djnz r6, top_loop
mov r6, #8
mid_loop:
mov c, DOR_A
setb SCLK
rlc a
xch a, r4
mov c, DOR_B
rlc a
xch a, r4
clr SCLK
mov r1, a
djnz r6, mid_loop
bot_loop:
mov c, DOR_A
rlc a
setb SCLK
xch a, r5
mov c, DOR_B
rlc a
xch a, r5
mov r2, a
clr SCLK
djnz r7, bot_loop
.
.
.
Whether or not you actually care about a clean 50% duty cycle is
another matter, of course.
If not, perhaps changing things so that the initial value of SCLK
before entering the loop doesn't matter:
; Assume DOR_A and DOR_B are valid upon entry.
; Initial value of SCLK doesn't matter and the
; duty cycle is close to 33%/66%.
mov r6, #8
top_loop:
mov c, DOR_A
rlc a
mov c, DOR_B
cpl SCLK
xch a, r3
rlc a
xch a, r3
cpl SCLK
djnz r6, top_loop
mov r0, a
.
.
.
Not much different, really. And your initial code was just fine. Just
some minor twists on what you've already done.
Jon
Bill Davy
news:3lurf55nvfa5j2q2r...@4ax.com...
Thanks for that input Jon and I am grateful to hear you say I am on the
right track. There is no pressure on a 50% duty cycle, so we will see how
it works. I must admit I seldom worry about the DJNZ being 2 once as in
reality things are not going to work if that matters (it allows me an error
in the other direction elsewhere).
There are some shenanigans about holding DOUT for some fairly precise number
of cycles to force devices sharing SCLK to fall into synchronisation.
That's going to be another stage of the battle.
I was hoping TI (or someone) would have done this for n*ADS1251 sharing an
SCLK. Hopefully, when I have done it (if, works, etc) I will post a copy
here for the record.
Regards,
Bill
Jon Kirwan
wrote:
>><snip>
>> Not much different, really. And your initial code was just fine. Just
>> some minor twists on what you've already done.
>>
>> Jon
>
>Thanks for that input Jon and I am grateful to hear you say I am on the
>right track. There is no pressure on a 50% duty cycle, so we will see how
>it works.
Sometimes, I want to retain as close to 50% in the clock's duty cycle
as I can. I gather than an asymmetric duty cycle introduces somewhat
larger spurs near the primary frequency and, since it is in control of
the software here, why not do that little bit extra?
Hajimiri and Lee have written a lot on similar subjects for a decade.
Nicely, much of their work can be downloaded and read from here:
http://en.scientificcommons.org/ali_hajimiri
I agree it probably doesn't impact anything you are doing. But as a
matter of general practice I try and stay on the straight and narrow,
other things equal.
>I must admit I seldom worry about the DJNZ being 2 once as in
>reality things are not going to work if that matters (it allows me an error
>in the other direction elsewhere).
Well, it matters at times. Not just in the case where you might
actually want to consider controlling the duty cycle precisely. But
also in other cases of communications between asynchronously clocked
cpus, as one example, where the precise control of the exact cycle
count in alternating branches/edges of code can be used to advantage.
Again, it has no real impact on what you are doing. But I like to get
my numbers right 'all the time' so that things are less likely to slip
by my notice when I really do care more.
[Not unlike making sure you maintain a consistent skill adding
numbers. More often than not, it's not important that you can add
because you can just roughly "know" you are in the ballpark. But if
you don't develop and maintain the skill by routine practice, it can
bite you in some cases when it may really count for something.]
>There are some shenanigans about holding DOUT for some fairly precise number
>of cycles to force devices sharing SCLK to fall into synchronisation.
>That's going to be another stage of the battle.
I remember reading about synchronization in the datasheet. What
bothers me about what I gathered from glanced over it, including
figure 13, is that it wasn't clear to me exactly how the device
"knows" how many cycles that SCLK is being held high. (I think it was
SCLK and _not_ DOUT, but maybe that's where I'm screwed up?) The only
other input I can think of is CLK, so I guessed back then that SCLK
needed to be held high for some fixed number of CLKs. But since you
aren't controlling that, different devices may have different CLKs,
and may not have access to them anyway, that leaves me wondering about
the whole process. Can you clear that up for me? That was the one
thing bothering me about what I took away scanning quickly over the
datasheet (without reading more than the occasional paragraph.)
>I was hoping TI (or someone) would have done this for n*ADS1251 sharing an
>SCLK. Hopefully, when I have done it (if, works, etc) I will post a copy
>here for the record.
Always good to have stuff posted up. I'm currently using an F061,
myself. But I'm using the high speed ADC in it. I get substantially
more equivalent bits than 16, but only by processing well more than
1000 data points at a time. Different thing, so I can luckily just
use the DMA. (And I don't need an external bus interface.)
Jon
Bill Davy
System clock is always running.
4*Tdrdy < [SCLK=1] < 20 * Tdrdy => Reset and synchronise
20 * Tdrdy < [SCLK=1] => power down mode
Counting exact cycles is always a bit risky when interrupts are running but
I take your point about asymmetry spreading the noise spectrum.
Jon Kirwan
wrote:
><BIG SNIP OF EVERYTHING>
>System clock is always running.
I know.
>4*Tdrdy < [SCLK=1] < 20 * Tdrdy => Reset and synchronise
Okay. Since Tdrdy is based upon CLK, I was right to imagine that had
to be the driving element. I seem to recall that the documentation
said that the SCLK period needs to be about 5 of those, not 4, just to
be on the safe side since the devices may be in varying states of
conversion.
>20 * Tdrdy < [SCLK=1] => power down mode
That much I did understand from the text, except at the time I didn't
know about, but suspected, the Tdrdy dependence.
>Counting exact cycles is always a bit risky when interrupts are running
Yes. However, in sensitive equipment where that matters (and I've
worked on a few), I keep uncontrolled, asynchronous external
interrupts excluded. This means I _know_, a priori, when interrupts
may take place and synchronize the execution of such fragments of code
aligned to interrupt events I now control such that I can assure
myself that they cannot occur during its execution. This still allows
things like a pacing timer to operate. I just make sure that the pace
is wide enough to accomodate the execution time of something like this
or else _live_ with the problem, I suppose. Or use a hardware
resource to drive SCLK.
>but I take your point about asymmetry spreading the noise spectrum.
I really don't know that it matters. Just thought I'd call attention
and let you think about it. Some folks _do_ worry about it enough to
do things a little differently than they otherwise would.
Jon