Abstracts for new neural network patents
Gregory Aharonian
The following is my periodic posting of the abstracts and stat data
for new neural network patents. The full text and diagrams of any of these
patents can be ordered from the patent office for $3 in printed form. Also,
for $20, I will provide a machine readable version of the abstract, text,
claims and references for any neural network patent.
Greg Aharonian
Source Translation & Optimization
src...@world.std.com
617-489-3727
=============================================================================
For a very good article on the legal issues involving neural network
patents, see the article "Intellectual Property Protection for Neural
Networks" by Donald Wenskay, Neural Networks, 3, pp. 229-236, 1990.
=============================================================================
For those interested in applying for a neural network patent, I freely
provide a LaTeX template for a patent application. Please email a request,
and I'll send it to you. Contains most of the boilerplate you need.
=============================================================================
To date, I have yet to see any articles in the trade journals on either
companies signing cross-licensing agreements to share their neural network
patents, or patent infringement lawsuits dealing with neural network patents.
To me, this means that no one is making much money with neural networks (other
than selling software), and that the financial return on acquiring a patent
is less than the cost of applying for and maintaining a patent.
If anyone hears of either occurrence, please let me know.
=============================================================================
==============================================================================
5,166,539 [IMAGE AVAILABLE] Nov. 24, 1992
Neural network circuit
INVENTOR: Kuniharu Uchimura, Kanagawa, Japan
Osamu Saito, Kanagawa, Japan
Yoshihito Amemiya, Tokyo, Japan
Atsushi Iwata, Tokyo, Japan
ASSIGNEE: Nippon Telegraph and Telephone Corporation, Tokyo, Japan
APPL-NO: 07/727,065
DATE FILED: Jul. 8, 1991
INT-CL: [5] H03K 19/08
US-CL-ISSUED: 307/201, 464
US-CL-CURRENT: 307/201, 464
SEARCH-FLD: 307/201, 464, 465; 364/513, 807; 395/21-24
ART-UNIT: 252
PRIM-EXMR: Eugene R. LaRoche
ASST-EXMR: A. Zarabian
LEGAL-REP: Finnegan, Henderson Farabow, Garrett and Dunner
ABSTRACT:
A neural network circuit, in which a number n of weight coefficients (Wl-wn)
corresponding to a number n of inputs are provided, subtraction circuits
determine the difference between inputs and the weight coefficients in each
input terminal, the result thereof is inputted into absolute value circuits,
all calculation results of the absolute value circuts corresponding to the
inputs and the weight coefficients are inputted into an addition circuit and
accumulated, and this accumulation result determines the output value. The
threshold value circuit, which determines the final output value, has
characteristics of a step function pattern, a polygonal line pattern, or a
sigmoid function pattern, depending on the object. In the case in which a
neural network circuit is realized by means of digital circuits, the absolute
value circuits can comprise simply EX-OR logic (exclusive OR) gates.
Furthermore, in the case in which the input terminals have two input paths
and two weight coefficients corresponding to each input path, the neuron
circuits form a recognition area having a flexible shape which is controlled
by the weight coefficients. Neuron circuits are widely used in pattern
recognition; neuron circuits react to a pattern inputted into the input layer
and recognition is thereby conducted.
5 Claims, 40 Drawing Figures
==============================================================================
5,166,896 [IMAGE AVAILABLE] Nov. 24, 1992
Discrete cosine transform chip using neural network concepts for calculating
values of a discrete cosine transform function
INVENTOR: Ho-Sun Jeong, Taegu, Republic of Korea
Je-kwang Ryu, Taegu, Republic of Korea
ASSIGNEE: Samsung Electronics Co., Ltd., Kyunggi-do, Republic of Korea
APPL-NO: 07/659,089
DATE FILED: Feb. 22, 1991
FRN-PRIOR: Republic of Korea 90-4513 Apr. 3, 1990
INT-CL: [5] G06F 7/38
US-CL-ISSUED: 364/725
US-CL-CURRENT: 364/725
SEARCH-FLD: 364/725, 748, 768, 754; 395/21
ART-UNIT: 236
PRIM-EXMR: Long T. Nguyen
LEGAL-REP: Cushman, Darby & Cushman
ABSTRACT:
A discrete cosine transform chip includes circuits using neural network
concepts that have parallel processing capability as well as conventional
digital logic circuits. In particular, the discrete cosine transform chip
includes a cosine term processing portion, a multiplier, an adder, a
subtractor, and two groups of latches. The multiplier, the adder and the
subtractor incorporated in the discrete cosine transform chip use
unidirectional feed back neural network models.
12 Claims, 10 Drawing Figures
==============================================================================
5,166,927 [IMAGE AVAILABLE] Nov. 24, 1992
Adaptive pathfinding neutral network for a packet communication system
INVENTOR: Ichiro Iida, Yokohama, Japan
Akira Chugo, Tokyo, Japan
ASSIGNEE: Fujitsu Limited, Kanagawa, Japan
APPL-NO: 07/455,323
DATE FILED: Mar. 6, 1990
PCT-FILED: Jul. 6, 1989
PCT-NO: PCT/JP89/00684
371-DATE: Mar. 6, 1990
102(E)-DATE: Mar. 6, 1990
PCT-PUB-NO: WO90/00842
PCT-PUB-DATE: Jan. 25, 1990
INT-CL: [5] H04Q 11/04
US-CL-ISSUED: 370/60, 94.1, 94.3, 54; 395/21
US-CL-CURRENT: 370/60, 54, 94.1, 94.3; 395/21
SEARCH-FLD: 370/94.1, 95.3, 16, 60, 94.3, 54, 79; 395/22, 21
ART-UNIT: 263
PRIM-EXMR: Douglas W. Olms
ASST-EXMR: Shick Hom
LEGAL-REP: Staas & Halsey
ABSTRACT:
An adaptive routing system is used in a network for performing a
communication in a packet form obtained by adding address data and data
length to the transmission information. This connects nodes having input
ports and output ports arranged in a distributed manner, by the input link
and output link. This system enables the network to assign the neuron
elements to input ports and output ports of respective nodes one by one,
inputs a network state to the neuron element to evaluate the traffic
condition of the network and determines the output port assigned to the
neuron element having the "1" output from among the neuron elements assigned
to the output ports of the respective nodes when the outputs of respective
neuron elements are not changed after reaching the balanced state, thereby
enabling the output of said output port to be produced in the optimum output
direction of the packet from respective nodes.
64 Claims, 39 Drawing Figures
==============================================================================
5,166,938 [IMAGE AVAILABLE] Nov. 24, 1992
Error correction circuit using a design based on a neural network model
comprising an encoder portion and a decoder portion
INVENTOR: Ho-Sun Chung, Taegu, Republic of Korea
ASSIGNEE: Samsung Electronics Co., Ltd., Kyunggi, Republic of Korea
APPL-NO: 07/549,931
DATE FILED: Jul. 9, 1990
FRN-PRIOR: Republic of Korea 90-9552 Jun. 27, 1990
INT-CL: [5] G06F 11/08
US-CL-ISSUED: 371/37.1; 395/27
US-CL-CURRENT: 371/37.1; 395/27
SEARCH-FLD: 395/27, 24, 22; 371/37.1
ART-UNIT: 233
PRIM-EXMR: Robert W. Beausoliel
ASST-EXMR: Henry C. Lebowitz
LEGAL-REP: Cushman, Darby & Cushman
ABSTRACT:
An error correction circuit is provided which uses NMOS and PMOS synapses to
form network type responses to a coded multi-bit input. Use of MOS technology
logic in error correction circuits allows such devices to be easily
interfaced with other like technology circuits without the need to use
distinct interface logic as with conventional error correction circuitry.
4 Claims, 22 Drawing Figures
==============================================================================
5,167,006 [IMAGE AVAILABLE] Nov. 24, 1992
Neuron unit, neural network and signal processing method
INVENTOR: Toshiyuki Furuta, Yokohama, Japan
Hiroyuki Horiguchi, Yokohama, Japan
Hirotoshi Eguchi, Yokohama, Japan
Yutaka Ebi, Yokohama, Japan
Tatsuya Furukawa, Yokohama, Japan
Yoshio Watanabe, Kawasaki, Japan
Toshihiro Tsukagoshi, Itami, Japan
ASSIGNEE: Ricoh Company, Ltd., Japan
APPL-NO: 07/629,632
DATE FILED: Dec. 18, 1990
INT-CL: [5] G06F 15/18
US-CL-ISSUED: 395/11, 27
US-CL-CURRENT: 395/11, 27
SEARCH-FLD: 395/24, 26, 27, 11
ART-UNIT: 238
PRIM-EXMR: Allen R. MacDonald
LEGAL-REP: Mason, Fenwick & Lawrence
ABSTRACT:
A neuron unit processes a plurality of input signals and outputs an output
signal which is indicative of a result of the processing. The neuron unit
includes input lines for receiving the input signals, a forward process part
including a supplying part for supplying weight functions and an operation
part for carrying out an operation on each of the input signals using one of
the weight functions and for outputting the output signal, and a
self-learning part including a generating part for generating new weight
functions based on errors between the output signal of the forward process
part and teaching signals and a varying part for varying the weight functions
supplied by the supplying part of the forward process part to the new weight
functions generated by the generating part.
72 Claims, 76 Drawing Figures
==============================================================================
5,167,007 [IMAGE AVAILABLE] Nov. 24, 1992
Multilayered optical neural network system
INVENTOR: Haruyoshi Toyoda, Fukuroi, Japan
ASSIGNEE: Hamamatsu Photonics K.K., Japan
APPL-NO: 07/598,173
DATE FILED: Oct. 12, 1990
FRN-PRIOR: Japan 1-269718 Oct. 17, 1989
INT-CL: [5] G06F 15/18
US-CL-ISSUED: 395/25
US-CL-CURRENT: 395/25
SEARCH-FLD: 364/513; 395/25
ART-UNIT: 238
PRIM-EXMR: Allen R. MacDonald
LEGAL-REP: Oliff & Berridge
ABSTRACT:
A multilayered optical neural network system comprise an input layer, an
output layer, at least one hidden layer provided between the input layer and
the output layer, a memory matrix holding device provided between the
respective layers for holding weighted couplings between the layers, a
correlation operating device for optically computing a correlation between an
output optical pattern from the previous layer and the memory matrix pattern,
an output function operating device for implementing optical computing of an
output function corresponding to a result of the correlation operation, and a
memory matrix correcting device provided between the respective layers for
optically correcting a memory matrix held in the memory matrix holding device
by a learning operation, whereby the system is capable of two-dimensional
optical computing of all data transfers and operations and executing a great
amount of computing without use of holograms.
9 Claims, 26 Drawing Figures
==============================================================================
5,167,008 [IMAGE AVAILABLE] Nov. 24, 1992
Digital circuitry for approximating sigmoidal response in a neural network
layer
INVENTOR: William E. Engeler, Scotia, NY
ASSIGNEE: General Electric Company, Schenectady, NY
APPL-NO: 07/752,290
DATE FILED: Aug. 29, 1991
REL-US-DATA: Division of Ser. No. 628,257, Dec. 14, 1990, Pat. No.
5,115,492, May 19, 1992.
INT-CL: [5] G06F 15/18
US-CL-ISSUED: 395/27; 364/715.01, 602; 395/24
US-CL-CURRENT: 395/27; 364/602, 715.01; 395/24
SEARCH-FLD: 395/27, 24; 364/715.01, 716, 729, 602
ART-UNIT: 238
PRIM-EXMR: Michael R. Fleming
ASST-EXMR: Robert W. Downs
LEGAL-REP: Marvin Snyder
ABSTRACT:
A plurality of neural circuits are connected in a neural network layer for
generating their respective digital axonal responses to the same plurality of
synapse input signals. Each neural circuit includes digital circuitry for
approximating a sigmoidal response connected after respective circuitry for
performing a weighted summation of the synapse input signals to generate a
weighted summation result in digital form. In this digital circuitry the
absolute value of the digital weighted summation result is first determined.
Then, a window comparator determines into which of a plurality of amplitude
ranges the absolute value of the weighted summation result falls. A digital
intercept value and a digital slope value are selected in accordance with the
range into which the absolute value of the weighted summation result falls.
The absolute value of the digital weighted summation result is multiplied by
the selected digital slope value to generate a digital product; and the
digital intercept value is added to the digital product to generate an
absolute value representation of a digital axonal response. The polarity of
the weighted summation result is determined, and the same polarity is
assigned to the absolute value representation of the digital axonal response,
thereby to generate the digital axonal response.
4 Claims, 38 Drawing Figures
==============================================================================
5,167,009 [IMAGE AVAILABLE] Nov. 24, 1992
On-line process control neural network using data pointers
INVENTOR: Richard D. Skeirik, Newark, DE
ASSIGNEE: E. I. Du Pont de Nemours & Co. (Inc.), Wilmington, DE
APPL-NO: 07/562,388
DATE FILED: Aug. 3, 1990
INT-CL: [5] G06F 15/18
US-CL-ISSUED: 395/27, 22, 68, 11, 906
US-CL-CURRENT: 395/27, 11, 22, 68, 906
SEARCH-FLD: 364/513, 148, 149, 150, 151, 164, 165, 807, 200, 474.15, 500,
501, 502, 503; 395/22, 26, 27, 906, 907, 914, 915, 11, 68
ART-UNIT: 238
PRIM-EXMR: Allen R. MacDonald
LEGAL-REP: Sterne, Kessler, Goldstein & Fox
ABSTRACT:
An on-line process control neural network using data pointers allows the
neural network to be easily configured to use data in a process control
environment. The inputs, outputs, training inputs and errors can be retrieved
and/or stored from any available data source without programming. The user of
the neural network specifies data pointers indicating the particular computer
system in which the data resides or will be stored; the type of data to be
retrieved and/or stored; and the specific data value or storage location to
be used. The data pointers include maximum, minimum, and maximum change
limits, which can also serve as scaling limits for the neural network. Data
pointers indicating time-dependent data, such as time averages, also include
time boundary specifiers. The data pointers are entered by the user of the
neural network using pop-up menus and by completing fields in a template. An
historical database provides both a source of input data and a storage
function for output and error data.
24 Claims, 34 Drawing Figures
--
**************************************************************************
Greg Aharonian
Source Translation & Optimiztion
P.O. Box 404, Belmont, MA 02178