We're very excited to announce our second public release of chisel. Chisel is a hardware construction language embedded in the high-level programming language Scala. Since our dac12 talk and bootcamp we've improved ease of use, expressivity, and performance. Also in this release is a set of educational processors, which are substantial examples of Chisel code.
Our Chisel website is:
In the future, we plan to provide more frequent stable releases as jarfiles, but you can always get instant access to the github repository:
g...@github.com:ucb-bar/chisel.git
Please subscribe to our discussion group:
Finally, in order to further improve chisel, we'd appreciate people taking a chisel survey which is available from:
Some details of improvements are listed below:
ease of use
o verilog works with new test harness
o cleaned up tutorials
o check for unimplemented clone methods
o add pictures for describing all mechanisms (as part of cs250 lectures)
o jarfile release
o swap ordering of INPUT/OUTPUT and width
o better error message
o running on windows under Cygwin
o improve modified BSD license
expressivity
o add bulk type support for mems
o more reusable components -- arbiters, queues, counter, pipe, prioritymux, priorityencoderOH
o user defined backends
performance
o 5x improvement in C++ compile time
o speed up C++ mems
o improve FPGA backend
o slim down memory usage