Groups
Sign in
Groups
chisel-users
Conversations
About
Send feedback
Help
chisel-users
Contact owners and managers
1–30 of 1010
Mark all as read
Report group
0 selected
Martin Schoeberl
Apr 25
DSD Special Session on Chisel
Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the
unread,
DSD Special Session on Chisel
Hi all, this is a gently reminder for a submission of a paper to the special session on Chisel at the
Apr 25
Martin Schoeberl
Apr 22
DSD special session on Chisel
Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more
unread,
DSD special session on Chisel
Dear all, this is a reminder to submit papers to the special session on Chisel at DSD 2024. See more
Apr 22
Nick Gian
Apr 16
Is chisel supporting blackbox for .systemVerilog?
Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.
unread,
Is chisel supporting blackbox for .systemVerilog?
Dear Community, Is chisel support .sv files as blackbox? if yes what version of chisel?.
Apr 16
Martin Schoeberl
Apr 8
Chisel projects on Tiny Tapeout 06
Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny
unread,
Chisel projects on Tiny Tapeout 06
Hi all, it is time for Chisel to get Tiny. A Chisel template is available, just in time, for Tiny
Apr 8
Øyvind Harboe
Apr 2
BoringUtils.bore() is depricated, example of how to translate into modern speak?
Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax
unread,
BoringUtils.bore() is depricated, example of how to translate into modern speak?
Silly question: is there an example somewhere of how to switch BoringUtils.bore() deprecated syntax
Apr 2
Nick Gian
Mar 27
Chisel 5 and blackbox an .SV
Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files
unread,
Chisel 5 and blackbox an .SV
Can chisel (v5) handle blackbox as .sv files? because i only found examples with .v files
Mar 27
Øyvind Harboe
,
Øystein Hovind
3
Mar 6
Scala 3 and Chisel
Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig
unread,
Scala 3 and Chisel
Thanks! On Wednesday, March 6, 2024 at 10:28:57 AM UTC+1 oys...@ascenium.com wrote: Jack Koenig
Mar 6
Nick Gian
,
Martoni
5
Feb 27
How to use floating point & fixed point
I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to
unread,
How to use floating point & fixed point
I have run the generating stuff but i want to run a chisel test in hardfloat. Can you help me how to
Feb 27
Nick Gian
Feb 27
Can ChiselTest generate testbench verilog file?
Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?
unread,
Can ChiselTest generate testbench verilog file?
Hello chisel community, Can chiselTest generate testbench verilog file? lf yes how?
Feb 27
Nick Gian
Feb 12
I want to compile and use FixedPoint & hardFloat for every project
I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?
unread,
I want to compile and use FixedPoint & hardFloat for every project
I am using Chisel 3.6 and i want to use those 2 https://github.com/ucb-bar/fixedpoint/tree/chisel6?
Feb 12
qwer trump (zsjj)
, …
Dmitry Belimov
4
Feb 4
chiseltest failed on chisel 6.0
Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this
unread,
chiseltest failed on chisel 6.0
Hi All, Is it possible to transform Chisel code to C++ sources without iverilator? Why I ask this
Feb 4
chiselStudent
Jan 23
verilog output with Chisel v5.1.0
I am using the chisel-template gcd module and see that I can generate a system verilog file. using:
unread,
verilog output with Chisel v5.1.0
I am using the chisel-template gcd module and see that I can generate a system verilog file. using:
Jan 23
Martin Schoeberl
Jan 23
bit order on asUInt
Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =
unread,
bit order on asUInt
Hi all, I am wondering why the mapping of a Vec to UInt is different from mapping a Bundle: val vec =
Jan 23
Ruige Lee
Jan 22
Black-Box files cannot generate in one verilog files, when using chisel5
Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in
unread,
Black-Box files cannot generate in one verilog files, when using chisel5
Hello, I am trying to bump from chisel 3.5.6 to chisel5. However, when I try to generate all code in
Jan 22
Madhava Krishna
,
Ruige Lee
3
Jan 22
Chisel 5.0.0: Provider firrtl.passes.memlib.MemLibOptions not found
Thanks, deleting the file worked. BTW, generating a .fir file using ChiselStage.emitCHIRRTL and then
unread,
Chisel 5.0.0: Provider firrtl.passes.memlib.MemLibOptions not found
Thanks, deleting the file worked. BTW, generating a .fir file using ChiselStage.emitCHIRRTL and then
Jan 22
Saltuk Akgül
Jan 3
Naming of modules
Hi everyone, I want to fix names of my modules. Not instance names but module names and generated
unread,
Naming of modules
Hi everyone, I want to fix names of my modules. Not instance names but module names and generated
Jan 3
Martin Schoeberl
,
Schuyler Eldridge
7
12/11/23
Chisel 3.6
OK, that compiled. Thanks, Martin On 11.12.2023, at 17:46, Schuyler Eldridge <schuyler.eldridge@
unread,
Chisel 3.6
OK, that compiled. Thanks, Martin On 11.12.2023, at 17:46, Schuyler Eldridge <schuyler.eldridge@
12/11/23
Gemma Tuner
12/7/23
Xforce Keygen 64-bit Inventor 2010 Keygen
Xforce Keygen 64-bit Inventor 2010 Keygen Download https://urlca.com/2wJ2Sf eebf2c3492
unread,
Xforce Keygen 64-bit Inventor 2010 Keygen
Xforce Keygen 64-bit Inventor 2010 Keygen Download https://urlca.com/2wJ2Sf eebf2c3492
12/7/23
Arsh G
12/7/23
Re: Digest for chisel-users@googlegroups.com - 3 updates in 1 topic
Thanks to both of you :)) The help was much appreciated. On Tue, 5 Dec 2023 at 19:17, <chisel-
unread,
Re: Digest for chisel-users@googlegroups.com - 3 updates in 1 topic
Thanks to both of you :)) The help was much appreciated. On Tue, 5 Dec 2023 at 19:17, <chisel-
12/7/23
Ina Tankesly
12/6/23
Nee Manasu Naaku Telusu [2003 €? FLAC]
Nee Manasu Naaku Telusu [2003 FLAC] Download File https://t.co/mZoAiKB8Xb eebf2c3492
unread,
Nee Manasu Naaku Telusu [2003 €? FLAC]
Nee Manasu Naaku Telusu [2003 FLAC] Download File https://t.co/mZoAiKB8Xb eebf2c3492
12/6/23
Ina Tankesly
12/6/23
Bhoothnath Returns Movie All Songs Download
download Bhootnath 2 Songs unlimited Movies and videos Download Here.Bhootnath 2 Songs Hd,3gp. mp4
unread,
Bhoothnath Returns Movie All Songs Download
download Bhootnath 2 Songs unlimited Movies and videos Download Here.Bhootnath 2 Songs Hd,3gp. mp4
12/6/23
Ina Tankesly
12/6/23
Rizzato Nunes Direito Do Consumidor Pdf Download
Já a boa-fé objetiva, que é a que está presente no CDC,pode ser definida, grosso modo, como uma regra
unread,
Rizzato Nunes Direito Do Consumidor Pdf Download
Já a boa-fé objetiva, que é a que está presente no CDC,pode ser definida, grosso modo, como uma regra
12/6/23
Ina Tankesly
12/6/23
Cf Auto Root Apk Download Now V1.1 (updated)
Rooting gives access to the advantages of installing updates, improving overall speed and battery
unread,
Cf Auto Root Apk Download Now V1.1 (updated)
Rooting gives access to the advantages of installing updates, improving overall speed and battery
12/6/23
Ina Tankesly
12/6/23
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest]
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest] Download Zip https://t.co/1tqDr2FgWz
unread,
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest]
ESET NOD32 ANTIVIRUS 2019 Crack License Key Full [Latest] Download Zip https://t.co/1tqDr2FgWz
12/6/23
Ina Tankesly
12/6/23
Activator For Windows And Office KMS Pico V10.1 Free Download
Activator For Windows And Office KMS Pico V10.1 Free Download DOWNLOAD https://t.co/YYCiVcEriJ
unread,
Activator For Windows And Office KMS Pico V10.1 Free Download
Activator For Windows And Office KMS Pico V10.1 Free Download DOWNLOAD https://t.co/YYCiVcEriJ
12/6/23
Ina Tankesly
12/6/23
IMyFone Umate Pro 6.0.0.7 With Crack
iMyFone Umate Pro 6.0.0.7 with Crack Download Zip https://t.co/bhp8tYulao eebf2c3492
unread,
IMyFone Umate Pro 6.0.0.7 With Crack
iMyFone Umate Pro 6.0.0.7 with Crack Download Zip https://t.co/bhp8tYulao eebf2c3492
12/6/23
Arsh G
, …
Kevin Laeufer
3
12/5/23
Duplicating of Modules
Something that might also be worth trying is: val Y = (0 until n).map(_ => Module(new Y(proto= ...
unread,
Duplicating of Modules
Something that might also be worth trying is: val Y = (0 until n).map(_ => Module(new Y(proto= ...
12/5/23
Chin Tsai
,
Jack Koenig
2
11/16/23
Generate verilog file with different file name
Hello, You can use command-line argument -o. Since you're using class chisel3.stage.ChiselStage,
unread,
Generate verilog file with different file name
Hello, You can use command-line argument -o. Since you're using class chisel3.stage.ChiselStage,
11/16/23
Jack Koenig
11/16/23
Chisel v5.1.0 has been released!
Howdy Chiselers, I am very delighted to announce that we have released v5.1.0 of Chisel: https://
unread,
Chisel v5.1.0 has been released!
Howdy Chiselers, I am very delighted to announce that we have released v5.1.0 of Chisel: https://
11/16/23
Burkhard Steinmacher-Burow
11/9/23
A Chisel job posting – Develop a new CPU fabric architecture
Hi all, The previous job posting here was in 2021, so I hope it's now okay to post another. :-) I
unread,
A Chisel job posting – Develop a new CPU fabric architecture
Hi all, The previous job posting here was in 2021, so I hope it's now okay to post another. :-) I
11/9/23