Patch for fixing the nand hw mode write - Patch(1/1)

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Pillai, Manikandan

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Sep 5, 2008, 4:51:43 AM9/5/08
to beagl...@googlegroups.com

Hi all,

 

Pls find a patch attached to fix the issue of nand hw mode. This will enable the upload of x-loader from u-boot.

I have also upgraded the prompt for onenand since they were given as start and end address and not as offsets.

 

Pls let me know if you have any comments.

 

 

Regards

-------------------------------------------------------------------

Manikandan Pillai

BCG-PSP Project Lead 

(Type "pspproducts" in you web browser for PSP info)

http://dbdwss01.india.ti.com/pspproducts/

PSP downloads at : http://software.ti.com/swcoe/intranet/reports/pds/PSP_releases.php

Office : +91-80-25048069

-------------------------------------------------------------------

 

u-boot-nand-hw-p1.txt

Steve Sakoman

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Sep 5, 2008, 7:24:20 PM9/5/08
to beagl...@googlegroups.com, Pillai, Manikandan
On Fri, Sep 5, 2008 at 1:51 AM, Pillai, Manikandan <mani....@ti.com> wrote:
> Pls find a patch attached to fix the issue of nand hw mode. This will enable
> the upload of x-loader from u-boot.
>
> I have also upgraded the prompt for onenand since they were given as start
> and end address and not as offsets.
>
> Pls let me know if you have any comments.

Thanks for your patch submission!

A few comments:

1. It would be better if you didn't bundle your patches into one
email/file. I have to separate them by hand before I can apply them
and this increases the chance of something getting screwed up. In
this case a nand patch and a onenand patch would have been
appropriate.

2. Keep each patch/email to a separate chunk of functionality. That
way people can comment on each individually.

3. Patches that aren't omap specific (like the onenand patch) should
go directly to the u-boot mailing list for consideration.

4. It makes sense to include the nand ecc changes in this u-boot git
repo because they are omap specific and can't really be pushed
upstream until we push the board files. I will attempt to separate
those out by hand and apply them. I'll let you know if I run into any
difficulties.

Best regards,

Steve

Dirk Behme

unread,
Sep 6, 2008, 4:16:12 AM9/6/08
to Pillai, Manikandan, beagl...@googlegroups.com, Syed Mohammed, Khasim
Pillai, Manikandan wrote:
> Hi all,
>
> Pls find a patch attached to fix the issue of nand hw mode. This will
> enable the upload of x-loader from u-boot.
>
> I have also upgraded the prompt for onenand since they were given as
> start and end address and not as offsets.
>
> Pls let me know if you have any comments.

Many thanks for the patch!

Besides Steve's comments, some additional remarks:

- Do you like to have a look to

http://wiki.davincidsp.com/index.php?title=Patch_upstream_sending#Patch_rules

?

With increasing traffic at this list, it would be really helpful if
you like to improve your subjects to add something like [PATCH] at
subject beginning. It would help to recognize patches at list.

- It would be nice if you could add patch description to patch
(attachment), too. Not only to mail text. And, additionally, being a
little more specific in patch description would help, too. "to fix the
issue" isn't really specific. I had to look into patch changes to get
an idea what this patch is about.

- Do you have a Beagle (NAND) board, now? If not, maybe Khasim can
help? Would be helpful if your patches are not only for one board but
for all OMAP3 boards we currently support. Ok, nobody except Steve has
overo, yet ;)

Many thanks for your help

Dirk


Pillai, Manikandan

unread,
Sep 9, 2008, 7:29:08 AM9/9/08
to Dirk Behme, beagl...@googlegroups.com, Syed Mohammed, Khasim
Hi all,

Pls find a patch which provides a changes for a single binary image for OMAP3
for NAND/Onenand based boards. I have added a description of the patch at the start of the file.

I was not sure whether to send this patch to this list or the u-boot list but
Since the single image is currently there for OMAP3 I am sending it to this list.

Note: While applying this patch, depending on whether the previous patch is applied, you might have warning for nand_base.c which you can ignore.

Pls let me know your comments.

Regards
Mani

http://wiki.davincidsp.com/index.php?title=Patch_upstream_sending#Patch_rules

?

Mani>>> I have a beagle board now. I have tested it to see if it comes up on
Beagle and it looks fine.

u-boot-single-bin-p1.txt

Pillai, Manikandan

unread,
Sep 22, 2008, 2:17:49 AM9/22/08
to beagl...@googlegroups.com

Hi all,

Pls ignore the patches which have been sent for single binary image for NAND and OneNAND flashes. I will generate them again against the common branch and resend them.

In this patch, I am fixing some compilation bugs for jffs2 arising out of the upstream changes in nand header files and adding a default mux configuration for
EVM that support some display configuration.

Pls send in your comments for the same. I am in the process of generating the
Single binary image patch )based on a similar approach for the patch I sent a few days back).

Regards
Mani


-----Original Message-----
From: Pillai, Manikandan
Sent: Tuesday, September 09, 2008 4:59 PM
To: 'Dirk Behme'
Cc: beagl...@googlegroups.com; Syed Mohammed, Khasim

Subject: [PATCH] - Single binary image for NAND/OneNAND based OMAP3 board(Patch1/1)

Hi all,

Pls find a patch which provides a changes for a single binary image for OMAP3


for NAND/Onenand based boards. I have added a description of the patch at the start of the file.

I was not sure whether to send this patch to this list or the u-boot list but
Since the single image is currently there for OMAP3 I am sending it to this list.

Note: While applying this patch, depending on whether the previous patch is applied, you might have warning for nand_base.c which you can ignore.

Pls let me know your comments.

Regards
Mani

-----Original Message-----
From: Dirk Behme [mailto:dirk....@googlemail.com]
Sent: Saturday, September 06, 2008 1:46 PM
To: Pillai, Manikandan
Cc: beagl...@googlegroups.com; Syed Mohammed, Khasim
Subject: Re: [beagleboard] Patch for fixing the nand hw mode write - Patch(1/1)

http://wiki.davincidsp.com/index.php?title=Patch_upstream_sending#Patch_rules

?

Mani>>> I have a beagle board now. I have tested it to see if it comes up on
Beagle and it looks fine.

Many thanks for your help

Dirk

u-boot-mux-p1.txt

Koen Kooi

unread,
Sep 22, 2008, 10:25:32 AM9/22/08
to Beagle Board
On 22 sep, 08:17, "Pillai, Manikandan" <mani.pil...@ti.com> wrote:
> Hi all,
>
> Pls ignore the patches which have been sent for single binary image for NAND and OneNAND flashes. I will generate them again against the common branch and resend them.
>
> In this patch, I am fixing some compilation bugs for jffs2 arising out of the upstream changes in nand header files and adding a default mux configuration for
> EVM that support some display configuration.

Could that fix the "no picture on LCD" problem I'm having on the EVM?

regards,

Koen
> http://wiki.davincidsp.com/index.php?title=Patch_upstream_sending#Pat...
>
> ?
>
> With increasing traffic at this list, it would be really helpful if
> you like to improve your subjects to add something like [PATCH] at
> subject beginning. It would help to recognize patches at list.
>
> - It would be nice if you could add patch description to patch
> (attachment), too. Not only to mail text. And, additionally, being a
> little more specific in patch description would help, too. "to fix the
> issue" isn't really specific. I had to look into patch changes to get
> an idea what this patch is about.
>
> - Do you have a Beagle (NAND) board, now? If not, maybe Khasim can
> help? Would be helpful if your patches are not only for one board but
> for all OMAP3 boards we currently support. Ok, nobody except Steve has
> overo, yet ;)
> Mani>>> I have a beagle board now. I have tested it to see if it comes up on
> Beagle and it looks fine.
>
> Many thanks for your help
>
> Dirk
>
> [u-boot-mux-p1.txt59K ]Patch provides support for NAND and OneNAND flashes in the config file for EVM
> It fixes the compilation bugs coming when NAND and OneNAND is generated
> It also brings in DEFAULT_MUX_EVM which provides some additional default pin muxing
> for Display subsystem.
> From 00479c1a46fd26a30ef7a195d7c55bc845d8f7a9 Mon Sep 17 00:00:00 2001
> From: Manikandan Pillai <mani.pil...@ti.com>
> Date: Mon, 22 Sep 2008 11:34:56 +0530
> Subject: [PATCH] Changes for NAND compilation and EVM pin mux.
>
> Signed-off-by: Manikandan Pillai <mani.pil...@ti.com>
> ---
>  board/omap3/evm/evm.c            |    4 +-
>  drivers/mtd/nand/nand_base.c     |    1 +
>  fs/jffs2/jffs2_1pass.c           |    4 +-
>  include/asm-arm/arch-omap3/mux.h |  709 ++++++++++++++++++++++++++++++++++++--
>  include/configs/omap3_evm.h      |    5 +-
>  include/linux/mtd/nand.h         |   76 +----
>  6 files changed, 682 insertions(+), 117 deletions(-)
>
> diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
> index f773407..88f249d 100644
> --- a/board/omap3/evm/evm.c
> +++ b/board/omap3/evm/evm.c
> @@ -68,8 +68,6 @@ int board_init(void)
>  int misc_init_r(void)
>  {
>
> -       unsigned char byte;
> -
>  #ifdef CONFIG_DRIVER_OMAP34XX_I2C
>         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
>  #endif
> @@ -89,7 +87,7 @@ int misc_init_r(void)
>   *************************************************************************** **/
>  void set_muxconf_regs(void)
>  {
> -       MUX_DEFAULT_ES2();
> +       MUX_DEFAULT_EVM();
>  }
>
>  /************************************************************************** ****
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index 7fcd79e..7658a86 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -2869,6 +2869,7 @@ int nand_switch_ecc(struct mtd_info *mtd)
>         if (chip->options & NAND_SKIP_BBTSCAN)
>                 chip->options |= NAND_BBT_SCANNED;
>
> +       return 0;
>  }
>
>  /* module_text_address() isn't exported, and it's mostly a pointless
> diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
> index 57f5582..003907a 100644
> --- a/fs/jffs2/jffs2_1pass.c
> +++ b/fs/jffs2/jffs2_1pass.c
> @@ -458,9 +458,9 @@ static inline void put_fl_mem(void *buf)
>  #endif
>
>  #if defined(CONFIG_CMD_ONENAND)
> -       struct mtdids *id = current_part->dev->id;
> +       struct mtdids *id_onenand = current_part->dev->id;
>
> -       if (id->type == MTD_DEV_TYPE_ONENAND)
> +       if (id_onenand->type == MTD_DEV_TYPE_ONENAND)
>                 return put_fl_mem_onenand(buf);
>  #endif
>  }
> diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h
> index cd7c386..c7926a7 100644
> --- a/include/asm-arm/arch-omap3/mux.h
> +++ b/include/asm-arm/arch-omap3/mux.h
> @@ -31,12 +31,20 @@
>   * M0   - Mode 0
>   */
>
> +#define OFF_PD          (1 << 12)
> +#define OFF_PU          (3 << 12)
> +#define OFF_OUT_PTD     (0 << 11)
> +#define OFF_OUT_PTU     (1 << 11)
> +#define OFF_IN          (1 << 10)
> +#define OFF_OUT         (0 << 10)
> +#define OFF_EN          (1 << 9)
> +
>  #define  IEN   (1 << 8)
>
>  #define  IDIS  (0 << 8)
>  #define  PTU   (1 << 4)
>  #define  PTD   (0 << 4)
> -#define  EN            (1 << 3)
> +#define  EN    (1 << 3)
>  #define  DIS   (0 << 3)
>
>  #define  M0    0
> @@ -48,6 +56,18 @@
>  #define  M6    6
>  #define  M7    7
>
> +#ifdef CONFIG_OFF_PADCONF
> +#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
> +#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
> +#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
> +#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
> +#else
> +#define OFF_IN_PD       0
> +#define OFF_IN_PU       0
> +#define OFF_OUT_PD      0
> +#define OFF_OUT_PU      0
> +#endif /* #ifdef CONFIG_OFF_PADCONF */
> +
>  /*
>   * To get the actual address the offset has to added
>   * with OMAP34XX_CTRL_BASE to get the actual address
> @@ -419,6 +439,618 @@
>   * M0   - Mode 0
>   * The commented string gives the final mux configuration for that pin
>   */
> +
> +#define MUX_DEFAULT_EVM()\
> +       /*SDRC*/\
> +       MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
> +       MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
> +       MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
> +       MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
> +       MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
> +       MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
> +       MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
> +       MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
> +       MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
> +       MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
> +       MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
> +       MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
> +       MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
> +       MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
> +       MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
> +       MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
> +       MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
> +       MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
> +       MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
> +       MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
> +       MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
> +       MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
> +       MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
> +       MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
> +       MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
> +       MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
> +       MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
> +       MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
> +       MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
> +       MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
> +       MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
> +       MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
> +       MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
> +       MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
> +       MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
> +       MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
> +       MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
> +       /*GPMC*/\
> +       /*GPMC_A1*/\
> +       MUX_VAL(CP(GPMC_A1),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A2*/\
> +       MUX_VAL(CP(GPMC_A2),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A3*/\
> +       MUX_VAL(CP(GPMC_A3),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A4*/\
> +       MUX_VAL(CP(GPMC_A4),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A5*/\
> +       MUX_VAL(CP(GPMC_A5),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A6*/\
> +       MUX_VAL(CP(GPMC_A6),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A7*/\
> +       MUX_VAL(CP(GPMC_A7),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A8*/\
> +       MUX_VAL(CP(GPMC_A8),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A9*/\
> +       MUX_VAL(CP(GPMC_A9),        (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_A10*/\
> +       MUX_VAL(CP(GPMC_A10),       (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_D0*/\
> +       MUX_VAL(CP(GPMC_D0),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D1*/\
> +       MUX_VAL(CP(GPMC_D1),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D2*/\
> +       MUX_VAL(CP(GPMC_D2),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D3*/\
> +       MUX_VAL(CP(GPMC_D3),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D4*/\
> +       MUX_VAL(CP(GPMC_D4),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D5*/\
> +       MUX_VAL(CP(GPMC_D5),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D6*/\
> +       MUX_VAL(CP(GPMC_D6),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D7*/\
> +       MUX_VAL(CP(GPMC_D7),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D8*/\
> +       MUX_VAL(CP(GPMC_D8),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D9*/\
> +       MUX_VAL(CP(GPMC_D9),        (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D10*/\
> +       MUX_VAL(CP(GPMC_D10),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D11*/\
> +       MUX_VAL(CP(GPMC_D11),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D12*/\
> +       MUX_VAL(CP(GPMC_D12),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D13*/\
> +       MUX_VAL(CP(GPMC_D13),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D14*/\
> +       MUX_VAL(CP(GPMC_D14),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_D15*/\
> +       MUX_VAL(CP(GPMC_D15),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_nCS0*/\
> +       MUX_VAL(CP(GPMC_nCS0),      (OFF_OUT_PD | IDIS | PTU | EN  | M0)) \
> +       /*GPMC_nCS1*/\
> +       MUX_VAL(CP(GPMC_nCS1),      (OFF_OUT_PD | IDIS | PTU | EN  | M0)) \
> +       /*GPMC_nCS2*/\
> +       MUX_VAL(CP(GPMC_nCS2),      (OFF_OUT_PD | IDIS | PTU | EN  | M0)) \
> +       /*GPMC_nCS3*/\
> +       MUX_VAL(CP(GPMC_nCS3),      (OFF_OUT_PD | IDIS | PTU | EN  | M0)) \
> +       /*GPMC_nCS4*/\
> +       MUX_VAL(CP(GPMC_nCS4),      (OFF_IN_PD  | IEN  | PTU | EN   | M0)) \
> +       /*GPMC_nCS5*/\
> +       MUX_VAL(CP(GPMC_nCS5),      (OFF_OUT_PD | IDIS | PTD | DIS  | M0)) \
> +       /*GPMC_nCS6*/\
> +       MUX_VAL(CP(GPMC_nCS6),      (OFF_IN_PD  | IEN  | PTD | DIS  | M0)) \
> +       /*GPMC_nCS7*/\
> +       MUX_VAL(CP(GPMC_nCS7),      (OFF_IN_PD  | IEN  | PTU | EN   | M0)) \
> +       /*GPMC_CLK*/\
> +       MUX_VAL(CP(GPMC_CLK),       (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_nADV_ALE*/\
> +       MUX_VAL(CP(GPMC_nADV_ALE),  (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_nOE*/\
> +       MUX_VAL(CP(GPMC_nOE),       (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_nWE*/\
> +       MUX_VAL(CP(GPMC_nWE),       (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_nBE0_CLE*/\
> +       MUX_VAL(CP(GPMC_nBE0_CLE),  (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> +       /*GPMC_nBE1*/\
> +       MUX_VAL(CP(GPMC_nBE1),      (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +       /*GPMC_nWP*/\
> +       MUX_VAL(CP(GPMC_nWP),       (OFF_IN_PD  | IEN  | PTD | DIS | M0)) \
> +        /*GPMC_WAIT0*/\
> +       MUX_VAL(CP(GPMC_WAIT0),     (OFF_IN_PD  | IEN  | PTU | EN  | M0)) \
> +       /*GPMC_WAIT1*/\
> +       MUX_VAL(CP(GPMC_WAIT1),    ...
>
> meer lezen »

Pillai, Manikandan

unread,
Sep 22, 2008, 11:49:10 PM9/22/08
to beagl...@googlegroups.com
Hi all,

Pls find attached a patch for generating a single binary image for
EVM. This detects on the fly whether the flash on the board is NAND
or ONENAND and does the proper initialization.

Pls send in your comments.

Regards
Manikandan

-----Original Message-----
From: Pillai, Manikandan
Sent: Monday, September 22, 2008 11:48 AM
To: beagl...@googlegroups.com
Subject: RE: [PATCH] - Fixing some MUX and compilation issues on the OMAP3 EVM board(Patch1/1)


Hi all,

Pls ignore the patches which have been sent for single binary image for NAND and OneNAND flashes. I will generate them again against the common branch and resend them.

In this patch, I am fixing some compilation bugs for jffs2 arising out of the upstream changes in nand header files and adding a default mux configuration for
EVM that support some display configuration.

Pls send in your comments for the same. I am in the process of generating the


Single binary image patch )based on a similar approach for the patch I sent a few days back).

Regards
Mani


-----Original Message-----
From: Pillai, Manikandan
Sent: Tuesday, September 09, 2008 4:59 PM
To: 'Dirk Behme'
Cc: beagl...@googlegroups.com; Syed Mohammed, Khasim
Subject: [PATCH] - Single binary image for NAND/OneNAND based OMAP3 board(Patch1/1)

Hi all,

Pls find a patch which provides a changes for a single binary image for OMAP3


for NAND/Onenand based boards. I have added a description of the patch at the start of the file.

I was not sure whether to send this patch to this list or the u-boot list but
Since the single image is currently there for OMAP3 I am sending it to this list.

Note: While applying this patch, depending on whether the previous patch is applied, you might have warning for nand_base.c which you can ignore.

Pls let me know your comments.

Regards
Mani

-----Original Message-----
From: Dirk Behme [mailto:dirk....@googlemail.com]
Sent: Saturday, September 06, 2008 1:46 PM
To: Pillai, Manikandan
Cc: beagl...@googlegroups.com; Syed Mohammed, Khasim
Subject: Re: [beagleboard] Patch for fixing the nand hw mode write - Patch(1/1)

http://wiki.davincidsp.com/index.php?title=Patch_upstream_sending#Patch_rules

?

Mani>>> I have a beagle board now. I have tested it to see if it comes up on
Beagle and it looks fine.

Many thanks for your help

Dirk

u-boot-single-bin-p1.txt

Dirk Behme

unread,
Oct 3, 2008, 9:16:30 AM10/3/08
to beagl...@googlegroups.com
Mani,

Pillai, Manikandan wrote:
> Hi all,
>

> Pls ignore the patches which have been sent for single binary image for NAND and OneNAND flashes. I will generate them again against the common branch and resend them.
>
> In this patch, I am fixing some compilation bugs for jffs2 arising out of the upstream changes in nand header files and adding a default mux configuration for
> EVM that support some display configuration.
>
> Pls send in your comments for the same.

Thanks for your patches, they are not forgotten ;)

Some remarks, though:

* In general, Steve and I like to wait with applying (new) patches to
Steve's git until basic OMAP3 support is accepted in upstream U-Boot.
Everything else would result in a lot merge work and confusion. The
next U-Boot merge window is supposed to open at mid of october, so
hopefully OMAP3 support is merged then. Hope it is ok for you to wait
some additional days. Maybe we can work on the topics below until then ;)

* It would be easier to review and understand your patches if you could

a) split the patches in small logical parts with one functionality
change/bugfix in one patch. Having a quick look at changes below this
patch contains at least 3 logical independent parts (mux changes,
minor fixes/clean up, nand & jffs changes)

b) don't mix mails, subjects and patches. In this mail I count 4 (!)
different subjects:

[PATCH] - Fixing some MUX and compilation issues on the OMAP3 EVM
board(Patch1/1)

[PATCH] - Single binary image for NAND/OneNAND based OMAP3 board(Patch1/1)

Patch for fixing the nand hw mode write - Patch(1/1)

[PATCH] Changes for NAND compilation and EVM pin mux.

Quite confusing :(

c) send OMAP3 independent patches directly to U-Boot list for inclusion.

* Regarding mux.h I'd like to discuss how we can do this more generic
with less code.

Yes, having a #define MUX_DEFAULT_xxx() for each board in mux.h is the
easiest way. But adding additional mux settings for additional boards
will result in a quite large mux.h, soon. So we should discuss how we
can replace the existing #define MUX_DEFAULT_xxx() with a more generic
and scalable solution.

I think we should have something like one global default mux setting
for all boards and then overwrite the (hopefully small) *different*
board specific parts with something in the board files. E.g. something
like we already do with the "const omap3_sysinfo sysinfo" logic we
introduced recently.

Unfortunately, I don't have an idea how this could look in real code,
yet ;) Any proposals?

Thanks

Dirk

> ------------------------------------------------------------------------


>
> Patch provides support for NAND and OneNAND flashes in the config file for EVM
> It fixes the compilation bugs coming when NAND and OneNAND is generated
> It also brings in DEFAULT_MUX_EVM which provides some additional default pin muxing
> for Display subsystem.
> From 00479c1a46fd26a30ef7a195d7c55bc845d8f7a9 Mon Sep 17 00:00:00 2001

> From: Manikandan Pillai <mani....@ti.com>


> Date: Mon, 22 Sep 2008 11:34:56 +0530
> Subject: [PATCH] Changes for NAND compilation and EVM pin mux.
>
>

> Signed-off-by: Manikandan Pillai <mani....@ti.com>

> + MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*GPIO_64 - ETH_nRESET*/\
> + MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) \
> + /*GPIO_65*/\
> + MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*DSS*/\
> + /*DSS_PCLK*/\
> + MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_HSYNC*/\
> + MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_VSYNC*/\
> + MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_ACBIAS*/\
> + MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA0*/\
> + MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA1*/\
> + MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA2*/\
> + MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA3*/\
> + MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA4*/\
> + MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA5*/\
> + MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA6*/\
> + MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA7*/\
> + MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA8*/\
> + MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA9*/\
> + MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA10*/\
> + MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA11*/\
> + MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA12*/\
> + MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA13*/\
> + MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA14*/\
> + MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA15*/\
> + MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA16*/\
> + MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA17*/\
> + MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA18*/\
> + MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA19*/\
> + MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA20*/\
> + MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA21*/\
> + MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA22*/\
> + MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*DSS_DATA23*/\
> + MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*CAMERA*/\
> + /*CAM_HS */\
> + MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*CAM_VS */\
> + MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*CAM_XCLKA*/\
> + MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*CAM_PCLK*/\
> + MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*GPIO_98 - CAM_RESET*/\
> + MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + /*CAM_D0 */\
> + MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D1 */\
> + MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D2 */\
> + MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D3 */\
> + MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D4 */\
> + MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D5 */\
> + MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D6 */\
> + MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D7 */\
> + MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D8 */\
> + MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D9 */\
> + MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D10*/\
> + MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_D11*/\
> + MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CAM_XCLKB*/\
> + MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*GPIO_167*/\
> + MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) \
> + /*CAM_STROBE*/\
> + MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*CSI2_DX0*/\
> + MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CSI2_DY0*/\
> + MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CSI2_DX1*/\
> + MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*CSI2_DY1*/\
> + MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*Audio Interface */\
> + /*McBSP2_FSX*/\
> + MUX_VAL(CP(McBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP2_CLKX*/\
> + MUX_VAL(CP(McBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP2_DR*/\
> + MUX_VAL(CP(McBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP2_DX*/\
> + MUX_VAL(CP(McBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*Expansion card */\
> + /*MMC1_CLK*/\
> + MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0)) \
> + /*MMC1_CMD*/\
> + MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT0*/\
> + MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT1*/\
> + MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT2*/\
> + MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT3*/\
> + MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT4*/\
> + MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT5*/\
> + MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT6*/\
> + MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC1_DAT7*/\
> + MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*Wireless LAN */\
> + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*MMC2_CMD*/\
> + MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC2_DAT0*/\
> + MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC2_DAT1*/\
> + MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC2_DAT2*/\
> + MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC2_DAT3*/\
> + MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*MMC2_DAT4*/\
> + MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*MMC2_DAT5*/\
> + MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*MMC2_DAT6 */\
> + MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*MMC2_DAT7*/\
> + MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*Bluetooth*/\
> + /*McBSP3_DX*/\
> + MUX_VAL(CP(McBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*McBSP3_DR*/\
> + MUX_VAL(CP(McBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP3_CLKX */\
> + MUX_VAL(CP(McBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP3_FSX*/\
> + MUX_VAL(CP(McBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*UART2_CTS*/\
> + MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*UART2_RTS*/\
> + MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*UART2_TX*/\
> + MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*UART2_RX*/\
> + MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*Modem Interface */\
> + /*UART1_TX*/\
> + MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*UART1_RTS*/\
> + MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*UART1_CTS*/\
> + MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0)) \
> + /*UART1_RX*/\
> + MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*GPIO_152 - LCD_INI*/\
> + MUX_VAL(CP(McBSP4_CLKX), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + /*GPIO_153 - LCD_ENVDD */\
> + MUX_VAL(CP(McBSP4_DR), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + /*GPIO_154 - LCD_QVGA/nVGA */\
> + MUX_VAL(CP(McBSP4_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + /*GPIO_155 - LCD_RESB */\
> + MUX_VAL(CP(McBSP4_FSX), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + /*McBSP1_CLKR */\
> + MUX_VAL(CP(McBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP1_FSR*/\
> + MUX_VAL(CP(McBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M0)) \
> + /*McBSP1_DX*/\
> + MUX_VAL(CP(McBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*McBSP1_DR*/\
> + MUX_VAL(CP(McBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP_CLKS */\
> + MUX_VAL(CP(McBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0)) \
> + /*McBSP1_FSX*/\
> + MUX_VAL(CP(McBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McBSP1_CLKX */\
> + MUX_VAL(CP(McBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*Serial Interface*/\
> + /*UART3_CTS_RCTX */\
> + MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*UART3_RTS_SD */\
> + MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*UART3_RX_IRRX*/\
> + MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*UART3_TX_IRTX*/\
> + MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*HSUSB0_CLK*/\
> + MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_STP*/\
> + MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0)) \
> + /*HSUSB0_DIR*/\
> + MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_NXT*/\
> + MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA0 */\
> + MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA1 */\
> + MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA2 */\
> + MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA3 */\
> + MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA4 */\
> + MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA5 */\
> + MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA6 */\
> + MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*HSUSB0_DATA7 */\
> + MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*I2C1_SCL*/\
> + MUX_VAL(CP(I2C1_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C1_SDA*/\
> + MUX_VAL(CP(I2C1_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C2_SCL*/\
> + MUX_VAL(CP(I2C2_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C2_SDA*/\
> + MUX_VAL(CP(I2C2_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C3_SCL*/\
> + MUX_VAL(CP(I2C3_SCL), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C3_SDA*/\
> + MUX_VAL(CP(I2C3_SDA), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*I2C4_SCL*/\
> + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
> + /*I2C4_SDA*/\
> + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
> + /*HDQ_SIO*/\
> + MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*McSPI1_CLK*/\
> + MUX_VAL(CP(McSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI1_SIMO */\
> + MUX_VAL(CP(McSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI1_SOMI */\
> + MUX_VAL(CP(McSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI1_CS0*/\
> + MUX_VAL(CP(McSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*GPIO_175 - TS_PEN_IRQ */\
> + MUX_VAL(CP(McSPI1_CS1), (OFF_IN_PD | IEN | PTD | EN | M4)) \
> + /*GPIO_176 - LAN_INTR*/\
> + MUX_VAL(CP(McSPI1_CS2), (OFF_IN_PD | IEN | PTD | DIS | M4)) \
> + /*McSPI1_CS3*/\
> + MUX_VAL(CP(McSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*McSPI2_CLK*/\
> + MUX_VAL(CP(McSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI2_SIMO*/\
> + MUX_VAL(CP(McSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI2_SOMI*/\
> + MUX_VAL(CP(McSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*McSPI2_CS0*/\
> + MUX_VAL(CP(McSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*McSPI2_CS1*/\
> + MUX_VAL(CP(McSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*Control and debug */\
> + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
> + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
> + /*SYS_nIRQ*/\
> + MUX_VAL(CP(SYS_nIRQ), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*GPIO_2*/\
> + MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_3 */\
> + MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_4 */\
> + MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_5*/\
> + MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_6*/\
> + MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_7*/\
> + MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4)) \
> + /*GPIO_8 - VIO 1V8*/\
> + MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4)) \
> + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE */\
> + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1 */\
> + /*SYS_CLKOUT2*/\
> + MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
> + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
> + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
> + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
> + /*JTAG_EMU0*/\
> + MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*JTAG_EMU1*/\
> + MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_CLK*/\
> + MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0)) \
> + /*ETK_CTL*/\
> + MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0)) \
> + /*ETK_D0*/\
> + MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D1*/\
> + MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D2*/\
> + MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*ETK_D3*/\
> + MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D4*/\
> + MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D5*/\
> + MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D6*/\
> + MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D7*/\
> + MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D8*/\
> + MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D9*/\
> + MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D10*/\
> + MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D11*/\
> + MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D12*/\
> + MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D13*/\
> + MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D14*/\
> + MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*ETK_D15*/\
> + MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*Die to Die */\
> + /*d2d_mcad0*/\
> + MUX_VAL(CP(d2d_mcad0), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad1*/\
> + MUX_VAL(CP(d2d_mcad1), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad2*/\
> + MUX_VAL(CP(d2d_mcad2), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad3*/\
> + MUX_VAL(CP(d2d_mcad3), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad4*/\
> + MUX_VAL(CP(d2d_mcad4), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad5*/\
> + MUX_VAL(CP(d2d_mcad5), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad6*/\
> + MUX_VAL(CP(d2d_mcad6), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad7*/\
> + MUX_VAL(CP(d2d_mcad7), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad8*/\
> + MUX_VAL(CP(d2d_mcad8), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad9*/\
> + MUX_VAL(CP(d2d_mcad9), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad10*/\
> + MUX_VAL(CP(d2d_mcad10), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad11*/\
> + MUX_VAL(CP(d2d_mcad11), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad12*/\
> + MUX_VAL(CP(d2d_mcad12), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad13*/\
> + MUX_VAL(CP(d2d_mcad13), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad14*/\
> + MUX_VAL(CP(d2d_mcad14), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad15*/\
> + MUX_VAL(CP(d2d_mcad15), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad16*/\
> + MUX_VAL(CP(d2d_mcad16), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad17*/\
> + MUX_VAL(CP(d2d_mcad17), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad18*/\
> + MUX_VAL(CP(d2d_mcad18), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad19*/\
> + MUX_VAL(CP(d2d_mcad19), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad20*/\
> + MUX_VAL(CP(d2d_mcad20), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad21*/\
> + MUX_VAL(CP(d2d_mcad21), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad22*/\
> + MUX_VAL(CP(d2d_mcad22), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad23*/\
> + MUX_VAL(CP(d2d_mcad23), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad24*/\
> + MUX_VAL(CP(d2d_mcad24), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad25*/\
> + MUX_VAL(CP(d2d_mcad25), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad26*/\
> + MUX_VAL(CP(d2d_mcad26), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad27*/\
> + MUX_VAL(CP(d2d_mcad27), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad28*/\
> + MUX_VAL(CP(d2d_mcad28), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad29*/\
> + MUX_VAL(CP(d2d_mcad29), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad30*/\
> + MUX_VAL(CP(d2d_mcad30), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad31*/\
> + MUX_VAL(CP(d2d_mcad31), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad32*/\
> + MUX_VAL(CP(d2d_mcad32), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad33*/\
> + MUX_VAL(CP(d2d_mcad33), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad34*/\
> + MUX_VAL(CP(d2d_mcad34), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad35*/\
> + MUX_VAL(CP(d2d_mcad35), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_mcad36*/\
> + MUX_VAL(CP(d2d_mcad36), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_clk26mi */\
> + MUX_VAL(CP(d2d_clk26mi), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_nrespwron*/\
> + MUX_VAL(CP(d2d_nrespwron), (OFF_OUT_PD | IEN | PTD | EN | M0)) \
> + /*d2d_nreswarm */\
> + MUX_VAL(CP(d2d_nreswarm), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*d2d_arm9nirq */\
> + MUX_VAL(CP(d2d_arm9nirq), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_uma2p6fiq*/\
> + MUX_VAL(CP(d2d_uma2p6fiq), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_spint*/\
> + MUX_VAL(CP(d2d_spint), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_frint*/\
> + MUX_VAL(CP(d2d_frint), (OFF_IN_PD | IEN | PTD | EN | M0)) \
> + /*d2d_dmareq0 */\
> + MUX_VAL(CP(d2d_dmareq0), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_dmareq1 */\
> + MUX_VAL(CP(d2d_dmareq1), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_dmareq2 */\
> + MUX_VAL(CP(d2d_dmareq2), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_dmareq3 */\
> + MUX_VAL(CP(d2d_dmareq3), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3gtrst */\
> + MUX_VAL(CP(d2d_n3gtrst), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3gtdi*/\
> + MUX_VAL(CP(d2d_n3gtdi), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3gtdo*/\
> + MUX_VAL(CP(d2d_n3gtdo), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3gtms*/\
> + MUX_VAL(CP(d2d_n3gtms), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3gtck*/\
> + MUX_VAL(CP(d2d_n3gtck), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_n3grtck */\
> + MUX_VAL(CP(d2d_n3grtck), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_mstdby*/\
> + MUX_VAL(CP(d2d_mstdby), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup */\
> + /*d2d_idlereq */\
> + MUX_VAL(CP(d2d_idlereq), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_idleack */\
> + MUX_VAL(CP(d2d_idleack), (OFF_IN_PD | IEN | PTU | EN | M0)) \
> + /*d2d_mwrite*/\
> + MUX_VAL(CP(d2d_mwrite), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_swrite*/\
> + MUX_VAL(CP(d2d_swrite), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_mread*/\
> + MUX_VAL(CP(d2d_mread), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_sread*/\
> + MUX_VAL(CP(d2d_sread), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_mbusflag */\
> + MUX_VAL(CP(d2d_mbusflag), (OFF_IN_PD | IEN | PTD | DIS | M0)) \
> + /*d2d_sbusflag */\
> + MUX_VAL(CP(d2d_sbusflag), (OFF_OUT_PD | IEN | PTD | DIS | M0)) \
> + /*sdrc_cke0 */\
> + MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) \
> + /*sdrc_cke1 not used*/\
> + MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7))
> +
> +
> +
> #define MUX_DEFAULT_ES2() \
> /*SDRC*/\


> MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\

> @@ -827,8 +1459,8 @@
> /* - MMC1_WP*/\
> MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
> MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
> - MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
> - MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
> + MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPIO_57*/\
> + MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPIO_58*/\
> MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
> MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
> MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
> @@ -874,7 +1506,8 @@
> MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
> MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
> MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
> - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
> + MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
> + /* - CAM_RESET*/\
> MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
> MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
> MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
> @@ -888,12 +1521,13 @@
> MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
> MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
> MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
> - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
> + MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
> MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
> MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
> MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
> MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
> - MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\
> + MUX_VAL(CP(CSI2_DY1), (IDIS | PTU | EN | M4)) /*GPIO_115*/\
> + /* - W2W_PON*/\
> /*Audio Interface */\
> MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
> MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
> @@ -922,36 +1556,35 @@
> MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
> MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
> /*Bluetooth*/\
> - MUX_VAL(CP(McBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
> - MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
> - MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
> - MUX_VAL(CP(McBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
> - MUX_VAL(CP(UART2_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_144*/\
> - /* - LCD_EN*/\
> - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_145*/\
> - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M4)) /*GPIO_146*/\
> - MUX_VAL(CP(UART2_RX), (IDIS | PTD | DIS | M4)) /*GPIO_147*/\
> + MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
> + MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
> + MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
> + MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
> + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
> + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
> + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
> + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
> + /*Modem Interface */\
> MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
> - MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
> - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150*/ \
> - /* - MMC3_WP*/\
> + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
> + MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
> MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
> - MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
> - MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
> - MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
> - MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
> - MUX_VAL(CP(McBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
> - MUX_VAL(CP(McBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
> - MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
> - MUX_VAL(CP(McBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
> + MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
> + MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
> + MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
> + MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
> + MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
> + MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157*/\
> + /* - BT_WAKEUP*/\
> + MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
> + MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
> MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
> - MUX_VAL(CP(McBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
> - MUX_VAL(CP(McBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
> + MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
> + MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
> /*Serial Interface*/\
> MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_*/\
> /* RCTX*/\
> - MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 */\
> - /* - W2W_BT_NRESET*/\
> + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
> MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
> MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
> MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
> @@ -970,7 +1603,7 @@
> MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
> MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
> /* - USBH_CPEN*/\
> - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
> + MUX_VAL(CP(I2C2_SDA), (IEN | PTD | EN | M4)) /*GPIO_183*/\
> /* - USBH_RESET*/\
> MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
> MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
> @@ -983,6 +1616,7 @@
> MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
> MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
> MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176*/\
> + /* - NOR_DPD*/\
> MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
> MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
> MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
> @@ -994,22 +1628,27 @@
> MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
> MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
> MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
> + /* - PEN_IRQ */\
> MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
> MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\
> /* - MMC1_WP */\
> MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
> + /* - LCD_ENVDD*/\
> MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
> + /* - LAN_INTR0*/\
> MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
> - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
> + /* - MMC2_WP*/\
> + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
> + /* - LCD_ENBKL*/\
> MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
> MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
> MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
> MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\
> MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
> MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\
> - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15*/\
> - /* - X_GATE*/\
> - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
> + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M4)) /*GPIO_15*/\
> + /* - MMC1-CD*/\
> + MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M4)) /*GPIO_16*/\
> /* - W2W_NRESET*/\
> MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
> MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index d1d29e6..005b9bf 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -105,6 +105,7 @@
> #define CONFIG_CMD_I2C /* I2C serial bus support */
> #define CONFIG_CMD_MMC /* MMC support */
> #define CONFIG_CMD_ONENAND /* ONENAND support */
> +#define CONFIG_CMD_NAND /* NAND support */
>
> #define CONFIG_CMD_AUTOSCRIPT /* autoscript support */
> #define CONFIG_CMD_BDI /* bdinfo */
> @@ -253,8 +254,8 @@
> #define CFG_ONENAND_BASE ONENAND_MAP
>
> #define CONFIG_ENV_IS_IN_ONENAND 1
> -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
> -#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
> +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
> +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
>
> #define CONFIG_ENV_SECT_SIZE boot_flash_sec
> #define CONFIG_ENV_OFFSET boot_flash_off
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 7ac72de..fb3ea8f 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -31,7 +31,7 @@
>
> #include "linux/mtd/compat.h"
> #include "linux/mtd/mtd.h"
> -
> +#include <linux/mtd/bbm.h>
>
> struct mtd_info;
> /* Scan and identify a NAND device */
> @@ -363,7 +363,6 @@ struct nand_buffers {
> * (determine if errors are correctable)
> * @write_page: [REPLACEABLE] High-level page write function
> */
> -
> struct nand_chip {
> void __iomem *IO_ADDR_R;
> void __iomem *IO_ADDR_W;
> @@ -470,79 +469,6 @@ struct nand_manufacturers {
> extern struct nand_flash_dev nand_flash_ids[];
> extern struct nand_manufacturers nand_manuf_ids[];
>
> -#ifndef NAND_MAX_CHIPS
> -#define NAND_MAX_CHIPS 8
> -#endif
> -
> -/**
> - * struct nand_bbt_descr - bad block table descriptor
> - * @options: options for this descriptor
> - * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
> - * when bbt is searched, then we store the found bbts pages here.
> - * Its an array and supports up to 8 chips now
> - * @offs: offset of the pattern in the oob area of the page
> - * @veroffs: offset of the bbt version counter in the oob are of the page
> - * @version: version read from the bbt page during scan
> - * @len: length of the pattern, if 0 no pattern check is performed
> - * @maxblocks: maximum number of blocks to search for a bbt. This number of
> - * blocks is reserved at the end of the device where the tables are
> - * written.
> - * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
> - * bad) block in the stored bbt
> - * @pattern: pattern to identify bad block table or factory marked good /
> - * bad blocks, can be NULL, if len = 0
> - *
> - * Descriptor for the bad block table marker and the descriptor for the
> - * pattern which identifies good and bad blocks. The assumption is made
> - * that the pattern and the version count are always located in the oob area
> - * of the first block.
> - */
> -struct nand_bbt_descr {
> - int options;
> - int pages[NAND_MAX_CHIPS];
> - int offs;
> - int veroffs;
> - uint8_t version[NAND_MAX_CHIPS];
> - int len;
> - int maxblocks;
> - int reserved_block_code;
> - uint8_t *pattern;
> -};
> -
> -/* Options for the bad block table descriptors */
> -
> -/* The number of bits used per block in the bbt on the device */
> -#define NAND_BBT_NRBITS_MSK 0x0000000F
> -#define NAND_BBT_1BIT 0x00000001
> -#define NAND_BBT_2BIT 0x00000002
> -#define NAND_BBT_4BIT 0x00000004
> -#define NAND_BBT_8BIT 0x00000008
> -/* The bad block table is in the last good block of the device */
> -#define NAND_BBT_LASTBLOCK 0x00000010
> -/* The bbt is at the given page, else we must scan for the bbt */
> -#define NAND_BBT_ABSPAGE 0x00000020
> -/* The bbt is at the given page, else we must scan for the bbt */
> -#define NAND_BBT_SEARCH 0x00000040
> -/* bbt is stored per chip on multichip devices */
> -#define NAND_BBT_PERCHIP 0x00000080
> -/* bbt has a version counter at offset veroffs */
> -#define NAND_BBT_VERSION 0x00000100
> -/* Create a bbt if none axists */
> -#define NAND_BBT_CREATE 0x00000200
> -/* Search good / bad pattern through all pages of a block */
> -#define NAND_BBT_SCANALLPAGES 0x00000400
> -/* Scan block empty during good / bad block scan */
> -#define NAND_BBT_SCANEMPTY 0x00000800
> -/* Write bbt if neccecary */
> -#define NAND_BBT_WRITE 0x00001000
> -/* Read and write back block contents when writing bbt */
> -#define NAND_BBT_SAVECONTENT 0x00002000
> -/* Search good / bad pattern on the first and the second page */
> -#define NAND_BBT_SCAN2NDPAGE 0x00004000
> -
> -/* The maximum number of blocks to scan for a bbt */
> -#define NAND_BBT_SCAN_MAXBLOCKS 4
> -
> extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
> extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
> extern int nand_default_bbt(struct mtd_info *mtd);

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