S-Video out and OMAP git tree
Hunyue Yau
Based on work done by MontaVista for the 3430SDP, I have a version
of the TI (WTBU) OMAP frame buffer driver that supports TV out grafted
onto a recent OMAP-git tree. It isn't perfect but I am able to see the
boot penguin on a NTSC display. And the display is indeed noisy.
I don't have a HDMI/DVI convert/cable combo to try the LCD output so
someone else will have to test that.
The patch itself is rather long (11K lines). What's a good way of
getting this out? I can attach it if people do not consider it too
long.
-- Hunyue
koen
regards,
Koen
Hunyue Yau
Okay - here it is. Sorry for the monolithic patch but this is really a
"grafting" of the code. I have a working config if needed. There are
some bugs. I got it as far as seeing the boot logo when I do the
echo 'tv' line.
-- Hunyue
Graft in OMAP frame buffer driver from TI tree.
The original code was from TI based on an older kernel.
It has been ported to the 2.6.24 Linux OMAP git tree
by Montavista. This version has been ported to the 2.6.26
Linux OMAP git tree. It has only been tested on a
OMAP3 Beagle board using TV (NTSC) out. This driver is not
perfect but is currently the only driver for the OMAP
git tree that will do TV out.
To enable TV out, be sure CONFIG_VIDEO_OMAP24XX_TVOUT is enabled
in addition to CONFIG_FB_OMAP. At run time the following will
enable the TV output:
echo 'tv' > /sys/class/display_control/omap_disp_control/graphics
Signed-off-by: Hunyue Yau <hy...@mvista.com>
Signed-off-by: Jean Pihet <jpi...@mvista.com>
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 93bbb64..d6d5ce5 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -14,6 +14,8 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
+obj-$(CONFIG_ARCH_OMAP3) += display.o
+
obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_BOOT_REASON) += bootreason.o
diff --git a/arch/arm/plat-omap/display.c b/arch/arm/plat-omap/display.c
new file mode 100644
index 0000000..7012d29
--- /dev/null
+++ b/arch/arm/plat-omap/display.c
@@ -0,0 +1,3802 @@
+/*
+ * arch/arm/mach-omap2/display.c
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Leveraged code from the OMAP24xx camera driver
+ * Video-for-Linux (Version 2) camera capture driver for
+ * the OMAP24xx camera controller.
+ *
+ * Author: Andy Lowe (sou...@mvista.com)
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ *
+ * History:
+ * 20-APR-2006 Khasim Modified VRFB based Rotation equations,
+ * The image data is always read from 0 degree
+ * view and written to the virtual space of desired
+ * rotation angle
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/semaphore.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/display.h>
+#include <asm/arch/venc.h>
+#include <asm/arch/clock.h>
+#ifdef CONFIG_TRACK_RESOURCES
+#include <linux/device.h>
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+extern int lpr_enabled;
+#endif
+
+/* usage count for DSS power management */
+static int disp_usage;
+#ifndef CONFIG_ARCH_OMAP3410
+static int omap2_current_tvstandard = NTSC_M;
+#endif
+static spinlock_t dss_lock;
+short int current_colorconv_values[2][3][3];
+static struct omap_dss_regs dss_ctx;
+static struct clk *dss1f_scale;
+static struct tvlcd_status_t tvlcd_status;
+
+static struct clk *dss1f, *dss1i;
+
+struct omap2_disp_dma_params {
+ u32 ba0;
+ u32 ba1;
+ int row_inc;
+ int pix_inc;
+};
+
+static struct layer_t {
+ int output_dev;
+ int in_use;
+ int ctx_valid;
+
+ /* one set of dma parameters each for LCD and TV */
+ struct omap2_disp_dma_params dma[2];
+
+ int size_x;
+ int size_y;
+} layer[DSS_CTX_NUMBER] = {
+ {.ctx_valid = 0,},
+ {.ctx_valid = 0,},
+ {.ctx_valid = 0,},
+ {.ctx_valid = 0,},
+ {.ctx_valid = 0,},
+};
+
+#define MAX_ISR_NR 8
+static int omap2_disp_irq;
+static struct {
+ omap2_disp_isr_t isr;
+ void *arg;
+ unsigned int mask;
+} registered_isr[MAX_ISR_NR];
+
+/* VRFB offset computation parameters */
+#define SIDE_H 1
+#define SIDE_W 0
+
+
+/* GFX FIFO thresholds */
+#define RMODE_GFX_FIFO_HIGH_THRES 0x3FC
+#define RMODE_GFX_FIFO_LOW_THRES 0x3BC
+
+#ifdef CONFIG_TRACK_RESOURCES
+/* device name needed for resource tracking layer */
+struct device_driver display_drv = {
+ .name = "display",
+};
+
+struct device display_dev = {
+ .driver = &display_drv,
+};
+#endif
+/*
+ * DSS register I/O routines
+ */
+static __inline__ u32
+dss_reg_in(u32 offset)
+{
+ return omap_readl(DSS_REG_BASE + DSS_REG_OFFSET + offset);
+}
+static __inline__ u32
+dss_reg_out(u32 offset, u32 val)
+{
+ omap_writel(val,DSS_REG_BASE + DSS_REG_OFFSET + offset);
+ return val;
+}
+static __inline__ u32
+dss_reg_merge(u32 offset, u32 val, u32 mask)
+{
+ u32 addr = DSS_REG_BASE + DSS_REG_OFFSET + offset;
+ u32 new_val = (omap_readl(addr) & ~mask) | (val & mask);
+
+ omap_writel(new_val, addr);
+ return new_val;
+}
+
+/*
+ * Display controller register I/O routines
+ */
+static __inline__ u32
+dispc_reg_in(u32 offset)
+{
+ return omap_readl(DSS_REG_BASE + DISPC_REG_OFFSET + offset);
+}
+
+static __inline__ u32
+dispc_reg_out(u32 offset, u32 val)
+{
+ omap_writel(val, DSS_REG_BASE + DISPC_REG_OFFSET + offset);
+ return val;
+}
+static __inline__ u32
+dispc_reg_merge(u32 offset, u32 val, u32 mask)
+{
+ u32 addr = DSS_REG_BASE + DISPC_REG_OFFSET + offset;
+ u32 new_val = (omap_readl(addr) & ~mask) | (val & mask);
+
+ omap_writel(new_val, addr);
+ return new_val;
+}
+
+/*
+ * RFBI controller register I/O routines
+ */
+static __inline__ u32
+rfbi_reg_in(u32 offset)
+{
+ return omap_readl(DSS_REG_BASE + RFBI_REG_OFFSET + offset);
+}
+
+static __inline__ u32
+rfbi_reg_out(u32 offset, u32 val)
+{
+ omap_writel(val, DSS_REG_BASE + RFBI_REG_OFFSET + offset);
+ return val;
+}
+
+/*
+ * VENC register I/O Routines
+ */
+static __inline__ u32
+venc_reg_in(u32 offset)
+{
+ return omap_readl(DSS_REG_BASE + VENC_REG_OFFSET + offset);
+}
+static __inline__ u32
+venc_reg_out(u32 offset, u32 val)
+{
+ omap_writel(val, DSS_REG_BASE + VENC_REG_OFFSET + offset);
+ return val;
+}
+static __inline__ u32
+venc_reg_merge(u32 offset, u32 val, u32 mask)
+{
+ u32 addr = DSS_REG_BASE + VENC_REG_OFFSET + offset;
+ u32 new_val = (omap_readl(addr) & ~mask) | (val & mask);
+
+ omap_writel(new_val, addr);
+ return new_val;
+}
+
+/* Write the color space conversion coefficients to the display controller
+ * registers. Each coefficient is a signed 11-bit integer in the range
+ * [-1024, 1023]. The matrix coefficients are:
+ * [ RY RCr RCb ]
+ * [ GY GCr GCb ]
+ * [ BY BCr BCb ]
+ */
+
+static void
+set_colorconv(int v,int colorspace)
+{
+ unsigned long ccreg;
+ short int mtx[3][3];
+ int i,j;
+ for(i=0;i<3;i++)
+ for(j=0;j<3;j++){
+ mtx[i][j] = current_colorconv_values[v][i][j];
+ }
+
+ ccreg = (mtx[0][0] & 0x7ff) | ((mtx[0][1] & 0x7ff) << 16);
+ dispc_reg_out(DISPC_VID_CONV_COEF0(v), ccreg);
+ ccreg = (mtx[0][2] & 0x7ff) | ((mtx[1][0] & 0x7ff) << 16);
+ dispc_reg_out(DISPC_VID_CONV_COEF1(v), ccreg);
+ ccreg = (mtx[1][1] & 0x7ff) | ((mtx[1][2] & 0x7ff) << 16);
+ dispc_reg_out(DISPC_VID_CONV_COEF2(v), ccreg);
+ ccreg = (mtx[2][0] & 0x7ff) | ((mtx[2][1] & 0x7ff) << 16);
+ dispc_reg_out(DISPC_VID_CONV_COEF3(v), ccreg);
+ ccreg = mtx[2][2] & 0x7ff;
+ dispc_reg_out(DISPC_VID_CONV_COEF4(v), ccreg);
+
+ if(colorspace == V4L2_COLORSPACE_JPEG || colorspace == V4L2_COLORSPACE_SRGB)
{
+ dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
+ DISPC_VID_ATTRIBUTES_VIDFULLRANGE, DISPC_VID_ATTRIBUTES_VIDFULLRANGE);
+ }
+}
+
+static void
+update_colorconv_mtx(int v,const short int mtx[3][3])
+{
+ int i,j;
+ for(i=0;i<3;i++)
+ for(j=0;j<3;j++)
+ current_colorconv_values[v][i][j] = mtx[i][j];
+}
+
+void
+omap2_disp_set_default_colorconv(int ltype, struct v4l2_pix_format *pix)
+{
+ int v;
+
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ switch (pix->colorspace) {
+ case V4L2_COLORSPACE_SMPTE170M:
+ case V4L2_COLORSPACE_SMPTE240M:
+ case V4L2_COLORSPACE_BT878:
+ case V4L2_COLORSPACE_470_SYSTEM_M:
+ case V4L2_COLORSPACE_470_SYSTEM_BG:
+ /* luma (Y) range lower limit is 16, BT.601 standard */
+ update_colorconv_mtx(v,cc_bt601);
+ set_colorconv(v,pix->colorspace);
+ break;
+ case V4L2_COLORSPACE_REC709:
+ /* luma (Y) range lower limit is 16, BT.709 standard */
+ update_colorconv_mtx(v,cc_bt709);
+ set_colorconv(v,pix->colorspace);
+ break;
+ case V4L2_COLORSPACE_JPEG:
+ case V4L2_COLORSPACE_SRGB:
+ /* full luma (Y) range, assume BT.601 standard */
+ update_colorconv_mtx(v,cc_bt601_full);
+ set_colorconv(v,pix->colorspace);
+ break;
+ }
+}
+
+void
+omap2_disp_set_colorconv(int ltype, struct v4l2_pix_format *pix)
+{
+ int v;
+
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ set_colorconv(v,pix->colorspace);
+}
+
+/* Write the horizontal and vertical resizing coefficients to the display
+ * controller registers. Each coefficient is a signed 8-bit integer in the
+ * range [-128, 127] except for the middle coefficient (vc[1][i] and hc[3]
[i])
+ * which is an unsigned 8-bit integer in the range [0, 255]. The first index
of
+ * the matrix is the coefficient number (0 to 2 vertical or 0 to 4
horizontal)
+ * and the second index is the phase (0 to 7).
+ */
+static void
+omap2_disp_set_resize(int v, const short int vc[3][8], const short int hc[5]
[8])
+{
+ int i;
+ unsigned long reg;
+
+ for (i = 0; i < 8; i++) {
+ reg = (hc[0][i] & 0xff) | ((hc[1][i] & 0xff) << 8)
+ | ((hc[2][i] & 0xff) << 16) | ((hc[3][i] & 0xff) << 24);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v, i), reg);
+ reg = (hc[4][i] & 0xff) | ((vc[0][i] & 0xff) << 8)
+ | ((vc[1][i] & 0xff) << 16) | ((vc[2][i] & 0xff) << 24);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v, i), reg);
+ }
+}
+
+/*---------------------------------------------------------------------------*/
+
+void
+omap2_disp_get_panel_size(int output_dev, int *width, int *height)
+{
+ unsigned long size;
+
+ if (output_dev == OMAP2_OUTPUT_TV) {
+ size = dispc_reg_in(DISPC_SIZE_DIG);
+ *width = 1 + ((size & DISPC_SIZE_DIG_PPL)
+ >> DISPC_SIZE_DIG_PPL_SHIFT);
+ *height = 1 + ((size & DISPC_SIZE_DIG_LPP)
+ >> DISPC_SIZE_DIG_LPP_SHIFT);
+ *height = *height << 1;
+ }
+ else if (output_dev == OMAP2_OUTPUT_LCD) {
+ size = dispc_reg_in(DISPC_SIZE_LCD);
+ *width = 1 + ((size & DISPC_SIZE_LCD_PPL)
+ >> DISPC_SIZE_LCD_PPL_SHIFT);
+ *height = 1 + ((size & DISPC_SIZE_LCD_LPP)
+ >> DISPC_SIZE_LCD_LPP_SHIFT);
+ }
+}
+void
+omap2_disp_set_panel_size(int output_dev, int width, int height)
+{
+ unsigned long size;
+
+ if (output_dev == OMAP2_OUTPUT_TV) {
+ height = height >> 1;
+ size = ((width - 1) << DISPC_SIZE_DIG_PPL_SHIFT) & DISPC_SIZE_DIG_PPL;
+ size |= ((height - 1) << DISPC_SIZE_DIG_LPP_SHIFT)
+ & DISPC_SIZE_DIG_LPP;
+ dispc_reg_out(DISPC_SIZE_DIG, size);
+ }
+ else if (output_dev == OMAP2_OUTPUT_LCD) {
+ size = ((width - 1) << DISPC_SIZE_LCD_PPL_SHIFT) & DISPC_SIZE_LCD_PPL;
+ size |= ((height - 1) << DISPC_SIZE_LCD_LPP_SHIFT)
+ & DISPC_SIZE_LCD_LPP;
+ dispc_reg_out(DISPC_SIZE_LCD, size);
+ }
+}
+
+static int graphics_in_use;
+
+/* Turn off the GFX, or video1, or video2 layer. */
+void
+omap2_disp_disable_layer(int ltype)
+{
+ unsigned long attributes;
+ int digital, v;
+
+ if (ltype == OMAP2_GRAPHICS) {
+ attributes = dispc_reg_merge(DISPC_GFX_ATTRIBUTES, 0,
+ DISPC_GFX_ATTRIBUTES_ENABLE);
+ digital = attributes & DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT;
+ graphics_in_use = 0;
+ }
+ else {
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ attributes = dispc_reg_merge(DISPC_VID_ATTRIBUTES(v), 0,
+ DISPC_VID_ATTRIBUTES_ENABLE);
+ digital = attributes & DISPC_VID_ATTRIBUTES_VIDCHANNELOUT;
+ }
+ if (digital) {
+ /* digital output */
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GODIGITAL,
+ DISPC_CONTROL_GODIGITAL);
+ }
+ else {
+ /* LCD */
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+ }
+
+ dispc_reg_merge(DISPC_CONTROL, 0,
+ DISPC_CONTROL_OVERLAYOPTIMIZATION);
+}
+
+/* Turn on the GFX, or video1, or video2 layer. */
+void
+omap2_disp_enable_layer(int ltype)
+{
+ unsigned long attributes;
+ int digital, v;
+
+ if (ltype == OMAP2_GRAPHICS) {
+ attributes = dispc_reg_merge(DISPC_GFX_ATTRIBUTES,
+ DISPC_GFX_ATTRIBUTES_ENABLE, DISPC_GFX_ATTRIBUTES_ENABLE);
+ digital = attributes & DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT;
+ graphics_in_use = 1;
+ }
+ else {
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ attributes = dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
+ DISPC_VID_ATTRIBUTES_ENABLE, DISPC_VID_ATTRIBUTES_ENABLE);
+ digital = attributes & DISPC_VID_ATTRIBUTES_VIDCHANNELOUT;
+ }
+ if (digital) {
+ /* digital output */
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GODIGITAL,
+ DISPC_CONTROL_GODIGITAL);
+ }
+ else {
+ /* LCD */
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+ }
+}
+
+/*
+ * Save the DSS state before doing a GO LCD/DIGITAL
+ */
+
+void
+omap2_disp_save_ctx(int ltype)
+{
+ int v1=0, v2=1;
+ struct omap24xx_dispc_regs *dispc = &dss_ctx.dispc;
+
+ switch(ltype){
+ case OMAP_DSS_GENERIC:
+ dss_ctx.sysconfig = dss_reg_in(DSS_SYSCONFIG);
+ dss_ctx.control = dss_reg_in(DSS_CONTROL);
+#ifdef CONFIG_ARCH_OMAP3430
+ dss_ctx.sdi_control = dss_reg_in(DSS_SDI_CONTROL);
+ dss_ctx.pll_control = dss_reg_in(DSS_PLL_CONTROL);
+#endif
+ break;
+
+ case OMAP_DSS_DISPC_GENERIC:
+ dispc->revision = dispc_reg_in(DISPC_REVISION);
+ dispc->sysconfig = dispc_reg_in(DISPC_SYSCONFIG);
+ dispc->sysstatus = dispc_reg_in(DISPC_SYSSTATUS);
+ dispc->irqstatus = dispc_reg_in(DISPC_IRQSTATUS);
+ dispc->irqenable = dispc_reg_in(DISPC_IRQENABLE);
+ dispc->control = dispc_reg_in(DISPC_CONTROL);
+ dispc->config = dispc_reg_in(DISPC_CONFIG);
+ dispc->capable = dispc_reg_in(DISPC_CAPABLE);
+ dispc->default_color0 = dispc_reg_in(DISPC_DEFAULT_COLOR0);
+ dispc->default_color1 = dispc_reg_in(DISPC_DEFAULT_COLOR1);
+ dispc->trans_color0 = dispc_reg_in(DISPC_TRANS_COLOR0);
+ dispc->trans_color1 = dispc_reg_in(DISPC_TRANS_COLOR1);
+ dispc->line_status = dispc_reg_in(DISPC_LINE_STATUS);
+ dispc->line_number = dispc_reg_in(DISPC_LINE_NUMBER);
+ dispc->data_cycle1 = dispc_reg_in(DISPC_DATA_CYCLE1);
+ dispc->data_cycle2 = dispc_reg_in(DISPC_DATA_CYCLE2);
+ dispc->data_cycle3 = dispc_reg_in(DISPC_DATA_CYCLE3);
+ dispc->timing_h = dispc_reg_in(DISPC_TIMING_H);
+ dispc->timing_v = dispc_reg_in(DISPC_TIMING_V);
+ dispc->pol_freq = dispc_reg_in(DISPC_POL_FREQ);
+ dispc->divisor = dispc_reg_in(DISPC_DIVISOR);
+ dispc->size_lcd = dispc_reg_in(DISPC_SIZE_LCD);
+ dispc->size_dig = dispc_reg_in(DISPC_SIZE_DIG);
+
+ case OMAP2_GRAPHICS:
+ dispc->gfx_ba0 = dispc_reg_in(DISPC_GFX_BA0);
+ dispc->gfx_ba1 = dispc_reg_in(DISPC_GFX_BA1);
+ dispc->gfx_position = dispc_reg_in(DISPC_GFX_POSITION);
+ dispc->gfx_size = dispc_reg_in(DISPC_GFX_SIZE);
+ dispc->gfx_attributes = dispc_reg_in(DISPC_GFX_ATTRIBUTES);
+ dispc->gfx_fifo_size = dispc_reg_in(DISPC_GFX_FIFO_SIZE);
+ dispc->gfx_fifo_threshold = dispc_reg_in(DISPC_GFX_FIFO_THRESHOLD);
+ dispc->gfx_row_inc = dispc_reg_in(DISPC_GFX_ROW_INC);
+ dispc->gfx_pixel_inc = dispc_reg_in(DISPC_GFX_PIXEL_INC);
+ dispc->gfx_window_skip = dispc_reg_in(DISPC_GFX_WINDOW_SKIP);
+ dispc->gfx_table_ba = dispc_reg_in(DISPC_GFX_TABLE_BA);
+ break;
+
+ case OMAP2_VIDEO1:
+ dispc->vid1_ba0 = dispc_reg_in(DISPC_VID_BA0(v1));
+ dispc->vid1_ba1 = dispc_reg_in(DISPC_VID_BA0(v1));
+ dispc->vid1_position = dispc_reg_in(DISPC_VID_POSITION(v1));
+ dispc->vid1_size = dispc_reg_in(DISPC_VID_SIZE(v1));
+ dispc->vid1_attributes = dispc_reg_in(DISPC_VID_ATTRIBUTES(v1));
+ dispc->vid1_fifo_size = dispc_reg_in(DISPC_VID_FIFO_SIZE(v1));
+ dispc->vid1_fifo_threshold = dispc_reg_in(DISPC_VID_FIFO_THRESHOLD(v1));
+ dispc->vid1_row_inc = dispc_reg_in(DISPC_VID_ROW_INC(v1));
+ dispc->vid1_pixel_inc = dispc_reg_in(DISPC_VID_PIXEL_INC(v1));
+ dispc->vid1_fir = dispc_reg_in(DISPC_VID_FIR(v1));
+ dispc->vid1_accu0 = dispc_reg_in(DISPC_VID_ACCU0(v1));
+ dispc->vid1_accu1 = dispc_reg_in(DISPC_VID_ACCU1(v1));
+ dispc->vid1_picture_size = dispc_reg_in(DISPC_VID_PICTURE_SIZE(v1));
+ dispc->vid1_fir_coef_h0 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,0));
+ dispc->vid1_fir_coef_h1 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,1));
+ dispc->vid1_fir_coef_h2 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,2));
+ dispc->vid1_fir_coef_h3 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,3));
+ dispc->vid1_fir_coef_h4 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,4));
+ dispc->vid1_fir_coef_h5 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,5));
+ dispc->vid1_fir_coef_h6 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,6));
+ dispc->vid1_fir_coef_h7 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v1,7));
+ dispc->vid1_fir_coef_hv0 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,0));
+ dispc->vid1_fir_coef_hv1 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,1));
+ dispc->vid1_fir_coef_hv2 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,2));
+ dispc->vid1_fir_coef_hv3 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,3));
+ dispc->vid1_fir_coef_hv4 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,4));
+ dispc->vid1_fir_coef_hv5 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,5));
+ dispc->vid1_fir_coef_hv6 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,6));
+ dispc->vid1_fir_coef_hv7 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v1,7));
+ dispc->vid1_conv_coef0 = dispc_reg_in(DISPC_VID_CONV_COEF0(v1));
+ dispc->vid1_conv_coef1 = dispc_reg_in(DISPC_VID_CONV_COEF1(v1));
+ dispc->vid1_conv_coef2 = dispc_reg_in(DISPC_VID_CONV_COEF2(v1));
+ dispc->vid1_conv_coef3 = dispc_reg_in(DISPC_VID_CONV_COEF3(v1));
+ dispc->vid1_conv_coef4 = dispc_reg_in(DISPC_VID_CONV_COEF4(v1));
+ break;
+
+ case OMAP2_VIDEO2:
+ dispc->vid2_ba0 = dispc_reg_in(DISPC_VID_BA0(v2));
+ dispc->vid2_ba1 = dispc_reg_in(DISPC_VID_BA1(v2));
+ dispc->vid2_position = dispc_reg_in(DISPC_VID_POSITION(v2));
+ dispc->vid2_size = dispc_reg_in(DISPC_VID_SIZE(v2));
+ dispc->vid2_attributes = dispc_reg_in(DISPC_VID_ATTRIBUTES(v2));
+ dispc->vid2_fifo_size = dispc_reg_in(DISPC_VID_FIFO_SIZE(v2));
+ dispc->vid2_fifo_threshold = dispc_reg_in(DISPC_VID_FIFO_THRESHOLD(v2));
+ dispc->vid2_row_inc = dispc_reg_in(DISPC_VID_ROW_INC(v2));
+ dispc->vid2_pixel_inc = dispc_reg_in(DISPC_VID_PIXEL_INC(v2));
+ dispc->vid2_fir = dispc_reg_in(DISPC_VID_FIR(v2));
+ dispc->vid2_accu0 = dispc_reg_in(DISPC_VID_ACCU0(v2));
+ dispc->vid2_accu1 = dispc_reg_in(DISPC_VID_ACCU1(v2));
+ dispc->vid2_picture_size = dispc_reg_in(DISPC_VID_PICTURE_SIZE(v2));
+ dispc->vid2_fir_coef_h0 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,0));
+ dispc->vid2_fir_coef_h1 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,1));
+ dispc->vid2_fir_coef_h2 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,2));
+ dispc->vid2_fir_coef_h3 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,3));
+ dispc->vid2_fir_coef_h4 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,4));
+ dispc->vid2_fir_coef_h5 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,5));
+ dispc->vid2_fir_coef_h6 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,6));
+ dispc->vid2_fir_coef_h7 = dispc_reg_in(DISPC_VID_FIR_COEF_H(v2,7));
+ dispc->vid2_fir_coef_hv0 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,0));
+ dispc->vid2_fir_coef_hv1 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,1));
+ dispc->vid2_fir_coef_hv2 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,2));
+ dispc->vid2_fir_coef_hv3 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,3));
+ dispc->vid2_fir_coef_hv4 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,4));
+ dispc->vid2_fir_coef_hv5 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,5));
+ dispc->vid2_fir_coef_hv6 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,6));
+ dispc->vid2_fir_coef_hv7 = dispc_reg_in(DISPC_VID_FIR_COEF_HV(v2,7));
+ dispc->vid2_conv_coef0 = dispc_reg_in(DISPC_VID_CONV_COEF0(v2));
+ dispc->vid2_conv_coef1 = dispc_reg_in(DISPC_VID_CONV_COEF1(v2));
+ dispc->vid2_conv_coef2 = dispc_reg_in(DISPC_VID_CONV_COEF2(v2));
+ dispc->vid2_conv_coef3 = dispc_reg_in(DISPC_VID_CONV_COEF3(v2));
+ dispc->vid2_conv_coef4 = dispc_reg_in(DISPC_VID_CONV_COEF4(v2));
+ break;
+ }
+ layer[ltype].ctx_valid = 1;
+}
+
+void omap2_disp_save_initstate(int ltype)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&dss_lock, flags);
+ omap2_disp_save_ctx(ltype);
+ spin_unlock_irqrestore(&dss_lock, flags);
+}
+
+/*
+ * NOte, that VENC registers are not restored here
+ * Note, that DISPC_CONTROL register is not restored here
+ */
+void
+omap2_disp_restore_ctx(int ltype)
+{
+ int v1=0, v2=1;
+ struct omap24xx_dispc_regs *dispc = &dss_ctx.dispc;
+
+ if (layer[ltype].ctx_valid == 0)
+ return;
+
+ switch(ltype){
+ case OMAP_DSS_GENERIC:
+ dss_reg_out(DSS_SYSCONFIG, dss_ctx.sysconfig);
+ dss_reg_out(DSS_CONTROL, dss_ctx.control);
+#ifdef CONFIG_ARCH_OMAP3430
+ dss_reg_out(DSS_SDI_CONTROL, dss_ctx.sdi_control);
+ dss_reg_out(DSS_PLL_CONTROL, dss_ctx.pll_control);
+#endif
+ break;
+
+ case OMAP_DSS_DISPC_GENERIC:
+ dispc_reg_out(DISPC_SYSCONFIG, dispc->sysconfig);
+ dispc_reg_out(DISPC_IRQENABLE, dispc->irqenable);
+ dispc_reg_out(DISPC_CONFIG, dispc->config);
+ dispc_reg_out(DISPC_DEFAULT_COLOR0, dispc->default_color0);
+ dispc_reg_out(DISPC_DEFAULT_COLOR1, dispc->default_color1);
+ dispc_reg_out(DISPC_TRANS_COLOR0, dispc->trans_color0);
+ dispc_reg_out(DISPC_TRANS_COLOR1, dispc->trans_color1);
+ dispc_reg_out(DISPC_LINE_NUMBER, dispc->line_number);
+ dispc_reg_out(DISPC_DATA_CYCLE1, dispc->data_cycle1);
+ dispc_reg_out(DISPC_DATA_CYCLE2, dispc->data_cycle2);
+ dispc_reg_out(DISPC_DATA_CYCLE3, dispc->data_cycle3);
+ dispc_reg_out(DISPC_TIMING_H, dispc->timing_h);
+ dispc_reg_out(DISPC_TIMING_V, dispc->timing_v);
+ dispc_reg_out(DISPC_POL_FREQ, dispc->pol_freq);
+ dispc_reg_out(DISPC_DIVISOR, dispc->divisor);
+ dispc_reg_out(DISPC_SIZE_LCD, dispc->size_lcd);
+ dispc_reg_out(DISPC_SIZE_DIG, dispc->size_dig);
+ break;
+
+ case OMAP2_GRAPHICS:
+ dispc_reg_out(DISPC_GFX_BA0, dispc->gfx_ba0);
+ dispc_reg_out(DISPC_GFX_BA1, dispc->gfx_ba1);
+ dispc_reg_out(DISPC_GFX_POSITION, dispc->gfx_position);
+ dispc_reg_out(DISPC_GFX_SIZE, dispc->gfx_size);
+ dispc_reg_out(DISPC_GFX_ATTRIBUTES, dispc->gfx_attributes);
+ dispc_reg_out(DISPC_GFX_FIFO_SIZE,dispc->gfx_fifo_size);
+ dispc_reg_out(DISPC_GFX_FIFO_THRESHOLD, dispc->gfx_fifo_threshold);
+ dispc_reg_out(DISPC_GFX_ROW_INC, dispc->gfx_row_inc);
+ dispc_reg_out(DISPC_GFX_PIXEL_INC, dispc->gfx_pixel_inc);
+ dispc_reg_out(DISPC_GFX_WINDOW_SKIP, dispc->gfx_window_skip);
+ dispc_reg_out(DISPC_GFX_TABLE_BA, dispc->gfx_table_ba);
+
+ break;
+
+ case OMAP2_VIDEO1:
+ dispc_reg_out(DISPC_VID_BA0(v1), dispc->vid1_ba0);
+ dispc_reg_out(DISPC_VID_BA1(v1), dispc->vid1_ba1);
+ dispc_reg_out(DISPC_VID_POSITION(v1), dispc->vid1_position);
+ dispc_reg_out(DISPC_VID_SIZE(v1), dispc->vid1_size);
+ dispc_reg_out(DISPC_VID_ATTRIBUTES(v1), dispc->vid1_attributes);
+ dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v1),dispc->vid1_fifo_threshold);
+ dispc_reg_out(DISPC_VID_ROW_INC(v1), dispc->vid1_row_inc);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(v1), dispc->vid1_pixel_inc);
+ dispc_reg_out(DISPC_VID_FIR(v1), dispc->vid1_fir);
+ dispc_reg_out(DISPC_VID_ACCU0(v1), dispc->vid1_accu0);
+ dispc_reg_out(DISPC_VID_ACCU1(v1), dispc->vid1_accu1);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(v1), dispc->vid1_picture_size);
+
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,0), dispc->vid1_fir_coef_h0);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,1), dispc->vid1_fir_coef_h1);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,2), dispc->vid1_fir_coef_h2);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,3), dispc->vid1_fir_coef_h3);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,4), dispc->vid1_fir_coef_h4);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,5), dispc->vid1_fir_coef_h5);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,6), dispc->vid1_fir_coef_h6);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v1,7), dispc->vid1_fir_coef_h7);
+
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,0), dispc->vid1_fir_coef_hv0);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,1), dispc->vid1_fir_coef_hv1);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,2), dispc->vid1_fir_coef_hv2);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,3), dispc->vid1_fir_coef_hv3);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,4), dispc->vid1_fir_coef_hv4);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,5), dispc->vid1_fir_coef_hv5);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,6), dispc->vid1_fir_coef_hv6);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v1,7), dispc->vid1_fir_coef_hv7);
+
+ dispc_reg_out(DISPC_VID_CONV_COEF0(v1), dispc->vid1_conv_coef0);
+ dispc_reg_out(DISPC_VID_CONV_COEF1(v1), dispc->vid1_conv_coef1);
+ dispc_reg_out(DISPC_VID_CONV_COEF2(v1), dispc->vid1_conv_coef2);
+ dispc_reg_out(DISPC_VID_CONV_COEF3(v1), dispc->vid1_conv_coef3);
+ dispc_reg_out(DISPC_VID_CONV_COEF4(v1), dispc->vid1_conv_coef4);
+ break;
+
+ case OMAP2_VIDEO2:
+ dispc_reg_out(DISPC_VID_BA0(v2), dispc->vid2_ba0);
+ dispc_reg_out(DISPC_VID_BA1(v2), dispc->vid2_ba1);
+ dispc_reg_out(DISPC_VID_POSITION(v2), dispc->vid2_position);
+ dispc_reg_out(DISPC_VID_SIZE(v2), dispc->vid2_size);
+ dispc_reg_out(DISPC_VID_ATTRIBUTES(v2), dispc->vid2_attributes);
+ dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v2),dispc->vid2_fifo_threshold);
+ dispc_reg_out(DISPC_VID_ROW_INC(v2), dispc->vid2_row_inc);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(v2), dispc->vid2_pixel_inc);
+ dispc_reg_out(DISPC_VID_FIR(v2), dispc->vid2_fir);
+ dispc_reg_out(DISPC_VID_ACCU0(v2), dispc->vid2_accu0);
+ dispc_reg_out(DISPC_VID_ACCU1(v2), dispc->vid2_accu1);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(v2), dispc->vid2_picture_size);
+
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,0), dispc->vid2_fir_coef_h0);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,1), dispc->vid2_fir_coef_h1);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,2), dispc->vid2_fir_coef_h2);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,3), dispc->vid2_fir_coef_h3);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,4), dispc->vid2_fir_coef_h4);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,5), dispc->vid2_fir_coef_h5);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,6), dispc->vid2_fir_coef_h6);
+ dispc_reg_out(DISPC_VID_FIR_COEF_H(v2,7), dispc->vid2_fir_coef_h7);
+
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,0), dispc->vid2_fir_coef_hv0);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,1), dispc->vid2_fir_coef_hv1);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,2), dispc->vid2_fir_coef_hv2);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,3), dispc->vid2_fir_coef_hv3);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,4), dispc->vid2_fir_coef_hv4);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,5), dispc->vid2_fir_coef_hv5);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,6), dispc->vid2_fir_coef_hv6);
+ dispc_reg_out(DISPC_VID_FIR_COEF_HV(v2,7), dispc->vid2_fir_coef_hv7);
+
+ dispc_reg_out(DISPC_VID_CONV_COEF0(v2), dispc->vid2_conv_coef0);
+ dispc_reg_out(DISPC_VID_CONV_COEF1(v2), dispc->vid2_conv_coef1);
+ dispc_reg_out(DISPC_VID_CONV_COEF2(v2), dispc->vid2_conv_coef2);
+ dispc_reg_out(DISPC_VID_CONV_COEF3(v2), dispc->vid2_conv_coef3);
+ dispc_reg_out(DISPC_VID_CONV_COEF4(v2), dispc->vid2_conv_coef4);
+ break;
+ }
+}
+
+/*
+ * Sync Lost interrupt handler
+ */
+static void
+omap2_synclost_isr(void *arg, struct pt_regs *regs)
+{
+ int i = 0;
+
+ printk(KERN_WARNING "Sync Lost LCD %x\n",dispc_reg_in(DISPC_IRQSTATUS));
+ arg = NULL; regs = NULL;
+
+ /*
+ * Disable and Clear all the interrupts before we start
+ */
+ dispc_reg_out(DISPC_IRQENABLE, 0x00000000);
+ dispc_reg_out(DISPC_IRQSTATUS, 0x0000FFFF);
+
+ /* disable the display controller */
+ omap2_disp_disable(HZ/5);
+
+ /*
+ * Update the state of the display controller.
+ */
+#if 0
+ dss_ctx.dispc.sysconfig &= ~DISPC_SYSCONFIG_SOFTRESET;
+ dss_ctx.dispc.control &= ~(DISPC_CONTROL_GODIGITAL |
+ DISPC_CONTROL_GOLCD);
+#endif
+ /* TV is disabled when LPR is enabled */
+ dss_ctx.dispc.control |= DISPC_CONTROL_GOLCD;
+#ifdef CONFIG_ARCH_OMAP34XX
+ if (!lpr_enabled)
+#endif
+ dss_ctx.dispc.control |= DISPC_CONTROL_GODIGITAL;
+
+ dispc_reg_out(DISPC_SYSCONFIG, DISPC_SYSCONFIG_SOFTRESET);
+ while (!(dispc_reg_in(DISPC_SYSSTATUS) & DISPC_SYSSTATUS_RESETDONE)) {
+ udelay (100);
+ if (i++ > 5)
+ {
+ printk(KERN_WARNING "Failed to soft reset the DSS !! \n");
+ break;
+ }
+ }
+
+ /* Configure the VENC for the default standard */
+#ifndef CONFIG_ARCH_OMAP3410
+ if ((omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO1) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO2) == OMAP2_OUTPUT_TV))
+ {
+ omap2_disp_set_tvstandard(NTSC_M);
+ }
+#endif
+
+ /* Restore the registers */
+ omap2_disp_restore_ctx(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_restore_ctx(OMAP2_GRAPHICS);
+ omap2_disp_restore_ctx(OMAP2_VIDEO1);
+ omap2_disp_restore_ctx(OMAP2_VIDEO2);
+
+ /* enable the display controller */
+ if (layer[OMAP_DSS_DISPC_GENERIC].ctx_valid)
+ dispc_reg_out(DISPC_CONTROL, dss_ctx.dispc.control);
+
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+ if ((omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO1) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO2) == OMAP2_OUTPUT_TV))
+ {
+ omap2_disp_reg_sync(OMAP2_OUTPUT_TV);
+ }
+}
+
+static inline u32
+pages_per_side(u32 img_side, u32 page_exp)
+{
+ /* page_side = 2 ^ page_exp
+ * (page_side - 1) is added for rounding up
+ */
+ return (u32) (img_side + (1<<page_exp) - 1) >> page_exp;
+}
+
+static int get_vrfb_offset(u32 img_len, u32 bytes_per_pixel,int side)
+{
+ int page_width_exp, page_height_exp, pixel_size_exp,offset =0;
+
+ /* Maximum supported is 4 bytes (RGB32) */
+ if (bytes_per_pixel > 4)
+ return -EINVAL;
+
+ page_width_exp = PAGE_WIDTH_EXP;
+ page_height_exp = PAGE_HEIGHT_EXP;
+ pixel_size_exp = bytes_per_pixel >> 1;
+
+ if(side == SIDE_W){
+ offset = ((1<<page_width_exp) *
+ (pages_per_side(img_len * bytes_per_pixel, page_width_exp))
+ ) >> pixel_size_exp; /* in pixels */
+ }
+ else{
+ offset = (1<<page_height_exp) *
+ (pages_per_side(img_len, page_height_exp));
+ }
+
+ return (offset);
+}
+
+/* Flip the video overlay framebuffer. The video overlay window may
initially
+ * be either enabled or disabled. The overlay window will be enabled by this
+ * routine. fb_base_phys is the physical base address of the framebuffer for
+ * the video overlay. The address programmed into the base address register
of
+ * the video overlay window is calculated based on the cropped size and the
full
+ * size of the overlay framebuffer.
+ */
+void
+omap2_disp_start_vlayer(int ltype, struct v4l2_pix_format *pix,
+ struct v4l2_rect *crop, struct v4l2_window *win, unsigned long
fb_base_phys,
+ int rotation_deg, int mirroring)
+{
+ unsigned long cropped_base_phys;
+ int v, ps = 2,temp_ps=2,vr_ps = 1;
+ int offset=0, ctop=0, cleft=0, line_length=0;
+ int overlay_opt_delta, overlay_opt_enable = 0;
+ int gfx_posX, gfx_posY, vid_posX, vid_posY;
+ int gfx_sizeX, gfx_sizeY, vid_sizeX, vid_sizeY;
+ int screen_width, screen_height;
+ int bytesperpixel;
+ int X, Y, skip_val;
+ int gfx_pix_inc, gfx_row_inc;
+ u32 gfx_format;
+ int flicker_filter = 0;
+
+ gfx_format = dispc_reg_in(DISPC_GFX_ATTRIBUTES);
+
+ if ((omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV) &&
+ ((win->w.width == crop->width) && (win->w.height == crop->height)))
+ flicker_filter = 1;
+
+ switch (gfx_format & DISPC_GFX_ATTRIBUTES_GFXFORMAT) {
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1:
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2:
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4:
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8:
+ bytesperpixel = 1;
+ break;
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12:
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16:
+ bytesperpixel = 2;
+ break;
+ case DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24:
+ default:
+ bytesperpixel = 4;
+ break;
+ }
+
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ /*
+ * If pixel format is YUV then PS = 4, for RGB16 PS = 2 RGB24 Unpack PS =4
+ */
+
+ if (V4L2_PIX_FMT_YUYV == pix->pixelformat ||
+ V4L2_PIX_FMT_UYVY == pix->pixelformat) {
+ if (rotation_deg >= 0 || mirroring == 1){
+ /*
+ * ps - Actual pixel size for YUYV/UYVY for VRFB/Mirroring is 4 bytes
+ * vr_ps - Virtually pixel size for YUYV/UYVY is 2 bytes
+ */
+ ps = 4;
+ vr_ps = 2;
+ }
+ else
+ ps = 2; /* otherwise the pixel size is 2 byte */
+ }
+ else if(V4L2_PIX_FMT_RGB32 == pix->pixelformat) ps = 4;
+ else if(V4L2_PIX_FMT_RGB24 == pix->pixelformat) ps = 3;
+
+ /*
+ * If rotation is selected then compute the rotation parameters
+ */
+ if (rotation_deg >= 0) {
+ line_length = MAX_PIXELS_PER_LINE;
+ ctop = (pix->height - crop->height) - crop->top;
+ cleft = (pix->width - crop->width) - crop->left;
+ }
+ else {
+ line_length = pix->width;
+ }
+ switch (rotation_deg) {
+ case 90:
+ offset = (get_vrfb_offset(pix->width,ps,SIDE_H) - (pix->width/vr_ps)) * ps
* line_length;
+ temp_ps = ps/vr_ps;
+ if (mirroring == 0) {
+ cropped_base_phys = fb_base_phys + offset +
+ line_length * temp_ps * cleft + crop->top * temp_ps;
+ }
+ else{
+ cropped_base_phys =
+ fb_base_phys + offset +
+ line_length * temp_ps * cleft + crop->top * temp_ps +
+ (line_length * ( (crop->width/(vr_ps)) - 1) * ps);
+ }
+ break;
+
+ case 180:
+ offset = (get_vrfb_offset(pix->height,ps,SIDE_H) - pix->height) * ps *
line_length +
+ (get_vrfb_offset(pix->width,ps,SIDE_W) - (pix->width/vr_ps)) * ps;
+ if (mirroring == 0) {
+ cropped_base_phys = fb_base_phys + offset +
+ (line_length * ps * ctop) + (cleft/vr_ps) * ps;
+ }
+ else {
+ cropped_base_phys =
+ fb_base_phys + offset + (line_length * ps * ctop) +
+ (cleft/vr_ps) * ps +
+ (line_length * (crop->height - 1) * ps);
+ }
+ break;
+
+ case 270:
+ offset = (get_vrfb_offset(pix->height,ps,SIDE_W) - pix->height) * ps;
+ temp_ps = ps/vr_ps;
+ if (mirroring == 0) {
+ cropped_base_phys = fb_base_phys + offset +
+ line_length * temp_ps * crop->left + ctop * ps;
+ }
+ else {
+ cropped_base_phys =
+ fb_base_phys + offset + line_length * temp_ps * crop->left +
+ ctop * ps +
+ (line_length * ( (crop->width/vr_ps) - 1) * ps);
+ }
+ break;
+
+ case 0:
+ if (mirroring == 0) {
+ cropped_base_phys = fb_base_phys
+ + (line_length * ps) * crop->top + (crop->left/vr_ps) * ps;
+ }
+ else {
+ cropped_base_phys =
+ fb_base_phys + (line_length * ps) * crop->top +
+ (crop->left/vr_ps) * ps +
+ (line_length * (crop->height - 1) * ps);
+ }
+ break;
+
+ default:
+ if (mirroring == 0) {
+ cropped_base_phys = fb_base_phys
+ + line_length * ps * crop->top + crop->left * ps;
+ }
+ else {
+ cropped_base_phys = fb_base_phys
+ + (line_length * ps * crop->top) / vr_ps +
+ (crop->left * ps) / vr_ps +
+ ((crop->width / vr_ps) - 1) * ps;
+ }
+ break;
+ }
+
+ /*
+ * We store the information in the layer structure for : If user
+ * dynamically switches the pipeline from LCD to TV or vice versa
+ * we should have the necessary configurations for the output device
+ * (LCD/TV)
+ */
+
+ /*
+ * For LCD BA0 and BA1 are same
+ */
+ layer[ltype].dma[0].ba0 = cropped_base_phys;
+ layer[ltype].dma[0].ba1 = cropped_base_phys;
+
+ /*
+ * Store BA0 BA1 for TV, BA1 points to the alternate row
+ */
+ layer[ltype].dma[1].ba0 = cropped_base_phys;
+
+ if (flicker_filter == 1){
+ layer[ltype].dma[1].ba1 = cropped_base_phys;
+ } else if(rotation_deg >= 0){
+ if(mirroring == 1)
+ layer[ltype].dma[1].ba1 = cropped_base_phys - line_length * ps;
+ else
+ layer[ltype].dma[1].ba1 = cropped_base_phys + line_length * ps;
+ } else {
+ if (mirroring == 1)
+ layer[ltype].dma[1].ba1 = cropped_base_phys + line_length * ps/vr_ps;
+ else
+ layer[ltype].dma[1].ba1 = cropped_base_phys + line_length * ps;
+ }
+
+
+ /* If output path is set to TV */
+ if (omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV) {
+ dispc_reg_out(DISPC_VID_BA0(v), cropped_base_phys);
+ if(flicker_filter == 1){
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys);
+ } else {
+ if(rotation_deg >= 0){
+ if(mirroring == 1)
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys -
+ line_length * ps);
+ else
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys +
+ line_length * ps);
+ }
+ else{
+ if(mirroring ==1)
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys +
+ line_length * ps/vr_ps);
+ else
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys +
+ line_length * ps);
+ }
+ }
+
+ dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
+ DISPC_VID_ATTRIBUTES_ENABLE,
+ DISPC_VID_ATTRIBUTES_ENABLE);
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GODIGITAL,
+ DISPC_CONTROL_GODIGITAL);
+
+ /* if not enabled transparency and alpha blending enable overlay
optimization */
+ if(is_sil_rev_less_than(OMAP3430_REV_ES2_0)){
+ if (!(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKDIGENABLE))
+ overlay_opt_enable = 1;
+ }
+ else {
+ if ((!(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKDIGENABLE)) && (!
(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TVALPHAENABLE)))
+ overlay_opt_enable = 1;
+ }
+ }
+ /* If output path is set to LCD */
+ else {
+ dispc_reg_out(DISPC_VID_BA0(v), cropped_base_phys);
+ dispc_reg_out(DISPC_VID_BA1(v), cropped_base_phys);
+ dispc_reg_merge(DISPC_VID_ATTRIBUTES(v),
+ DISPC_VID_ATTRIBUTES_ENABLE,
+ DISPC_VID_ATTRIBUTES_ENABLE);
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+
+ /* if not enabled transparency enable overlay optimization */
+ if(is_sil_rev_less_than(OMAP3430_REV_ES2_0)){
+ if (!(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKLCDENABLE))
+ overlay_opt_enable = 1;
+ }
+ else {
+ if ((!(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKLCDENABLE)) && (!
(dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_LCDALPHAENABLE)))
+ overlay_opt_enable = 1;
+ }
+ }
+
+ /** if GFX pipeline enabled and no transparency enabled
+ * check for overlapping of GFX and Video pipelines to
+ * enable overlay optimization
+ */
+ if ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) & DISPC_GFX_ATTRIBUTES_ENABLE ) &&
overlay_opt_enable && (ltype == OMAP2_VIDEO1)) {
+
+ gfx_posX = (dispc_reg_in(DISPC_GFX_POSITION) & DISPC_GFX_POSITION_GFXPOSX)
>> DISPC_GFX_POSITION_GFXPOSX_SHIFT;
+ gfx_posY = (dispc_reg_in(DISPC_GFX_POSITION) & DISPC_GFX_POSITION_GFXPOSY)
>> DISPC_GFX_POSITION_GFXPOSY_SHIFT;
+ gfx_sizeX = (dispc_reg_in(DISPC_GFX_SIZE) & DISPC_GFX_SIZE_GFXSIZEX) >>
DISPC_GFX_SIZE_GFXSIZEX_SHIFT;
+ gfx_sizeY = (dispc_reg_in(DISPC_GFX_SIZE) & DISPC_GFX_SIZE_GFXSIZEY) >>
DISPC_GFX_SIZE_GFXSIZEY_SHIFT;
+ vid_posX = (dispc_reg_in(DISPC_VID_POSITION(v)) &
DISPC_VID_POSITION_VIDPOSX) >> DISPC_VID_POSITION_VIDPOSX_SHIFT;
+ vid_posY = (dispc_reg_in(DISPC_VID_POSITION(v)) &
DISPC_VID_POSITION_VIDPOSY) >> DISPC_VID_POSITION_VIDPOSY_SHIFT;
+ vid_sizeX = ((dispc_reg_in(DISPC_VID_SIZE(v)) & DISPC_VID_SIZE_VIDSIZEX) >>
DISPC_VID_SIZE_VIDSIZEX_SHIFT) + 1;
+ vid_sizeY = ((dispc_reg_in(DISPC_VID_SIZE(v)) & DISPC_VID_SIZE_VIDSIZEY) >>
DISPC_VID_SIZE_VIDSIZEY_SHIFT) + 1;
+ gfx_pix_inc = dispc_reg_in(DISPC_GFX_PIXEL_INC);
+ gfx_row_inc = dispc_reg_in(DISPC_GFX_ROW_INC);
+
+ omap2_disp_get_panel_size(omap2_disp_get_output_dev(ltype), &screen_width,
&screen_height);
+
+ if (((gfx_posX + gfx_sizeX) <= vid_posX) || ((gfx_posY + gfx_sizeY) <=
vid_posY)) {
+ overlay_opt_enable = 0;
+ }
+ }
+ else {
+ overlay_opt_enable = 0;
+ }
+
+ /* Enable overlay optimization */
+ if (overlay_opt_enable) {
+ X = vid_sizeX;
+
+ if ((vid_posX == 0) && (gfx_sizeX <= (vid_posX + vid_sizeX))) {
+ X = gfx_sizeX + 1;
+ Y = vid_sizeY + 1;
+ skip_val = Y * ((X - 1) * (gfx_pix_inc - 1 + bytesperpixel) +
+ (gfx_row_inc - 1 + bytesperpixel));
+ goto skip;
+ }
+
+ if ((vid_posX + vid_sizeX) >= gfx_sizeX) {
+ X = gfx_sizeX - vid_posX + 1;
+ }
+
+ if ((vid_posX == 0) || (gfx_sizeX <= (vid_posX + vid_sizeX))) {
+ overlay_opt_delta = 0;
+ }
+ else {
+ overlay_opt_delta = 1;
+ }
+ skip_val = (X * (gfx_pix_inc + bytesperpixel - 1) + overlay_opt_delta);
+
+skip: dispc_reg_out(DISPC_GFX_WINDOW_SKIP,skip_val);
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_OVERLAYOPTIMIZATION,
+ DISPC_CONTROL_OVERLAYOPTIMIZATION);
+ }
+}
+
+
+/* Configure VIDEO1 or VIDEO2 layer parameters*/
+void
+omap2_disp_config_vlayer(int ltype, struct v4l2_pix_format *pix,
+ struct v4l2_rect *crop, struct v4l2_window *win,
+ int rotation_deg, int mirroring)
+{
+ int vid_position_x, vid_position_y, ps = 2,vr_ps = 1;
+ unsigned long vid_position, vid_size, vid_picture_size;
+ unsigned long vid_attributes;
+ unsigned long firvinc, firhinc;
+ int winheight, winwidth, cropheight, cropwidth, pixheight, pixwidth;
+ int cleft, ctop;
+ int panelwidth, panelheight, row_inc_value=0, pixel_inc_value=0;
+ int flicker_filter = 0;
+
+ /* vertical resizing matrix */
+ const static short int vc[3][8] =
+ { { 0, 3, 12, 32, 0, 7, 5, 2 },
+ { 128, 123, 111, 89, 64, 89, 111, 123 },
+ { 0, 2, 5, 7, 64, 32, 12, 3 } };
+ /* horizontal resizing matrix */
+ const static short int hc[5][8] =
+ { { 0, -1, -2, -5, 0, -2, -1, 0 },
+ { 0, 13, 30, 51, -9, -11, -11, -8 },
+ { 128, 124, 112, 95, 73, 95, 112, 124 },
+ { 0, -8, -11, -11, 73, 51, 30, 13 },
+ { 0, 0, -1, -2, -9, -5, -2, -1 } };
+ int v;
+
+ if (ltype == OMAP2_VIDEO1) v = 0;
+ else if (ltype == OMAP2_VIDEO2) v = 1;
+ else return;
+
+ if ((omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV) &&
+ ((win->w.width == crop->width) && (win->w.height == crop->height)))
+ flicker_filter = 1;
+
+
+ /* make sure the video overlay is disabled before we reconfigure it */
+ omap2_disp_disable_layer(ltype);
+
+ /* configure the video attributes register */
+ vid_attributes = 0;
+ switch (pix->pixelformat) {
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_UYVY:
+ if(pix->pixelformat == V4L2_PIX_FMT_YUYV){
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_YUV2;
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDCOLORCONVENABLE;
+ }
+ else{
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_UYVY;
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDCOLORCONVENABLE;
+ }
+
+ if (mirroring == 1 || rotation_deg >=0){
+ /*
+ * ps - In VRFB space the pixel size for YUYV/UYVY is 4 bytes
+ * vr_ps - Actual pixel size for YUYV/UYVY is 2 bytes
+ */
+ ps = 4;vr_ps = 2;
+ }
+ if (rotation_deg >= 0) {
+ if(mirroring == 1){
+ vid_attributes |= (rotation_deg == 90)?
+ ((0x3) << DISPC_VID_ATTRIBUTES_VIDROT):
+ (rotation_deg == 270)?((0x1) << DISPC_VID_ATTRIBUTES_VIDROT):
+ (rotation_deg == 0)?(0x2 << DISPC_VID_ATTRIBUTES_VIDROT):
+ (0<<DISPC_VID_ATTRIBUTES_VIDROT);
+ }
+ else{
+ vid_attributes |= (rotation_deg == 90)?
+ ((0x3) << DISPC_VID_ATTRIBUTES_VIDROT):
+ (rotation_deg == 270)?((0x1) << DISPC_VID_ATTRIBUTES_VIDROT):
+ ((rotation_deg / 90) << DISPC_VID_ATTRIBUTES_VIDROT);
+ }
+ vid_attributes |= (rotation_deg == 90 || rotation_deg == 270)?
+ (1 << DISPC_VID_ATTRIBUTES_VIDROWREPEAT):
+ (0 << DISPC_VID_ATTRIBUTES_VIDROWREPEAT);
+ }
+ if (mirroring == 1 && rotation_deg == -1){
+ vid_attributes |= (0x2 << DISPC_VID_ATTRIBUTES_VIDROT);
+ }
+
+ break;
+ case V4L2_PIX_FMT_RGB24:
+ ps = 3; /* pixel size is 3 bytes */
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB24P;
+ vid_attributes |= ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) &
+ DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE)
+ << DISPC_GFX_ATTRIBUTES_GFXREPEN);
+ break;
+
+ /* The picture format is a bit confusing in V4L2.. as per the V4L2 spec
+ * RGB32 and BGR32 are always with alpha bits enabled.. (i.e always in
+ * packed mode) */
+ case V4L2_PIX_FMT_RGB32:
+ ps = 4; /* pixel size is 4 bytes */
+ if ((is_sil_rev_less_than(OMAP3430_REV_ES2_0)) || (ltype == OMAP2_VIDEO1))
{
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB24;
+ vid_attributes |= ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) &
+ DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE)
+ << DISPC_GFX_ATTRIBUTES_GFXREPEN);
+ }
+ else {
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_ARGB32;
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDENDIANNESS;
+ }
+ break;
+ case V4L2_PIX_FMT_BGR32:
+ ps = 4; /* pixel size is 4 bytes */
+ if ((is_sil_rev_less_than(OMAP3430_REV_ES2_0)) || (ltype == OMAP2_VIDEO1))
{
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB24;
+ vid_attributes |= ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) &
+ DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE)
+ << DISPC_GFX_ATTRIBUTES_GFXREPEN);
+ }
+ else {
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_ARGB32;
+ }
+ break;
+ case V4L2_PIX_FMT_RGB565:
+ default:
+ ps = 2; /* pixel size is 2 bytes */
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB16;
+ vid_attributes |= ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) &
+ DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE)
+ << DISPC_GFX_ATTRIBUTES_GFXREPEN);
+ break;
+ case V4L2_PIX_FMT_RGB565X:
+ ps = 2; /* pixel size is 2 bytes */
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB16;
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDENDIANNESS;
+ vid_attributes |= ((dispc_reg_in(DISPC_GFX_ATTRIBUTES) &
+ DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE)
+ << DISPC_GFX_ATTRIBUTES_GFXREPEN);
+ break;
+ }
+
+ if (omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV)
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDCHANNELOUT;
+
+ /* Enable 16 x 32 burst size */
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST16X32;
+
+ /* Set FIFO threshold to 0xFF (high) and 0xFF - (16x4bytes) = 0xC0 (low)*/
+ // dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v),0x00FF00C0);
+ dispc_reg_out(DISPC_VID_FIFO_THRESHOLD(v),0x03FC03BC);
+
+ /* Set the color converion parameters */
+ set_colorconv(v,pix->colorspace);
+
+ if (rotation_deg == 90 || rotation_deg == 270) {
+ winheight = win->w.width;
+ winwidth = win->w.height;
+ cropheight = crop->width;
+ cropwidth = crop->height;
+ pixheight = pix->width;
+ pixwidth = pix->height;
+ cleft = crop->top;
+ ctop = crop->left;
+ } else {
+ winwidth = win->w.width;
+ winheight = win->w.height;
+ cropwidth = crop->width;
+ cropheight = crop->height;
+ pixheight = pix->height;
+ pixwidth = pix->width;
+ ctop = crop->top;
+ cleft = crop->left;
+ }
+
+#ifdef DMA_DECIMATE
+ printk("winwidth = %d \n",win->w.width);
+ printk("winheight = %d \n",win->w.height);
+ printk("pixwidth = %d \n",pix->width);
+ printk("pixheigth = %d \n",pix->height);
+ printk("cropwidth = %d \n",crop->width);
+ printk("cropheigth = %d \n",crop->height);
+ printk("croptop = %d \n",crop->top);
+ printk("cropleft = %d \n",crop->left);
+#endif
+
+ if (winwidth != cropwidth) {
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_HRESIZE;
+ if (winwidth < cropwidth)
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDHRESIZECONF;
+ }
+ if (winheight != cropheight) {
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_VRESIZE;
+ if (winheight < cropheight)
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDVRESIZECONF;
+ }
+
+ if (flicker_filter == 1) {
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_VRESIZE;
+ vid_attributes |= DISPC_VID_ATTRIBUTES_VIDVRESIZECONF;
+ }
+
+ dispc_reg_out(DISPC_VID_ATTRIBUTES(v), vid_attributes);
+
+ /* initialize the resizing filter */
+ omap2_disp_set_resize(v, vc, hc);
+
+ dispc_reg_out(DISPC_VID_ACCU0(v), 0);
+ if(flicker_filter == 1)
+ dispc_reg_out(DISPC_VID_ACCU1(v), 0x01000000);
+ else
+ dispc_reg_out(DISPC_VID_ACCU1(v), 0);
+
+ firhinc = (1024 * (cropwidth - 1)) / (winwidth - 1);
+ if (firhinc < 1)
+ firhinc = 1;
+ else if (firhinc > 2047)
+ firhinc = 2047;
+ firvinc = (1024 * (cropheight - 1)) / (winheight - 1);
+ if (firvinc < 1)
+ firvinc = 1;
+ else if (firvinc > 2047)
+ firvinc = 2047;
+
+ if(flicker_filter == 0)
+ dispc_reg_out(DISPC_VID_FIR(v), firhinc | (firvinc << 16));
+ else
+ dispc_reg_out(DISPC_VID_FIR(v), 0x08000000);
+
+ omap2_disp_get_panel_size(omap2_disp_get_output_dev(ltype), &panelwidth,
+ &panelheight);
+
+ /* configure the target window on the display */
+ switch (rotation_deg) {
+
+ case 90:
+ vid_position_y = (panelheight - win->w.width) - win->w.left;
+ vid_position_x = win->w.top;
+ break;
+
+ case 180:
+ vid_position_x = (panelwidth - win->w.width) - win->w.left;
+ vid_position_y = (panelheight - win->w.height) - win->w.top;
+ break;
+
+ case 270:
+ vid_position_y = win->w.left;
+ vid_position_x = (panelwidth - win->w.height) - win->w.top;
+ break;
+
+ default:
+ vid_position_x = win->w.left;
+ vid_position_y = win->w.top;
+ break;
+ }
+
+ if (omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV)
+ vid_position_y = vid_position_y/2;
+
+ /*
+ * If Scaling is enabled for TV then the window height should be divided by
two
+ */
+
+ if (((omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV) &&
+ (winheight != cropheight)) || flicker_filter) {
+ vid_size = (((winwidth - 1) << DISPC_VID_SIZE_VIDSIZEX_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEX)
+ | ((((winheight - 1)/2) << DISPC_VID_SIZE_VIDSIZEY_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEY);
+ } else {
+ vid_size = (((winwidth - 1) << DISPC_VID_SIZE_VIDSIZEX_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEX)
+ | (((winheight - 1) << DISPC_VID_SIZE_VIDSIZEY_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEY);
+#ifdef DMA_DECIMATE
+ vid_size = (((winwidth - 1)/2 << DISPC_VID_SIZE_VIDSIZEX_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEX)
+ | ((((winheight - 1)/2) << DISPC_VID_SIZE_VIDSIZEY_SHIFT)
+ & DISPC_VID_SIZE_VIDSIZEY);
+#endif
+ }
+
+ /* configure the source window in the framebuffer */
+ if(flicker_filter == 1){
+ vid_picture_size =
+ (((cropwidth - 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((cropheight - 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ } else if((omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_TV) &&
(flicker_filter == 0)) {
+ vid_picture_size =
+ (((cropwidth -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((cropheight / 2 -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ } else {
+ vid_picture_size =
+ (((cropwidth -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((cropheight -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+#ifdef DMA_DECIMATE
+ vid_picture_size =
+ (((cropwidth / 2 -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((cropheight / 2 -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+#endif
+ }
+
+ switch (mirroring) {
+ case 0: /* No mirroring */
+ if (rotation_deg == 90 || rotation_deg == 270) {
+ row_inc_value =
+ 1 + (MAX_PIXELS_PER_LINE - pixwidth +
+ (pixwidth - cropwidth - cleft) + cleft) * ps;
+
+ }
+ else if (rotation_deg == 180 || rotation_deg == 0) {
+ if (V4L2_PIX_FMT_YUYV == pix->pixelformat
+ || V4L2_PIX_FMT_UYVY == pix->pixelformat)
+ row_inc_value =
+ 1 + (MAX_PIXELS_PER_LINE -
+ (pixwidth/ vr_ps) + ((pixwidth - cropwidth - cleft)/vr_ps)
+ + (cleft / vr_ps) ) * ps;
+
+ else
+ row_inc_value =
+ 1 + (MAX_PIXELS_PER_LINE - pixwidth +
+ (pixwidth -
+ cropwidth - cleft) + cleft) * ps;
+#ifdef DMA_DECIMATE
+ row_inc_value = row_inc_value + (MAX_PIXELS_PER_LINE * ps);
+#endif
+ }
+ else {
+ row_inc_value = 1 + (pix->width * ps) - cropwidth * ps;
+#ifdef DMA_DECIMATE
+ row_inc_value = row_inc_value + ((pix->width + 1) * ps);
+#endif
+ }
+ pixel_inc_value = 1;
+#ifdef DMA_DECIMATE
+ pixel_inc_value = 1+ (1* ps);
+#endif
+ break;
+
+ case 1: /* Mirroring */
+ if (rotation_deg == 90 || rotation_deg == 270) {
+ row_inc_value = (-(MAX_PIXELS_PER_LINE + cropwidth) * ps) + 1;
+ pixel_inc_value = 1;
+ } else if (rotation_deg == 180 || rotation_deg == 0) {
+ row_inc_value = (-(MAX_PIXELS_PER_LINE + (cropwidth / vr_ps))
+ * ps) + 1;
+ pixel_inc_value = 1;
+ } else {
+ row_inc_value =
+ 2 * ((cropwidth / vr_ps) -
+ 1) * ps + 1 +
+ ((pix->width * ps) / vr_ps) -
+ (cropwidth / vr_ps) * ps;
+ pixel_inc_value = (-2 * ps) + 1;
+ }
+ break;
+ } /* Mirroring Switch */
+
+ /*
+ * For LCD row inc and pixel inc
+ */
+
+ layer[ltype].dma[0].row_inc = row_inc_value;
+ layer[ltype].dma[0].pix_inc = pixel_inc_value;
+
+ if (omap2_disp_get_output_dev(ltype) == OMAP2_OUTPUT_LCD || flicker_filter
== 1) {
+ dispc_reg_out(DISPC_VID_ROW_INC(v), row_inc_value);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(v), pixel_inc_value);
+ }
+
+ /*
+ * For TV the row increment should be done twice as the
+ * TV operates in interlaced mode
+ */
+
+ else {
+ if (rotation_deg >= 0){
+ if(mirroring ==1) row_inc_value = row_inc_value -
+ MAX_PIXELS_PER_LINE * ps;
+ else row_inc_value = row_inc_value + MAX_PIXELS_PER_LINE * ps;
+ }
+ else{
+ if(mirroring ==1) row_inc_value = row_inc_value +
+ pix->width * ps / vr_ps;
+ else row_inc_value = row_inc_value + pix->width * ps;
+ }
+ dispc_reg_out(DISPC_VID_ROW_INC(v), row_inc_value);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(v), pixel_inc_value);
+ }
+
+ /*
+ * Store BA0 BA1 for TV, BA1 points to the alternate row
+ */
+ if(flicker_filter == 1){
+ layer[ltype].dma[1].row_inc = row_inc_value;
+ } else if (rotation_deg >= 0){
+ if(mirroring ==1)
+ layer[ltype].dma[1].row_inc = row_inc_value -
+ MAX_PIXELS_PER_LINE * ps;
+ else
+ layer[ltype].dma[1].row_inc = row_inc_value +
+ MAX_PIXELS_PER_LINE * ps;
+ }
+ else{
+ if(mirroring ==1)
+ layer[ltype].dma[1].row_inc =
+ row_inc_value + pix->width * ps/vr_ps;
+ else row_inc_value = row_inc_value + pix->width * ps;
+
+ }
+ layer[ltype].dma[1].pix_inc = pixel_inc_value;
+ layer[ltype].size_x = cropwidth;
+ layer[ltype].size_y = cropheight;
+
+ vid_position = ((vid_position_x << DISPC_VID_POSITION_VIDPOSX_SHIFT)
+ & DISPC_VID_POSITION_VIDPOSX)
+ | ((vid_position_y << DISPC_VID_POSITION_VIDPOSY_SHIFT)
+ & DISPC_VID_POSITION_VIDPOSY);
+
+ dispc_reg_out(DISPC_VID_POSITION(v), vid_position);
+ dispc_reg_out(DISPC_VID_SIZE(v), vid_size);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(v), vid_picture_size);
+ omap2_disp_save_initstate(ltype);
+
+}
+/*---------------------------------------------------------------------------*/
+
+/* Many display controller registers are shadowed. Setting the GO bit causes
+ * changes to these registers to take effect in hardware.
+ */
+void
+omap2_disp_reg_sync(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+ else
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GODIGITAL,
+ DISPC_CONTROL_GODIGITAL);
+}
+
+/* This function provides the status of the GO bit. After the GO bit is set
+ * through software, register changes take affect at the next VFP (vertical
+ * front porch) or EVSYNC. Per the specs, no further register changes
+ * must be done until the GO bit is reset by hardware. This function allows
+ * drivers to poll the status of the GO bit, and wait until it is reset if
they
+ * wish to.
+ */
+int
+omap2_disp_reg_sync_done(int output_dev)
+{
+ u32 control = dispc_reg_in(DISPC_CONTROL);
+
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ return ~(control & DISPC_CONTROL_GOLCD);
+ else
+ return ~(control & DISPC_CONTROL_GODIGITAL);
+}
+
+#ifndef CONFIG_ARCH_OMAP3410
+ static void
+omap24xx_ll_config_tv_clocks(int sleep_state)
+{
+ static int start = 1;
+ static struct clk *tv_clk;
+ static int disabled = 0;
+ static int enabled = 0;
+
+ if(start) {
+#ifdef CONFIG_MACH_OMAP_2430SDP
+ tv_clk = clk_get(NULL,"dss_54m_fck");
+#endif
+ #if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR) || defined(CONFIG_MACH_OMAP3_BEAGLE)
+ tv_clk = clk_get(NULL,"dss_tv_fck");
+#endif
+ if(IS_ERR(tv_clk)) {
+ printk("\n UNABLE to get dss TV fclk \n");
+ return;
+ }
+ start = 0;
+ }
+
+ if (sleep_state == 1) {
+ if (disabled == 0) {
+ clk_disable(tv_clk);
+ disabled = 1;
+ }
+ enabled = 0;
+ }
+ else {
+ if (enabled == 0) {
+ if(clk_enable(tv_clk) != 0) {
+ printk("\n UNABLE to enable dss TV fclk \n");
+ return;
+ }
+ enabled = 1;
+ }
+ disabled = 0;
+ }
+}
+#endif
+
+/*
+ * Disable the display controller. May be called in interrupt or process
+ * context. However, this function should not be called with interrupts
+ * disabled as jiffies will not increment.
+ */
+void
+omap2_disp_disable(unsigned long timeout_ticks)
+{
+ unsigned long timeout;
+
+ if (dispc_reg_in(DISPC_CONTROL)
+ & (DISPC_CONTROL_DIGITALENABLE | DISPC_CONTROL_LCDENABLE))
+ {
+ /* disable the display controller */
+ dispc_reg_merge(DISPC_CONTROL, 0,
+ DISPC_CONTROL_DIGITALENABLE | DISPC_CONTROL_LCDENABLE);
+
+ /* wait for any frame in progress to complete */
+ dispc_reg_out(DISPC_IRQSTATUS,
+ DISPC_IRQSTATUS_FRAMEDONE);
+ timeout = jiffies + timeout_ticks;
+ while(!(dispc_reg_in(DISPC_IRQSTATUS)
+ & DISPC_IRQSTATUS_FRAMEDONE)
+ && time_before(jiffies, timeout))
+ {
+ int a_ctx = (in_atomic() || irqs_disabled()
+ || in_interrupt());
+ if (!a_ctx) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(1);
+ } else
+ udelay(100);
+ }
+ if (!(dispc_reg_in(DISPC_IRQSTATUS)
+ & DISPC_IRQSTATUS_FRAMEDONE)) {
+ printk(KERN_WARNING "timeout waiting for "
+ "frame-done interrupt\n");
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ omap24xx_ll_config_tv_clocks(1);
+#endif
+ }
+
+ return;
+}
+
+void
+omap2_disp_set_gfx_palette(u32 palette_ba)
+{
+ dispc_reg_out(DISPC_GFX_TABLE_BA, palette_ba);
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_LOADMODE_PGTABUSETB,
+ DISPC_CONFIG_LOADMODE_PGTABUSETB);
+}
+
+/* Configure Graphics layer parameters */
+void
+omap2_disp_config_gfxlayer(u32 size_x, u32 size_y, int color_depth)
+{
+ u32 config = 0;
+ u32 gfx_attributes = 0, gfx_fifo_threshold = 0, gfx_format = 0;
+ u32 gfx_position = 0, gfx_window_skip = 0;
+
+
+ config = dispc_reg_in(DISPC_CONFIG);
+
+ config |= (DISPC_CONFIG_LOADMODE_PGTABUSETB |
+ DISPC_CONFIG_LOADMODE_FRDATLEFR);
+
+ /* This driver doesn't currently support the video windows, so
+ * we force the palette/gamma table to be a palette table and
+ * force both video windows to be disabled.
+ */
+ config &= ~DISPC_CONFIG_PALETTEGAMMATABLE;
+
+ gfx_attributes = DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST16X32;
+
+ /* enable the graphics window only if its size is not zero */
+#if 0
+ if (size_x > 0 && size_y > 0)
+ gfx_attributes |= DISPC_GFX_ATTRIBUTES_ENABLE;
+#endif
+
+ gfx_fifo_threshold =
+ (RMODE_GFX_FIFO_HIGH_THRES << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT) |
+ (RMODE_GFX_FIFO_LOW_THRES << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT);
+
+ gfx_position = 0;
+ gfx_window_skip = 0;
+
+ switch(color_depth) {
+ case 1:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1;
+ break;
+ case 2:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2;
+ break;
+ case 4:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4;
+ break;
+ case 8:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8;
+ break;
+ case 12:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12;
+ break;
+ case 16:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16;
+ break;
+ case 24:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24;
+ break;
+ case 32:
+ gfx_format = DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGBA32;
+ break;
+ default:
+ gfx_format = dispc_reg_in(DISPC_GFX_ATTRIBUTES)
+ & DISPC_GFX_ATTRIBUTES_GFXFORMAT;
+ break;
+ }
+
+ gfx_attributes |= gfx_format;
+
+ dispc_reg_out(DISPC_GFX_FIFO_THRESHOLD, gfx_fifo_threshold);
+ dispc_reg_out(DISPC_GFX_POSITION, gfx_position);
+ dispc_reg_out(DISPC_GFX_WINDOW_SKIP, gfx_window_skip);
+
+ dispc_reg_out(DISPC_CONFIG, config);
+ dispc_reg_out(DISPC_GFX_ATTRIBUTES, gfx_attributes);
+
+ layer[OMAP2_GRAPHICS].size_x = size_x;
+ layer[OMAP2_GRAPHICS].size_y = size_y;
+}
+
+/* Calculate the number of pixels sent to the display per pixel clock as
+ * (nom/den) pixels per clock.
+ */
+void
+omap2_disp_pixels_per_clock(unsigned int *nom, unsigned int *den)
+{
+ u32 dispc_control;
+
+ dispc_control = dispc_reg_in(DISPC_CONTROL);
+
+ if (dispc_control & DISPC_CONTROL_STNTFT) {
+ /* active display (TFT) */
+ if (dispc_control & DISPC_CONTROL_TDMENABLE) {
+ /* TFT with TDM */
+ switch (dispc_control & DISPC_CONTROL_TDMCYCLEFORMAT) {
+ case DISPC_CONTROL_TDMCYCLEFORMAT_1CYCPERPIX:
+ *nom = 1;
+ *den = 1;
+ break;
+ case DISPC_CONTROL_TDMCYCLEFORMAT_2CYCPERPIX:
+ *nom = 1;
+ *den = 2;
+ break;
+ case DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPERPIX:
+ *nom = 1;
+ *den = 3;
+ break;
+ case DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPER2PIX:
+ *nom = 2;
+ *den = 3;
+ break;
+ }
+ }
+ else {
+ /* TFT without TDM */
+ *nom = 1;
+ *den = 1;
+ }
+ }
+ else {
+ /* passive display (STN) */
+ if (dispc_control & DISPC_CONTROL_MONOCOLOR) {
+ /* STN mono */
+ if (dispc_control & DISPC_CONTROL_M8B) {
+ /* 8 pixels per pixclock */
+ *nom = 8;
+ *den = 1;
+ }
+ else {
+ /* 4 pixels per pixclock */
+ *nom = 4;
+ *den = 1;
+ }
+ }
+ else {
+ /* STN color--8 pixels per 3 pixclocks */
+ *nom = 8;
+ *den = 3;
+ }
+ }
+}
+
+/* Configure the signal configuration for LCD panel */
+void
+omap2_disp_lcdcfg_polfreq(u32 hsync_high, u32 vsync_high,
+ u32 acb,u32 ipc, u32 onoff)
+{
+ u32 pol_freq = 0;
+ /* set the sync polarity */
+ if (!hsync_high)
+ pol_freq &= ~DISPC_POL_FREQ_IHS;
+ else
+ pol_freq |= DISPC_POL_FREQ_IHS;
+ if (!vsync_high)
+ pol_freq &= ~DISPC_POL_FREQ_IVS;
+ else
+ pol_freq |= DISPC_POL_FREQ_IVS;
+
+ pol_freq |= acb | (ipc << DISPC_POL_FREQ_IPC_SHIFT) <<
+ (onoff << DISPC_POL_FREQ_ONOFF_SHIFT) ;
+ dispc_reg_out(DISPC_POL_FREQ, pol_freq);
+
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ /* set the sync polarity */
+ if (!hsync_high)
+ pol_freq &= ~DISPC_POL_FREQ_IHS;
+ else
+ pol_freq |= DISPC_POL_FREQ_IHS;
+
+ if (!vsync_high)
+ pol_freq &= ~DISPC_POL_FREQ_IVS;
+ else
+ pol_freq |= DISPC_POL_FREQ_IVS;
+
+ pol_freq |= acb | (ipc << DISPC_POL_FREQ_IPC_SHIFT) <<
+ (onoff << DISPC_POL_FREQ_ONOFF_SHIFT) ;
+ dispc_reg_out(DISPC_POL_FREQ, pol_freq);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+
+}
+
+/* Configure LCD parameters */
+void
+omap2_disp_config_lcd(u32 clkdiv, u32 hbp, u32 hfp, u32 hsw,
+ u32 vbp, u32 vfp, u32 vsw)
+{
+ u32 control, divisor, timing_h, timing_v;
+ divisor = (1 << DISPC_DIVISOR_LCD_SHIFT)
+ | (clkdiv << DISPC_DIVISOR_PCD_SHIFT);
+
+
+ // printk("HARRRI:config_lcd: clkdiv=0x%x,
hbp=0x%x,hfp=0x%x,hsw=0x%x,vbp=0x%x,vfp=0x%x,vsw=0x%x
\n",clkdiv,hbp,hfp,hsw,vbp,vfp,vsw);
+
+ if (hbp > 255) hbp = 255;
+ if (hfp > 255) hfp = 255;
+ if (hsw > 63) hsw = 63;
+ if (vbp > 255) vbp = 255;
+ if (vfp > 255) vfp = 255;
+ if (vsw > 63) vsw = 63;
+
+ timing_h = (hbp << DISPC_TIMING_H_HBP_SHIFT) | (hfp <<
DISPC_TIMING_H_HFP_SHIFT)
+ | (hsw << DISPC_TIMING_H_HSW_SHIFT);
+ timing_v = (vbp << DISPC_TIMING_V_VBP_SHIFT) | (vfp <<
DISPC_TIMING_V_VFP_SHIFT)
+ | (vsw << DISPC_TIMING_V_VSW_SHIFT);
+
+ dispc_reg_out(DISPC_TIMING_H, timing_h);
+ dispc_reg_out(DISPC_TIMING_V, timing_v);
+ dispc_reg_out(DISPC_DIVISOR, divisor);
+ control = dispc_reg_in(DISPC_CONTROL);
+#ifdef CONFIG_MACH_OMAP_3430LABRADOR
+ control |= DISPC_CONTROL_TFTDATALINES_OALSB18B;
+#else
+ control |= DISPC_CONTROL_TFTDATALINES_OALSB16B;
+#endif
+ control |= DISPC_CONTROL_GPOUT1 | DISPC_CONTROL_GPOUT0
+ | DISPC_CONTROL_STNTFT;
+
+ dispc_reg_out(DISPC_CONTROL, control);
+}
+
+/* Set the pixel clock divisor for the LCD */
+void
+omap2_disp_set_pcd(u32 pcd)
+{
+ dispc_reg_out(DISPC_DIVISOR, (1 << DISPC_DIVISOR_LCD_SHIFT) |
+ (pcd << DISPC_DIVISOR_PCD_SHIFT));
+}
+
+/*
+ * Set the DSS Functional clock
+ * The DSS clock should be 4 times the Panel's Pixel clock
+ * For TV the Pixel clock required is 13.5Mhz
+ * For LCD the Pixel clock is 6Mhz
+ */
+void
+omap2_disp_set_dssfclk(void)
+{
+ /* TODO set the LCD pixel clock rate based on the LCD configuration */
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ static int LCD_pixel_clk = 26000000; /* to get more bandwidth*/
+#else
+ static int LCD_pixel_clk = 10000000; /* to get more bandwidth*/
+#endif
+#ifdef CONFIG_VIDEO_OMAP24XX_TVOUT
+ static int TV_pixel_clk = 14000000; /* rounded 13.5 to 14*/
+#endif
+ u32 ask_clkrate=0,sup_clkrate=0,tgt_clkrate=0,i;
+
+ ask_clkrate = LCD_pixel_clk * 4;
+
+#ifdef CONFIG_VIDEO_OMAP24XX_TVOUT
+ if(ask_clkrate < (TV_pixel_clk * 4))
+ ask_clkrate = TV_pixel_clk * 4;
+#endif
+
+ tgt_clkrate = ask_clkrate;
+
+ sup_clkrate = clk_round_rate(dss1f_scale, ask_clkrate);
+ if(is_sil_rev_less_than(OMAP3430_REV_ES2_0)){
+ if(clk_get_rate(dss1f_scale) == 96000000){
+ /*96M already, dont do anything for ES 1.0*/
+ return;
+ }
+ }else
+ {
+ for(i=1;i<=20;i++){
+ sup_clkrate = clk_round_rate(dss1f_scale, ask_clkrate);
+ if(sup_clkrate >= tgt_clkrate) break;
+ ask_clkrate = ask_clkrate + 1000000;
+ }
+ if((clk_get_rate(dss1f_scale) != sup_clkrate) &&
+ (clk_set_rate(dss1f_scale, sup_clkrate)==-EINVAL))
+ printk(KERN_ERR "Unable to set the DSS"
+ " functional clock to %d\n",sup_clkrate);
+ }
+ return;
+}
+
+static void
+omap24xx_ll_config_disp_clocks(int sleep_state)
+{
+#ifdef CONFIG_TRACK_RESOURCES
+ struct device *dev = &display_dev;
+#else
+ struct device *dev = NULL;
+#endif
+ static int start = 1;
+ char *dss1_fck = cpu_is_omap34xx() ? "dss1_alwon_fck" : "dss1_fck";
+
+ //int (*clk_onoff)(struct clk *clk) = NULL;
+ if(start){
+ omap2_disp_set_dssfclk();
+ dss1i = clk_get(dev, "dss_ick");
+ dss1f = clk_get(dev, dss1_fck);
+ if(IS_ERR(dss1i) || IS_ERR(dss1f)) {
+ printk("Could not get DSS clocks\n");
+ return;
+ }
+ start = 0;
+ }
+ if(sleep_state == 1){
+ clk_disable(dss1i);
+ clk_disable(dss1f);
+ }
+ else {
+ if(clk_enable(dss1i) != 0) {
+ printk("Unable to enable DSS ICLK\n");
+ return;
+ }
+ if(clk_enable(dss1f) != 0) {
+ printk("Unable to enable DSS FCLK\n");
+ return;
+ }
+ }
+}
+
+
+
+/* This function must be called by any driver that needs to use the display
+ * controller before calling any routine that accesses the display controller
+ * registers. It increments the count of the number of users of the display
+ * controller, and turns the clocks ON only when required.
+ */
+void
+omap2_disp_get_all_clks(void)
+{
+ u32 idle_dispc;
+#ifdef CONFIG_HW_SUP_TRANS
+ u32 idle_dss;
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ spin_lock(&dss_lock);
+ if (disp_usage == 0) {
+ /* turn on DSS clock */
+ omap24xx_ll_config_disp_clocks(0);
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_disp_set_tvref(TVREF_ON);
+ omap24xx_ll_config_tv_clocks(0);
+#endif
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ /* Set the TV standard first */
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_disp_set_tvstandard(omap2_current_tvstandard);
+#endif
+ /* restore dss context */
+ omap2_disp_restore_ctx(OMAP_DSS_GENERIC);
+ omap2_disp_restore_ctx(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_restore_ctx(OMAP2_GRAPHICS);
+ omap2_disp_restore_ctx(OMAP2_VIDEO1);
+ omap2_disp_restore_ctx(OMAP2_VIDEO2);
+
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+#ifdef CONFIG_HW_SUP_TRANS
+ /* Set smart idle for Display subsystem */
+ idle_dss = dss_reg_in(DSS_SYSCONFIG);
+ idle_dss |= DSS_SYSCONFIG_AUTOIDLE;
+ dss_reg_out(DSS_SYSCONFIG, idle_dss);
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ /* Set smart idle, autoidle for Display controller */
+ idle_dispc = dispc_reg_in(DISPC_SYSCONFIG);
+ idle_dispc &= ~(DISPC_SYSCONFIG_MIDLEMODE |
+ DISPC_SYSCONFIG_SIDLEMODE);
+
+#ifdef CONFIG_HW_SUP_TRANS
+ idle_dispc |= (DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_SIDLE |
+ DISPC_SYSCONFIG_ENABLE_WKUP);
+ idle_dispc |= DISPC_SYSCONFIG_AUTOIDLE;
+#else
+ idle_dispc |= DISPC_SYSCONFIG_MIDLEMODE_NSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_NIDLE;
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ dispc_reg_out(DISPC_SYSCONFIG, idle_dispc);
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ dispc_reg_out(DISPC_CONTROL, dss_ctx.dispc.control);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+ }
+ else {
+ /* enable the TV clocks, since we are not if they are */
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_disp_set_tvref(TVREF_ON);
+ omap24xx_ll_config_tv_clocks(0);
+ {
+ omap2_disp_set_tvstandard(omap2_current_tvstandard);
+ }
+#endif
+ }
+ disp_usage++;
+ spin_unlock(&dss_lock);
+}
+
+/* This function must be called by a driver when it not going to use the
+ * display controller anymore. E.g., when a driver suspends, it must call
+ * omap2_disp_put_dss. When it wakes up, it must call omap2_disp_get_dss
again.
+ * It decrements the count of the number of users of the display
+ * controller, and turns the clocks OFF when not required.
+ */
+void
+omap2_disp_put_all_clks(void)
+{
+#ifndef CONFIG_HW_SUP_TRANS
+ u32 idle_dss;
+#endif /* #ifndef CONFIG_HW_SUP_TRANS */
+
+ spin_lock(&dss_lock);
+ if (disp_usage == 0) {
+ printk(KERN_ERR "trying to put DSS when usage count is zero\n");
+ spin_unlock(&dss_lock);
+ return;
+ }
+
+ disp_usage--;
+
+ if (disp_usage == 0) {
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ /* save dss context */
+ omap2_disp_save_ctx(OMAP_DSS_GENERIC);
+ omap2_disp_save_ctx(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_save_ctx(OMAP2_GRAPHICS);
+ omap2_disp_save_ctx(OMAP2_VIDEO1);
+ omap2_disp_save_ctx(OMAP2_VIDEO2);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+#ifndef CONFIG_HW_SUP_TRANS
+ idle_dss = dispc_reg_in(DISPC_SYSCONFIG);
+ idle_dss &= ~(DISPC_SYSCONFIG_MIDLEMODE | DISPC_SYSCONFIG_SIDLEMODE);
+ idle_dss |= DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_SIDLE;
+ dispc_reg_out(DISPC_SYSCONFIG, idle_dss);
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ omap2_disp_disable(HZ/5);
+ /* turn off TV clocks */
+#ifndef CONFIG_ARCH_OMAP3410
+ omap24xx_ll_config_tv_clocks(1);
+ omap2_disp_set_tvref(TVREF_OFF);
+#endif
+ mdelay(4);
+
+ omap24xx_ll_config_disp_clocks(1);
+ }
+ spin_unlock(&dss_lock);
+}
+///////////////////////////////////////////////////////////////////////////////
+
+/* This function must be called by any driver that needs to use the display
+ * controller before calling any routine that accesses the display controller
+ * registers. It increments the count of the number of users of the display
+ * controller, and turns the clocks ON only when required.
+ */
+void
+omap2_disp_get_dss(void)
+{
+ u32 idle_dispc;
+#ifdef CONFIG_HW_SUP_TRANS
+ u32 idle_dss;
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ spin_lock(&dss_lock);
+ if (disp_usage == 0) {
+ /* turn on DSS clock */
+ omap24xx_ll_config_disp_clocks(0);
+#ifndef CONFIG_ARCH_OMAP3410
+
+ if ((omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO1) == OMAP2_OUTPUT_TV) ||
+ (omap2_disp_get_output_dev(OMAP2_VIDEO2) == OMAP2_OUTPUT_TV))
+ {
+ // printk("get_dss: Enable TV clocks \n");
+ omap2_disp_set_tvref(TVREF_ON);
+ omap24xx_ll_config_tv_clocks(0);
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ omap2_disp_set_tvstandard(omap2_current_tvstandard);
+#endif
+ }
+#endif
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ /* restore dss context */
+ omap2_disp_restore_ctx(OMAP_DSS_GENERIC);
+ omap2_disp_restore_ctx(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_restore_ctx(OMAP2_GRAPHICS);
+ omap2_disp_restore_ctx(OMAP2_VIDEO1);
+ omap2_disp_restore_ctx(OMAP2_VIDEO2);
+
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+#ifdef CONFIG_HW_SUP_TRANS
+ /* Set smart idle for Display subsystem */
+ idle_dss = dss_reg_in(DSS_SYSCONFIG);
+ idle_dss |= DSS_SYSCONFIG_AUTOIDLE;
+ dss_reg_out(DSS_SYSCONFIG, idle_dss);
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ /* Set smart idle, autoidle for Display controller */
+ idle_dispc = dispc_reg_in(DISPC_SYSCONFIG);
+ idle_dispc &= ~(DISPC_SYSCONFIG_MIDLEMODE |
+ DISPC_SYSCONFIG_SIDLEMODE);
+
+#ifdef CONFIG_HW_SUP_TRANS
+ idle_dispc |= (DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_SIDLE |
+ DISPC_SYSCONFIG_ENABLE_WKUP);
+ idle_dispc |= DISPC_SYSCONFIG_AUTOIDLE;
+#else
+ idle_dispc |= DISPC_SYSCONFIG_MIDLEMODE_NSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_NIDLE;
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ dispc_reg_out(DISPC_SYSCONFIG, idle_dispc);
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ dispc_reg_out(DISPC_CONTROL, dss_ctx.dispc.control);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+ }
+ disp_usage++;
+ spin_unlock(&dss_lock);
+}
+
+/* This function must be called by a driver when it not going to use the
+ * display controller anymore. E.g., when a driver suspends, it must call
+ * omap2_disp_put_dss. When it wakes up, it must call omap2_disp_get_dss
again.
+ * It decrements the count of the number of users of the display
+ * controller, and turns the clocks OFF when not required.
+ */
+ void
+omap2_disp_put_dss(void)
+{
+#ifndef CONFIG_HW_SUP_TRANS
+ u32 idle_dss;
+#endif /* #ifndef CONFIG_HW_SUP_TRANS */
+
+ spin_lock(&dss_lock);
+ if (disp_usage == 0) {
+ printk(KERN_ERR "trying to put DSS when usage count is zero\n");
+ spin_unlock(&dss_lock);
+ return;
+ }
+
+ disp_usage--;
+
+ if (disp_usage == 0) {
+#ifdef CONFIG_OMAP34XX_OFFMODE
+ /* save dss context */
+ omap2_disp_save_ctx(OMAP_DSS_GENERIC);
+ omap2_disp_save_ctx(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_save_ctx(OMAP2_GRAPHICS);
+ omap2_disp_save_ctx(OMAP2_VIDEO1);
+ omap2_disp_save_ctx(OMAP2_VIDEO2);
+#endif /* #ifdef CONFIG_OMAP34XX_OFFMODE */
+#ifndef CONFIG_HW_SUP_TRANS
+ idle_dss = dispc_reg_in(DISPC_SYSCONFIG);
+ idle_dss &= ~(DISPC_SYSCONFIG_MIDLEMODE | DISPC_SYSCONFIG_SIDLEMODE);
+ idle_dss |= DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY |
+ DISPC_SYSCONFIG_SIDLEMODE_SIDLE;
+ dispc_reg_out(DISPC_SYSCONFIG, idle_dss);
+#endif /* #ifdef CONFIG_HW_SUP_TRANS */
+
+ omap2_disp_disable(HZ/5);
+#ifndef CONFIG_ARCH_OMAP3410
+ {
+ // printk("put_dss: Disable TV clocks \n");
+ omap24xx_ll_config_tv_clocks(1);
+ omap2_disp_set_tvref(TVREF_OFF);
+ }
+#endif
+ mdelay(4);
+ omap24xx_ll_config_disp_clocks(1);
+ }
+ spin_unlock(&dss_lock);
+}
+
+/* This function must be called by any driver that wishes to use a particular
+ * display pipeline (layer).
+ */
+int
+omap2_disp_request_layer(int ltype)
+{
+ int ret = 0;
+
+ spin_lock(&dss_lock);
+ if (!layer[ltype].in_use) {
+ layer[ltype].in_use = 1;
+ ret = 1;
+ }
+ spin_unlock(&dss_lock);
+
+ return ret;
+}
+
+/* This function must be called by a driver when it is done using a
particular
+ * display pipeline (layer).
+ */
+void
+omap2_disp_release_layer(int ltype)
+{
+ spin_lock(&dss_lock);
+ layer[ltype].in_use = 0;
+ layer[ltype].ctx_valid = 0;
+ spin_unlock(&dss_lock);
+}
+
+/* Used to enable LCDENABLE or DIGITALENABLE of the display controller.
+ */
+void
+omap2_disp_enable_output_dev(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_LCDENABLE,
+ DISPC_CONTROL_LCDENABLE);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_DIGITALENABLE,
+ DISPC_CONTROL_DIGITALENABLE);
+ }
+#endif
+}
+
+/* Used to disable LCDENABLE or DIGITALENABLE of the display controller.
+ */
+void
+omap2_disp_disable_output_dev(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ dispc_reg_merge(DISPC_CONTROL, ~DISPC_CONTROL_LCDENABLE,
+ DISPC_CONTROL_LCDENABLE);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ dispc_reg_merge(DISPC_CONTROL, ~DISPC_CONTROL_DIGITALENABLE,
+ DISPC_CONTROL_DIGITALENABLE);
+ }
+#endif
+}
+
+
+int
+omap2_disp_get_output_dev(int ltype)
+{
+ return layer[ltype].output_dev;
+}
+
+int omap2_disp_get_gfx_fifo_low_threshold(void)
+{
+ return ((dispc_reg_in(DISPC_GFX_FIFO_THRESHOLD) &
+ DISPC_GFX_FIFO_THRESHOLD_LOW) >>
+ DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT);
+}
+
+void omap2_disp_set_gfx_fifo_low_threshold(int thrs)
+{
+ dispc_reg_merge(DISPC_GFX_FIFO_THRESHOLD,
+ thrs << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT,
+ DISPC_GFX_FIFO_THRESHOLD_LOW);
+
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+
+}
+
+int omap2_disp_get_gfx_fifo_high_threshold(void)
+{
+ return ((dispc_reg_in(DISPC_GFX_FIFO_THRESHOLD) &
+ DISPC_GFX_FIFO_THRESHOLD_HIGH) >>
+ DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT);
+}
+
+void omap2_disp_set_gfx_fifo_high_threshold(int thrs)
+{
+ dispc_reg_merge(DISPC_GFX_FIFO_THRESHOLD,
+ thrs << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT,
+ DISPC_GFX_FIFO_THRESHOLD_HIGH);
+
+ dispc_reg_merge(DISPC_CONTROL, DISPC_CONTROL_GOLCD,
+ DISPC_CONTROL_GOLCD);
+
+}
+
+
+/* This is used to dynamically switch the output of a particular layer to
+ * either the LCD or TV.
+ */
+void
+omap2_disp_set_output_dev(int ltype, int output_dev)
+{
+ struct omap2_disp_dma_params *dma_param = 0;
+ int vid_pic_size = 0;
+ int val = (output_dev == OMAP2_OUTPUT_LCD) ? 0 : ~0;
+
+ layer[ltype].output_dev = output_dev;
+
+ switch(ltype) {
+ case OMAP2_GRAPHICS:
+ if (layer[ltype].in_use) {
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ int gfx_size = 0;
+ dma_param = &layer[OMAP2_GRAPHICS].dma[0];
+ gfx_size = (((layer[OMAP2_GRAPHICS].size_x - 1)
+ << DISPC_GFX_SIZE_GFXSIZEX_SHIFT)
+ & DISPC_GFX_SIZE_GFXSIZEX)
+ | (((layer[OMAP2_GRAPHICS].size_y - 1)
+ << DISPC_GFX_SIZE_GFXSIZEY_SHIFT)
+ & DISPC_GFX_SIZE_GFXSIZEY);
+ dispc_reg_out(DISPC_GFX_SIZE, gfx_size);
+
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ int gfx_size = 0;
+ dma_param = &layer[OMAP2_GRAPHICS].dma[1];
+ /* dividing the size_y by two,
+ * because TV operates in interleaved mode
+ */
+ gfx_size = (((layer[OMAP2_GRAPHICS].size_x - 1)
+ << DISPC_GFX_SIZE_GFXSIZEX_SHIFT)
+ & DISPC_GFX_SIZE_GFXSIZEX)
+ | (((layer[OMAP2_GRAPHICS].size_y/2 - 1)
+ << DISPC_GFX_SIZE_GFXSIZEY_SHIFT)
+ & DISPC_GFX_SIZE_GFXSIZEY);
+
+ /* move graphics display position to cover
+ * TV overscan
+ */
+ dispc_reg_out(DISPC_GFX_SIZE, gfx_size);
+ }
+#endif
+
+ dispc_reg_out(DISPC_GFX_BA0, dma_param->ba0);
+ dispc_reg_out(DISPC_GFX_BA1, dma_param->ba1);
+ dispc_reg_out(DISPC_GFX_ROW_INC, dma_param->row_inc);
+ dispc_reg_out(DISPC_GFX_PIXEL_INC, dma_param->pix_inc);
+ }
+
+ dispc_reg_merge(DISPC_GFX_ATTRIBUTES,
+ DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT & val,
+ DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT);
+
+ if (layer[ltype].in_use) omap2_disp_reg_sync(output_dev);
+ break;
+
+ case OMAP2_VIDEO1:
+ if (layer[ltype].in_use){
+ tvlcd_status.output_dev = output_dev;
+ tvlcd_status.ltype = ltype;
+ tvlcd_status.status = TVLCD_STOP;
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ dma_param = &layer[OMAP2_VIDEO1].dma[0];
+ vid_pic_size =
+ (((layer[OMAP2_VIDEO1].size_x -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((layer[OMAP2_VIDEO1].size_y -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(0), vid_pic_size);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ dma_param = &layer[OMAP2_VIDEO1].dma[1];
+ vid_pic_size =
+ (((layer[OMAP2_VIDEO1].size_x -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((layer[OMAP2_VIDEO1].size_y / 2 -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(0), vid_pic_size);
+ }
+#endif
+
+ dispc_reg_out(DISPC_VID_BA0(0), dma_param->ba0);
+ dispc_reg_out(DISPC_VID_BA1(0), dma_param->ba1);
+ dispc_reg_out(DISPC_VID_ROW_INC(0), dma_param->row_inc);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(0), dma_param->pix_inc);
+
+ dispc_reg_merge(DISPC_VID_ATTRIBUTES(0),
+ DISPC_VID_ATTRIBUTES_VIDCHANNELOUT & val,
+ DISPC_VID_ATTRIBUTES_VIDCHANNELOUT);
+ break;
+ }
+
+ case OMAP2_VIDEO2:
+ if (layer[ltype].in_use){
+
+ tvlcd_status.output_dev = output_dev;
+ tvlcd_status.ltype = ltype;
+ tvlcd_status.status = TVLCD_STOP;
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ dma_param = &layer[OMAP2_VIDEO2].dma[0];
+ vid_pic_size =
+ (((layer[OMAP2_VIDEO2].size_x -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((layer[OMAP2_VIDEO2].size_y -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(1), vid_pic_size);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ dma_param = &layer[OMAP2_VIDEO2].dma[1];
+ vid_pic_size =
+ (((layer[OMAP2_VIDEO2].size_x -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEX) |
+ (((layer[OMAP2_VIDEO2].size_y / 2 -
+ 1) << DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT)
+ & DISPC_VID_PICTURE_SIZE_VIDORGSIZEY);
+ dispc_reg_out(DISPC_VID_PICTURE_SIZE(1), vid_pic_size);
+ }
+#endif
+
+ dispc_reg_out(DISPC_VID_BA0(1), dma_param->ba0);
+ dispc_reg_out(DISPC_VID_BA1(1), dma_param->ba1);
+ dispc_reg_out(DISPC_VID_ROW_INC(1), dma_param->row_inc);
+ dispc_reg_out(DISPC_VID_PIXEL_INC(1), dma_param->pix_inc);
+
+ dispc_reg_merge(DISPC_VID_ATTRIBUTES(1),
+ DISPC_VID_ATTRIBUTES_VIDCHANNELOUT & val,
+ DISPC_VID_ATTRIBUTES_VIDCHANNELOUT);
+ break;
+ }
+ }
+}
+
+/* Used to save the DMA parameter settings for a particular layer to be
+ * displayed on a particular output device. These values help the
+ * omap2_disp_set_output_dev() function to dynamically switch the output of a
+ * layer to any output device.
+ */
+void
+omap2_disp_set_dma_params(int ltype, int output_dev,
+ u32 ba0, u32 ba1, u32 row_inc, u32 pix_inc)
+{
+ struct omap2_disp_dma_params *dma;
+
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ dma = &layer[ltype].dma[0];
+ else
+ dma = &layer[ltype].dma[1];
+
+ dma->ba0 = ba0;
+ dma->ba1 = ba1;
+ dma->row_inc = row_inc;
+ dma->pix_inc = pix_inc;
+}
+
+void
+omap2_disp_start_gfxlayer(void)
+{
+ omap2_disp_set_output_dev(OMAP2_GRAPHICS,
+ layer[OMAP2_GRAPHICS].output_dev);
+ omap2_disp_enable_layer(OMAP2_GRAPHICS);
+}
+
+/*---------------------------------------------------------------------------*/
+
+/* Sets the background color */
+void
+omap2_disp_set_bg_color(int output_dev, int color)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ dispc_reg_out(DISPC_DEFAULT_COLOR0, color);
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV)
+ dispc_reg_out(DISPC_DEFAULT_COLOR1, color);
+#endif
+
+ omap2_disp_reg_sync(output_dev);
+}
+
+/* Returns the current background color */
+void
+omap2_disp_get_bg_color(int output_dev, int *color)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ *color = dispc_reg_in(DISPC_DEFAULT_COLOR0);
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV)
+ *color = dispc_reg_in(DISPC_DEFAULT_COLOR1);
+#endif
+}
+
+/* Enable/Disable the Dithering block */
+void
+omap2_disp_set_dithering(int dither_state)
+{
+ omap2_disp_get_dss();
+ switch(dither_state){
+ case DITHERING_ON:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL) | DISPC_CONTROL_TFTDITHERENABLE));
+ break;
+ case DITHERING_OFF:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL) & ~DISPC_CONTROL_TFTDITHERENABLE));
+ break;
+ }
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+ // omap2_disp_reg_sync(OMAP2_OUTPUT_TV);
+ omap2_disp_put_dss();
+}
+
+/* Get the Dithering state */
+int
+omap2_disp_get_dithering(void)
+{
+ omap2_disp_get_dss();
+ if(dispc_reg_in(DISPC_CONTROL) & 0x00000080){
+ return(DITHERING_ON);
+ }
+ else{
+ return(DITHERING_OFF);
+ }
+ omap2_disp_put_dss();
+}
+
+/* Get the number of data lines connected to LCD panel*/
+int
+omap2_disp_get_lcddatalines(void)
+{
+ u32 tft_data_lines=0;
+
+ omap2_disp_get_dss();
+ tft_data_lines = dispc_reg_in(DISPC_CONTROL)
+ & (DISPC_CONTROL_TFTDATALINES);
+
+ switch(tft_data_lines){
+ case DISPC_CONTROL_TFTDATALINES_OALSB12B:
+ return(LCD_DATA_LINE_12BIT);
+ case DISPC_CONTROL_TFTDATALINES_OALSB16B:
+ return(LCD_DATA_LINE_16BIT);
+ case DISPC_CONTROL_TFTDATALINES_OALSB18B:
+ return(LCD_DATA_LINE_18BIT);
+ case DISPC_CONTROL_TFTDATALINES_OALSB24B:
+ return(LCD_DATA_LINE_24BIT);
+ }
+ omap2_disp_put_dss();
+ return(LCD_DATA_LINE_16BIT);
+}
+
+/* Set number of data lines to be connected to LCD panel*/
+void
+omap2_disp_set_lcddatalines(int no_of_lines)
+{
+ omap2_disp_get_dss();
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL) & ~DISPC_CONTROL_TFTDATALINES));
+
+ switch(no_of_lines){
+ case LCD_DATA_LINE_12BIT:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL)
+ | DISPC_CONTROL_TFTDATALINES_OALSB12B));
+ break;
+ case LCD_DATA_LINE_16BIT:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL)
+ | DISPC_CONTROL_TFTDATALINES_OALSB16B));
+ break;
+ case LCD_DATA_LINE_18BIT:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL)
+ | DISPC_CONTROL_TFTDATALINES_OALSB18B));
+ break;
+ case LCD_DATA_LINE_24BIT:
+ dispc_reg_out(DISPC_CONTROL,
+ (dispc_reg_in(DISPC_CONTROL)
+ | DISPC_CONTROL_TFTDATALINES_OALSB24B));
+ break;
+ }
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+ omap2_disp_put_dss();
+}
+
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
&& !defined(CONFIG_ARCH_OMAP3410)
+/* Turn on/off the TV reference voltage from OMAP */
+void
+omap2_disp_set_tvref(int tvref_state)
+{
+ switch(tvref_state){
+ case TVREF_ON:
+ dss_reg_out(DSS_CONTROL,(dss_reg_in(DSS_CONTROL)
+ | DSS_CONTROL_TV_REF));
+ break;
+ case TVREF_OFF:
+ dss_reg_out(DSS_CONTROL, (dss_reg_in(DSS_CONTROL) &
+ ~(DSS_CONTROL_TV_REF)));
+ break;
+ }
+}
+#endif
+
+/* Sets the SMS settings for rotation using the VRFB.
+ */
+int
+omap2_disp_set_vrfb(int context, u32 phy_addr,
+ u32 width, u32 height, u32 bytes_per_pixel)
+{
+ int page_width_exp, page_height_exp, pixel_size_exp;
+
+ if (bytes_per_pixel > 4)
+ return -EINVAL;
+
+ page_width_exp = PAGE_WIDTH_EXP;
+ page_height_exp = PAGE_HEIGHT_EXP;
+ pixel_size_exp = bytes_per_pixel >> 1;
+
+ width = ((1<<page_width_exp) *
+ (pages_per_side(width * bytes_per_pixel, page_width_exp))
+ ) >> pixel_size_exp; // in pixels
+
+ height = (1<<page_height_exp) *
+ (pages_per_side(height, page_height_exp));
+
+ SMS_ROT0_PHYSICAL_BA(context) = phy_addr;
+ SMS_ROT0_SIZE(context) = 0;
+ SMS_ROT0_SIZE(context) |= (width << SMS_IMAGEWIDTH_OFFSET)
+ | (height << SMS_IMAGEHEIGHT_OFFSET);
+ SMS_ROT_CONTROL(context) = 0;
+
+ SMS_ROT_CONTROL(context) |= pixel_size_exp << SMS_PS_OFFSET
+ | (page_width_exp - pixel_size_exp) << SMS_PW_OFFSET
+ | page_height_exp << SMS_PH_OFFSET;
+
+ return 0;
+}
+
+#ifndef CONFIG_ARCH_OMAP3410
+/* Sets VENC registers for TV operation.
+*/
+static void
+config_venc(struct tv_standard_config *tvstd)
+{
+ venc_reg_out(VENC_F_CONTROL, F_CONTROL_GEN);
+ venc_reg_out(VENC_SYNC_CONTROL,SYNC_CONTROL_GEN);
+ venc_reg_out(VENC_LLEN, tvstd->venc_llen);
+ venc_reg_out(VENC_FLENS, tvstd->venc_flens);
+ venc_reg_out(VENC_HFLTR_CTRL, tvstd->venc_hfltr_ctrl);
+ venc_reg_out(VENC_CC_CARR_WSS_CARR, tvstd->venc_cc_carr_wss_carr);
+ venc_reg_out(VENC_C_PHASE, tvstd->venc_c_phase);
+ venc_reg_out(VENC_GAIN_U, tvstd->venc_gain_u);
+ venc_reg_out(VENC_GAIN_V, tvstd->venc_gain_v);
+ venc_reg_out(VENC_GAIN_Y, tvstd->venc_gain_y);
+ venc_reg_out(VENC_BLACK_LEVEL, tvstd->venc_black_level);
+ venc_reg_out(VENC_BLANK_LEVEL, tvstd->venc_blank_level);
+ venc_reg_out(VENC_X_COLOR, tvstd->venc_x_color);
+ venc_reg_out(VENC_M_CONTROL, tvstd->venc_m_control);
+ venc_reg_out(VENC_BSTAMP_WSS_DATA, tvstd->venc_bstamp_wss_data);
+ venc_reg_out(VENC_S_CARR, tvstd->venc_s_carr);
+ venc_reg_out(VENC_LINE21, tvstd->venc_line21);
+ venc_reg_out(VENC_LN_SEL, tvstd->venc_ln_sel);
+ venc_reg_out(VENC_L21_WC_CTL, tvstd->venc_l21_wc_ctl);
+ venc_reg_out(VENC_HTRIGGER_VTRIGGER, tvstd->venc_htrigger_vtrigger);
+ venc_reg_out(VENC_SAVID_EAVID, tvstd->venc_savid_eavid);
+ venc_reg_out(VENC_FLEN_FAL, tvstd->venc_flen_fal);
+ venc_reg_out(VENC_LAL_PHASE_RESET, tvstd->venc_lal_phase_reset);
+ venc_reg_out(VENC_HS_INT_START_STOP_X,
+ tvstd->venc_hs_int_start_stop_x);
+ venc_reg_out(VENC_HS_EXT_START_STOP_X,
+ tvstd->venc_hs_ext_start_stop_x);
+ venc_reg_out(VENC_VS_INT_START_X, tvstd->venc_vs_int_start_x);
+ venc_reg_out(VENC_VS_INT_STOP_X_VS_INT_START_Y,
+ tvstd-> venc_vs_int_stop_x_vs_int_start_y);
+ venc_reg_out(VENC_VS_INT_STOP_Y_VS_EXT_START_X,
+ tvstd->venc_vs_int_stop_y_vs_ext_start_x);
+ venc_reg_out(VENC_VS_EXT_STOP_X_VS_EXT_START_Y,
+ tvstd->venc_vs_ext_stop_x_vs_ext_start_y);
+ venc_reg_out(VENC_VS_EXT_STOP_Y, tvstd->venc_vs_ext_stop_y);
+ venc_reg_out(VENC_AVID_START_STOP_X, tvstd->venc_avid_start_stop_x);
+ venc_reg_out(VENC_AVID_START_STOP_Y, tvstd->venc_avid_start_stop_y);
+ venc_reg_out(VENC_FID_INT_START_X_FID_INT_START_Y,
+ tvstd-> venc_fid_int_start_x_fid_int_start_y);
+ venc_reg_out(VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,
+ tvstd->venc_fid_int_offset_y_fid_ext_start_x);
+ venc_reg_out(VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,
+ tvstd->venc_fid_ext_start_y_fid_ext_offset_y);
+ venc_reg_out(VENC_TVDETGP_INT_START_STOP_X,
+ tvstd->venc_tvdetgp_int_start_stop_x);
+ venc_reg_out(VENC_TVDETGP_INT_START_STOP_Y,
+ tvstd->venc_tvdetgp_int_start_stop_y);
+ venc_reg_out(VENC_GEN_CTRL, tvstd->venc_gen_ctrl);
+ venc_reg_out(VENC_DAC_TST, tvstd->venc_dac_tst);
+ venc_reg_out(VENC_DAC, venc_reg_in(VENC_DAC));
+}
+
+
+int
+omap2_disp_get_tvstandard(void)
+{
+ return(omap2_current_tvstandard);
+}
+
+#else
+int
+omap2_disp_get_tvstandard(void){ return 0; }
+#endif
+
+void
+omap2_disp_get_tvlcd(struct tvlcd_status_t *status)
+{
+ status->status = tvlcd_status.status;
+ status->output_dev = tvlcd_status.output_dev;
+ status->ltype = tvlcd_status.ltype;
+}
+
+void
+omap2_disp_set_tvlcd(int status)
+{
+ tvlcd_status.status = status;
+}
+
+#ifndef CONFIG_ARCH_OMAP3410
+void
+omap2_disp_set_tvstandard(int tvstandard)
+{
+ omap2_current_tvstandard = tvstandard;
+ switch (tvstandard) {
+ case PAL_BDGHI:
+ config_venc(&pal_bdghi_cfg);
+ break;
+ case PAL_NC:
+ config_venc(&pal_nc_cfg);
+ break;
+ case PAL_N:
+ config_venc(&pal_n_cfg);
+ break;
+ case PAL_M:
+ config_venc(&pal_m_cfg);
+ break;
+ case PAL_60:
+ config_venc(&pal_60_cfg);
+ omap2_disp_set_panel_size(OMAP2_OUTPUT_TV, 720, 574);
+ break;
+ case NTSC_M:
+ config_venc(&ntsc_m_cfg);
+ break;
+ case NTSC_J:
+ config_venc(&ntsc_j_cfg);
+ break;
+ case NTSC_443:
+ config_venc(&ntsc_443_cfg);
+ omap2_disp_set_panel_size(OMAP2_OUTPUT_TV, 720, 480);
+ break;
+ }
+
+ if (in_atomic())
+ mdelay(50);
+ else
+ msleep(50);
+
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+}
+
+
+
+#else
+void
+omap2_disp_set_tvstandard(int tvstandard) {
+ return ;
+}
+#endif
+
+
+/* Sets the transparency color key type and value.
+*/
+void
+omap2_disp_set_colorkey(int output_dev, int key_type, int key_val)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ if (key_type == OMAP2_VIDEO_SOURCE)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_TCKLCDSELECTION,
+ DISPC_CONFIG_TCKLCDSELECTION);
+ else
+ dispc_reg_merge(DISPC_CONFIG, 0,
+ DISPC_CONFIG_TCKLCDSELECTION);
+ dispc_reg_out(DISPC_TRANS_COLOR0, key_val);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ if (key_type == OMAP2_VIDEO_SOURCE)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_TCKDIGSELECTION,
+ DISPC_CONFIG_TCKDIGSELECTION);
+ else
+ dispc_reg_merge(DISPC_CONFIG, 0,
+ DISPC_CONFIG_TCKDIGSELECTION);
+ dispc_reg_out(DISPC_TRANS_COLOR1, key_val);
+ }
+#endif
+
+ omap2_disp_reg_sync(output_dev);
+}
+
+/* Returns the current transparency color key type and value.
+*/
+void
+omap2_disp_get_colorkey(int output_dev, int *key_type, int *key_val)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ if (dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKLCDSELECTION)
+ *key_type = OMAP2_VIDEO_SOURCE;
+ else
+ *key_type = OMAP2_GFX_DESTINATION;
+ *key_val = dispc_reg_in(DISPC_TRANS_COLOR0);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ if (dispc_reg_in(DISPC_CONFIG) & DISPC_CONFIG_TCKDIGSELECTION)
+ *key_type = OMAP2_VIDEO_SOURCE;
+ else
+ *key_type = OMAP2_GFX_DESTINATION;
+ *key_val = dispc_reg_in(DISPC_TRANS_COLOR1);
+ }
+#endif
+}
+
+void
+omap2_disp_enable_colorkey(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_TCKLCDENABLE,
+ DISPC_CONFIG_TCKLCDENABLE);
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_TCKDIGENABLE,
+ DISPC_CONFIG_TCKDIGENABLE);
+#endif
+
+ omap2_disp_reg_sync(output_dev);
+}
+
+void
+omap2_disp_disable_colorkey(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD)
+ dispc_reg_merge(DISPC_CONFIG, ~DISPC_CONFIG_TCKLCDENABLE,
+ DISPC_CONFIG_TCKLCDENABLE);
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV)
+ dispc_reg_merge(DISPC_CONFIG, ~DISPC_CONFIG_TCKDIGENABLE,
+ DISPC_CONFIG_TCKDIGENABLE);
+#endif
+
+ omap2_disp_reg_sync(output_dev);
+}
+#ifdef CONFIG_ARCH_OMAP34XX
+void
+omap2_disp_set_alphablend(int output_dev,int value)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ if (value)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_LCDALPHAENABLE,
+ DISPC_CONFIG_LCDALPHAENABLE);
+ else
+ dispc_reg_merge(DISPC_CONFIG, ~DISPC_CONFIG_LCDALPHAENABLE,
+ DISPC_CONFIG_LCDALPHAENABLE);
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ if (value)
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_TVALPHAENABLE,
+ DISPC_CONFIG_TVALPHAENABLE);
+ else
+ dispc_reg_merge(DISPC_CONFIG, ~DISPC_CONFIG_TVALPHAENABLE,
+ DISPC_CONFIG_TVALPHAENABLE);
+ }
+#endif
+ omap2_disp_reg_sync(output_dev);
+}
+
+void
+omap2_disp_set_global_alphablend_value(int ltype,int value)
+{
+unsigned int alpha_value;
+
+ if (ltype == OMAP2_GRAPHICS) {
+ alpha_value = dispc_reg_in(DISPC_GLOBAL_ALPHA);
+ alpha_value &= (~DISPC_GLOBAL_ALPHA_GFX_GALPHA);
+ alpha_value |= (value << DISPC_GLOBAL_ALPHA_GFX_GALPHA_SHIFT);
+ dispc_reg_out(DISPC_GLOBAL_ALPHA,alpha_value);
+
+ }
+ else if (ltype == OMAP2_VIDEO2) {
+ alpha_value = dispc_reg_in(DISPC_GLOBAL_ALPHA);
+ alpha_value &= (~DISPC_GLOBAL_ALPHA_VID2_GALPHA);
+ alpha_value |= (value << DISPC_GLOBAL_ALPHA_VID2_GALPHA_SHIFT);
+ dispc_reg_out(DISPC_GLOBAL_ALPHA,alpha_value);
+
+ }
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_disp_reg_sync(OMAP2_OUTPUT_TV);
+#endif
+}
+
+unsigned char
+omap2_disp_get_global_alphablend_value(int ltype)
+{
+unsigned int alpha_value = 0;
+
+ if (ltype == OMAP2_GRAPHICS) {
+ alpha_value = dispc_reg_in(DISPC_GLOBAL_ALPHA);
+ alpha_value &= (DISPC_GLOBAL_ALPHA_GFX_GALPHA);
+ alpha_value = alpha_value >> DISPC_GLOBAL_ALPHA_GFX_GALPHA_SHIFT;
+ }
+ else if (ltype == OMAP2_VIDEO2) {
+ alpha_value = dispc_reg_in(DISPC_GLOBAL_ALPHA);
+ alpha_value &= (DISPC_GLOBAL_ALPHA_VID2_GALPHA);
+ alpha_value = alpha_value >> DISPC_GLOBAL_ALPHA_VID2_GALPHA_SHIFT;
+ }
+ return (unsigned char) alpha_value;
+}
+
+int
+omap2_disp_get_alphablend(int output_dev)
+{
+
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ if(dispc_reg_in(DISPC_CONFIG) & 0x00040000)
+ return 1;
+ else
+ return 0;
+ }
+#ifndef CONFIG_ARCH_OMAP3410
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ if(dispc_reg_in(DISPC_CONFIG) & 0x00080000)
+ return 1;
+ else
+ return 0;
+ }
+#endif
+ return 0;
+}
+#endif
+
+int
+omap2_disp_reg_sync_bit(int output_dev)
+{
+ u32 control = dispc_reg_in (DISPC_CONTROL);
+
+ if(output_dev == OMAP2_OUTPUT_LCD){
+ return (control & DISPC_CONTROL_GOLCD) >> 5;
+ }
+ else {
+ return (control & DISPC_CONTROL_GODIGITAL) >> 6;
+ }
+}
+
+
+
+/*
+ * This function is required for 2420 errata 1.97
+ */
+
+#ifndef CONFIG_ARCH_OMAP3410
+static void
+omap2_reset_venc(void)
+{
+ u32 i=0;
+ struct clk *dss_tv_fck;
+ #ifdef CONFIG_MACH_OMAP_2430SDP
+ dss_tv_fck = clk_get(NULL,"dss_54m_fck");
+ #endif
+ #if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR) || defined(CONFIG_MACH_OMAP3_BEAGLE)
+ #ifdef CONFIG_TRACK_RESOURCES
+ dss_tv_fck = clk_get(&display_dev,"dss_tv_fck");
+ #else
+ dss_tv_fck = clk_get(NULL,"dss_tv_fck");
+ #endif
+ #endif
+
+ if(IS_ERR(dss_tv_fck)){
+ printk("\n UNABLE to get dss TV fclk \n");
+ return;
+ }
+
+ /* Enable VENC clock */
+ if(clk_enable(dss_tv_fck) != 0) {
+ printk("\n UNABLE to enable dss TV fclk \n");
+ return;
+ }
+
+ /*
+ * Write 1 to the 8th bit of the F_Control register to reset the VENC
+ */
+ venc_reg_merge(VENC_F_CONTROL, VENC_FCONTROL_RESET, VENC_FCONTROL_RESET);
+
+ /* wait for reset to complete */
+ while ((venc_reg_in(VENC_F_CONTROL) & VENC_FCONTROL_RESET) == 0x00000100)
+ {
+ udelay(10);
+ if(i++ >10) break;
+ }
+
+ if (venc_reg_in(VENC_F_CONTROL) & VENC_FCONTROL_RESET)
+ {
+ printk(KERN_WARNING
+ "omap2_disp: timeout waiting for venc reset\n");
+
+ /* remove the reset */
+ venc_reg_merge(VENC_F_CONTROL,(0<<8),VENC_FCONTROL_RESET);
+ }
+
+ /* disable the VENC clock */
+ clk_disable(dss_tv_fck);
+}
+#endif
+
+/*
+ * Enables an IRQ in DSPC_IRQENABLE.
+ */
+int
+omap2_disp_irqenable(omap2_disp_isr_t isr,unsigned int mask)
+{
+ int i;
+ unsigned long flags;
+
+ if (omap2_disp_irq == 0 || mask == 0)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dss_lock, flags);
+ for (i = 0; i < MAX_ISR_NR; i++) {
+ if (registered_isr[i].isr == isr) {
+ registered_isr[i].mask |= mask;
+ dispc_reg_out(DISPC_IRQENABLE,dispc_reg_in(DISPC_IRQENABLE) | mask);
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return 0;
+ }
+ }
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return -EBUSY;
+}
+
+/*
+ * Disables an IRQ in DISPC_IRQENABLE,
+ * The IRQ will be active if any other ISR is still using the same.
+ * mask : should contain '0' for irq to be disable and rest should be '1'.
+ */
+int
+omap2_disp_irqdisable(omap2_disp_isr_t isr,unsigned int mask)
+{
+ int i;
+ unsigned long flags;
+ unsigned int new_mask = 0;
+
+ if (omap2_disp_irq == 0)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dss_lock, flags);
+ for (i = 0; i < MAX_ISR_NR; i++)
+ if (registered_isr[i].isr == isr) break;
+
+ if(i == MAX_ISR_NR){
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return -EINVAL;
+ }
+
+ registered_isr[i].mask &= mask;
+
+ /* disable an IRQ if every one wishes to do so */
+ for (i = 0; i < MAX_ISR_NR; i++){
+ new_mask |= registered_isr[i].mask;
+ }
+
+ dispc_reg_out(DISPC_IRQENABLE, new_mask);
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return -EBUSY;
+}
+
+/* Display controller interrupts are handled first by this display library.
+ * Drivers that need to use certain interrupts should register their ISRs and
+ * interrupt enable mask with the display library.
+ */
+int
+omap2_disp_register_isr(omap2_disp_isr_t isr, void *arg, unsigned int mask)
+{
+ int i;
+ unsigned long flags;
+
+ if (omap2_disp_irq == 0 || isr == 0 || arg == 0)
+ return -EINVAL;
+
+ /* Clear all the interrupt, so that you dont get an immediate interrupt*/
+ dispc_reg_out(DISPC_IRQSTATUS, 0xFFFFFFFF);
+ spin_lock_irqsave(&dss_lock, flags);
+ for (i = 0; i < MAX_ISR_NR; i++) {
+ if (registered_isr[i].isr == NULL) {
+ registered_isr[i].isr = isr;
+ registered_isr[i].arg = arg;
+ registered_isr[i].mask = mask;
+
+ /* Clear previous interrupts if any */
+ dispc_reg_out(DISPC_IRQSTATUS, mask);
+ dispc_reg_out(DISPC_IRQENABLE,dispc_reg_in(DISPC_IRQENABLE) | mask);
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return 0;
+ }
+ }
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return -EBUSY;
+}
+
+int
+omap2_disp_unregister_isr(omap2_disp_isr_t isr)
+{
+ int i,j;
+ unsigned long flags;
+ unsigned int new_mask =0;
+
+ if (omap2_disp_irq == 0)
+ return -EINVAL;
+
+ spin_lock_irqsave(&dss_lock, flags);
+ for (i = 0; i < MAX_ISR_NR; i++) {
+ if (registered_isr[i].isr == isr) {
+ registered_isr[i].isr = NULL;
+ registered_isr[i].arg = NULL;
+ registered_isr[i].mask = 0;
+
+ /* The interrupt may no longer be valid, re-set the IRQENABLE */
+ for (j = 0; j < MAX_ISR_NR; j++){
+ new_mask |= registered_isr[j].mask;
+ }
+ dispc_reg_out(DISPC_IRQENABLE, new_mask);
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return 0;
+ }
+ }
+ spin_unlock_irqrestore(&dss_lock, flags);
+ return -EINVAL;
+}
+
+/* DSS Interrupt master service routine. */
+static irqreturn_t
+omap2_disp_master_isr(int irq, void *arg, struct pt_regs *regs)
+{
+ unsigned long dispc_irqstatus = dispc_reg_in(DISPC_IRQSTATUS);
+ int i;
+
+ for (i = 0; i < MAX_ISR_NR; i++) {
+ if (registered_isr[i].isr == NULL)
+ continue;
+ if (registered_isr[i].mask & dispc_irqstatus)
+ registered_isr[i].isr(registered_isr[i].arg, regs);
+ }
+
+ /* ack the interrupt */
+ dispc_reg_out(DISPC_IRQSTATUS, dispc_irqstatus);
+
+ return IRQ_HANDLED;
+}
+
+int __init
+omap2_disp_init(void)
+{
+ int rev,i;
+ u32 dss_control;
+ char *dss1_fck = cpu_is_omap34xx() ? "dss1_alwon_fck" : "dss1_fck";
+
+ spin_lock_init(&dss_lock);
+
+ /* Required for scale call */
+#ifdef CONFIG_TRACK_RESOURCES
+ dss1f_scale = clk_get(&display_dev, dss1_fck);
+#else
+ dss1f_scale = clk_get(NULL, dss1_fck);
+#endif
+ if(IS_ERR(dss1f_scale)) {
+ printk("Could not get DSS1 FCLK\n");
+ return PTR_ERR(dss1f_scale);
+ }
+
+ omap2_disp_get_all_clks();
+
+ /* disable the display controller */
+ omap2_disp_disable(HZ/5);
+
+ rev = dss_reg_in(DSS_REVISION);
+ printk(KERN_INFO "OMAP Display hardware version %d.%d\n",
+ (rev & DISPC_REVISION_MAJOR) >> DISPC_REVISION_MAJOR_SHIFT,
+ (rev & DISPC_REVISION_MINOR) >> DISPC_REVISION_MINOR_SHIFT);
+
+ /* Disable RFBI mode, which is not currently supported. */
+ dispc_reg_merge(DISPC_CONTROL, 0, DISPC_CONTROL_RFBIMODE);
+
+ /* For 2420 VENC errata 1.97 */
+ /* For 2430 VENC errata 1.20 */
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_reset_venc();
+#endif
+ /* enable DAC_DEMEN and VENC_4X_CLOCK in DSS for TV operation */
+ dss_control = dss_reg_in(DSS_CONTROL);
+
+ /* Should be replaced by FPGA register read ADD A 2420 ifdef here*/
+
+#ifdef CONFIG_ARCH_OMAP2420
+ dss_control |= (DSS_CONTROL_DAC_DEMEN |
+ DSS_CONTROL_VENC_CLOCK_4X_ENABLE);
+#endif
+
+#ifdef CONFIG_MACH_OMAP_2430SDP
+ #ifdef CONFIG_TWL4030_CORE_T2
+ dss_control |= (DSS_CONTROL_TV_REF | DSS_CONTROL_DAC_DEMEN |
+ DSS_CONTROL_VENC_CLOCK_4X_ENABLE);
+ #endif
+
+ #ifdef CONFIG_TWL4030_CORE_M1
+ dss_control |= (DSS_CONTROL_DAC_DEMEN |
+ DSS_CONTROL_VENC_CLOCK_4X_ENABLE);
+ #endif
+#endif
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) || \
+ defined(CONFIG_MACH_OMAP_3430LABRADOR) || \
+ defined(CONFIG_MACH_OMAP3_BEAGLE)
+ /* enabling S-video connector for 3430 SDP */
+#ifndef CONFIG_ARCH_OMAP3410
+ dss_control |= (DSS_CONTROL_DAC_DEMEN | DSS_CONTROL_TV_REF |
+ DSS_CONTROL_VENC_CLOCK_4X_ENABLE | DSS_CONTROL_VENC_OUT);
+#else
+ dss_control |= (DSS_CONTROL_DAC_DEMEN |
+ DSS_CONTROL_VENC_CLOCK_4X_ENABLE | DSS_CONTROL_VENC_OUT);
+#endif
+#endif
+
+ dss_control &= ~DSS_CONTROL_VENC_CLOCK_MODE;
+ dss_reg_out(DSS_CONTROL, dss_control);
+
+ /* By default, all layers go to LCD */
+ layer[OMAP2_GRAPHICS].output_dev = OMAP2_OUTPUT_LCD;
+ layer[OMAP2_VIDEO1].output_dev = OMAP2_OUTPUT_LCD;
+ layer[OMAP2_VIDEO2].output_dev = OMAP2_OUTPUT_LCD;
+
+ /*
+ * Set the default color conversion parameters for Video pipelines
+ * by default the color space is set to JPEG
+ */
+
+ update_colorconv_mtx(0,cc_bt601_full);
+ set_colorconv(0,V4L2_COLORSPACE_JPEG);
+
+ update_colorconv_mtx(1,cc_bt601_full);
+ set_colorconv(1,V4L2_COLORSPACE_JPEG);
+
+ /* Set the default background color to be black*/
+ omap2_disp_set_bg_color(OMAP2_OUTPUT_LCD, 0x000000);
+#ifndef CONFIG_ARCH_OMAP3410
+ omap2_disp_set_bg_color(OMAP2_OUTPUT_TV, 0x000000);
+#endif
+
+ if (request_irq(INT_24XX_DSS_IRQ, (void *)omap2_disp_master_isr,
IRQF_SHARED,
+ "OMAP2 Display", registered_isr))
+ {
+ printk(KERN_WARNING "omap2_disp: request_irq failed\n");
+ omap2_disp_irq = 0;
+ }
+ else {
+ omap2_disp_irq = 1;
+ for(i=0;i<MAX_ISR_NR;i++){
+ registered_isr[i].isr = NULL;
+ registered_isr[i].mask = 0;
+ }
+ /* Clear all the pending interrupts, if any */
+ dispc_reg_out(DISPC_IRQSTATUS, 0xFFFFFFFF);
+ omap2_disp_register_isr(omap2_synclost_isr, layer,
+ DISPC_IRQSTATUS_SYNCLOST);
+ }
+
+ omap2_disp_register_isr(omap2_synclost_isr, layer,
+ DISPC_IRQSTATUS_SYNCLOST);
+ omap2_disp_put_all_clks();
+
+ return 0;
+
+}
+
+#ifdef CONFIG_ARCH_OMAP34XX
+
+/*
+ * optimal precalculated frequency for DSS1_ALWON_CLK. The freq is optimal
+ * in the sense that there is a divider that gives pixel clock rate closest
to
+ * the lowest possible pixel clock rate for a given panel
+ */
+#ifdef CONFIG_FB_OMAP_LCD_VGA
+#define LPR_DSS1_ALWON_FCLK_OPT_FREQ 96000000
+#define LPR_DSS_LOGIC_DIV 2
+#define LPR_HBP 79
+#define LPR_HFP 59
+#define LPR_HSW 2
+#define LPR_VBP 0
+#define LPR_VFP 0
+#define LPR_VSW 1
+#define LPR_GFX_FIFO_LOW_THRES 0x99C
+#define LPR_GFX_FIFO_HIGH_THRES 0xB9C
+#else
+/* These values are validated only on 3430 ES2 */
+/* Might not work on 3430 ES1 */
+#define LPR_DSS1_ALWON_FCLK_OPT_FREQ 108000000
+#define LPR_DSS_LOGIC_DIV 9
+#define LPR_HBP 31
+#define LPR_HFP 37
+#define LPR_HSW 3
+#define LPR_VBP 8
+#define LPR_VFP 2
+#define LPR_VSW 1
+#define LPR_GFX_FIFO_LOW_THRES 0x7F8
+#define LPR_GFX_FIFO_HIGH_THRES 0xB9C
+#endif /* CONFIG_FB_OMAP_LCD_VGA */
+
+
+#define LPR_DEFAULT_FPS 60
+
+#ifdef CONFIG_MACH_OMAP_3430SDP
+
+#endif /* CONFIG_MACH_OMAP_3430SDP */
+
+struct dss_run_mode {
+ int rate;
+ int divisors;
+ int timing_h;
+ int timing_v;
+};
+
+static struct dss_run_mode rmode;
+int lpr_enabled;
+
+/*
+ * if set, the lowest dss logic frequency to achieve given(lowest) pixel
clock
+ * frequency is set. Otherwise 'lpr_lowest_dss_logic_freq' value is used.
+ * The flag is set by default and can be reset via sysfs interface
+ */
+int lpr_lowest_dss_logic_freq_enabled = 1;
+
+/*
+ * dss logic freq. initially initialized to be equal to DSS1_ALWON_FCLK.
+ * the value may be adjusted via sysfs interface if needed
+ */
+int lpr_dss_logic_freq = LPR_DSS1_ALWON_FCLK_OPT_FREQ;
+
+/* FPS value in LPR. may be adjusted via sysfs interface */
+int lpr_fps = LPR_DEFAULT_FPS;
+
+static DEFINE_MUTEX(lpr_mutex);
+
+/*
+ * adjust porches and pulses to get desired FPS after pixel clock is adjusted
+ * to LPR value
+ */
+static void lpr_set_fps(int fps)
+{
+ int timing_h, timing_v;
+
+ if (lpr_lowest_dss_logic_freq_enabled) {
+
+ /* adjust porches and pulses to get 60 FPS */
+ timing_h = ((LPR_HBP - 1) << DISPC_TIMING_H_HBP_SHIFT) |
+ ((LPR_HFP - 1) << DISPC_TIMING_H_HFP_SHIFT) |
+ ((LPR_HSW - 1) << DISPC_TIMING_H_HSW_SHIFT);
+ timing_v = (LPR_VBP << DISPC_TIMING_V_VBP_SHIFT) |
+ (LPR_VFP << DISPC_TIMING_V_VFP_SHIFT) |
+ (LPR_VSW << DISPC_TIMING_V_VSW_SHIFT);
+
+ dispc_reg_merge(DISPC_TIMING_H, timing_h,
+ (DISPC_TIMING_H_HBP |
+ DISPC_TIMING_H_HFP |
+ DISPC_TIMING_H_HSW));
+
+ dispc_reg_merge(DISPC_TIMING_V, timing_v,
+ (DISPC_TIMING_V_VBP |
+ DISPC_TIMING_V_VFP |
+ DISPC_TIMING_V_VSW));
+
+ }
+ return;
+}
+
+/**
+ * lpr_set_dss_logic_freq - chose lcd div and pcd based on user input
+ *
+ * If lpr_lowest_dss_logic_freq_enabled flag is set (default) the routine
sets
+ * dss logic frequency equal to twice pixel clock frequency. If the default
+ * setup does not work for an application (dss logic frequency equal to twice
+ * pixel clock frequency is not enough) user can affect the settings using
+ * sysfs interface:
+ * if lpr_lowest_dss_logic_freq_enabled flag is reset the logic frequency is
+ * set to user specified value (may be adjusted using sysfs interface).
+ * Default value in this case is DSS1_ALWON_FCLK frequency.
+ */
+static int lpr_set_dss_logic_freq(void)
+{
+ int lcd_div, pcd;
+
+ if (lpr_lowest_dss_logic_freq_enabled) {
+ /*
+ * set pcd and lcd div to get lowest _both_ pixel clock freq
+ * _and_ logic frequency
+ */
+ pcd = 2;
+ lcd_div = LPR_DSS_LOGIC_DIV;
+ } else {
+ /* set requested DSS logic freq */
+#if 0
+ TODO, not tested!
+
+ lcd_div = LPR_DSS1_ALWON_FCLK_OPT_FREQ / lpr_dss_logic_freq;
+ if (lcd_div < 1)
+ return -EINVAL;
+
+ logic_freq = LPR_DSS1_ALWON_FCLK_OPT_FREQ / lcd_div;
+
+ /*
+ * (LPR_DSS1_ALWON_FCLK_OPT_FREQ / LPR_DSS_LOGIC_DIV) gives best
+ * minimal pixel clock freq for a panel
+ */
+ pcd = logic_freq / (LPR_DSS1_ALWON_FCLK_OPT_FREQ / LPR_DSS_LOGIC_DIV);
+ if (pcd < 1)
+ return -EINVAL;
+#else
+ return -ENOTSUPP;
+#endif /* 0 */
+ }
+
+ dispc_reg_merge(DISPC_DIVISOR,
+ (lcd_div << DISPC_DIVISOR_LCD_SHIFT) |
+ (pcd << DISPC_DIVISOR_PCD_SHIFT),
+ DISPC_DIVISOR_LCD | DISPC_DIVISOR_PCD);
+
+ return 0;
+}
+
+
+/**
+ * omap2_disp_lpr_enable - trigger Low Power Refresh mode
+ *
+ * TODO: desc of LPR
+ */
+
+int omap2_disp_lpr_enable(void)
+{
+ int dss1_rate;
+ int gfx_fifo_thresholds;
+ int rc = 0;
+ int v_attr;
+ int digitalen;
+ unsigned long flags;
+
+ /* Cannot enable lpr if DSS is inactive */
+ if (!graphics_in_use)
+ return -1;
+
+ mutex_lock(&lpr_mutex);
+
+ if (lpr_enabled)
+ goto lpr_out;
+ /*
+ * Check whether LPR can be triggered
+ * - gfx pipeline is routed to LCD
+ * - both video pipelines are disabled (this allows FIFOs merge)
+ */
+
+ /* may be more meaningful error code is required */
+ if (omap2_disp_get_output_dev(OMAP2_GRAPHICS) != OMAP2_OUTPUT_LCD) {
+ rc = -1;
+ goto lpr_out;
+ }
+
+ omap2_disp_get_dss();
+
+ v_attr = dispc_reg_in(DISPC_VID_ATTRIBUTES(0)) |
+ dispc_reg_in(DISPC_VID_ATTRIBUTES(1));
+
+ if (v_attr & DISPC_VID_ATTRIBUTES_ENABLE) {
+ rc = -1;
+ goto lpr_out_clk;
+ }
+
+ /*
+ * currently DSS is running on DSS1 by default. just warn if it has
+ * changed in the future
+ */
+ if (dss_reg_in(DSS_CONTROL) & DSS_CONTROL_APLL_CLK)
+ BUG();
+
+ /* save run mode rate */
+ rmode.rate = dss1_rate = clk_get_rate(dss1f);
+
+ digitalen = dispc_reg_in(DISPC_CONTROL) & DISPC_CONTROL_DIGITALENABLE;
+
+ /* disable DSS before adjusting DSS clock */
+ omap2_disp_disable(HZ/5);
+
+ /* set DSS1_ALWON_FCLK freq */
+ rc = clk_set_rate(dss1f, LPR_DSS1_ALWON_FCLK_OPT_FREQ);
+ if (rc != 0)
+ goto lpr_out_clk_en;
+
+ rmode.divisors = (dispc_reg_in(DISPC_DIVISOR) & (DISPC_DIVISOR_LCD |
+ DISPC_DIVISOR_PCD));
+
+ rmode.timing_h = (dispc_reg_in(DISPC_TIMING_H) & (DISPC_TIMING_H_HBP |
+ DISPC_TIMING_H_HFP |
+ DISPC_TIMING_H_HSW));
+
+ rmode.timing_v = (dispc_reg_in(DISPC_TIMING_V) & (DISPC_TIMING_V_VBP |
+ DISPC_TIMING_V_VFP |
+ DISPC_TIMING_V_VSW));
+
+ /* chose lcd div and pcd based on user input */
+ rc = lpr_set_dss_logic_freq();
+ if (rc != 0)
+ goto lpr_out_clk_en_rate;
+
+ lpr_set_fps(lpr_fps);
+
+ /* set up LPR default FIFO thresholds */
+ gfx_fifo_thresholds =
+ (LPR_GFX_FIFO_HIGH_THRES << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT) |
+ (LPR_GFX_FIFO_LOW_THRES << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT);
+
+ dispc_reg_merge(DISPC_GFX_FIFO_THRESHOLD, gfx_fifo_thresholds,
+ (DISPC_GFX_FIFO_THRESHOLD_HIGH |
+ DISPC_GFX_FIFO_THRESHOLD_LOW));
+
+ dispc_reg_merge(DISPC_CONFIG, DISPC_CONFIG_FIFOMERGE,
+ DISPC_CONFIG_FIFOMERGE);
+
+ /*
+ * save LPR configuration of DISPC and GFX register in case synclost
+ * happens during LPR. If synclost happens LPR parameters get reset
+ * to last-known-good LPR parameters
+ *
+ * may be useful to restore known-good parameters if FIFO underrun
+ * occurs as well
+ */
+ omap2_disp_save_ctx(OMAP2_GRAPHICS);
+
+ spin_lock_irqsave(&dss_lock, flags);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ if (digitalen)
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+
+ omap2_disp_save_ctx(OMAP_DSS_DISPC_GENERIC);
+ spin_unlock_irqrestore(&dss_lock, flags);
+
+ /* let LPR settings to take effect */
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+
+ lpr_enabled = 1;
+
+ omap2_disp_put_dss();
+ mutex_unlock(&lpr_mutex);
+
+ return 0;
+
+lpr_out_clk_en_rate:
+ clk_set_rate(dss1f, rmode.rate);
+
+lpr_out_clk_en:
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ if (digitalen)
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+lpr_out_clk:
+ omap2_disp_put_dss();
+lpr_out:
+ mutex_unlock(&lpr_mutex);
+ return rc;
+}
+
+int omap2_disp_lpr_disable(void)
+{
+ int rc = 0;
+ int gfx_fifo_thresholds;
+ int digitalen;
+ unsigned long flags;
+
+ if (!graphics_in_use)
+ return -1;
+
+ mutex_lock(&lpr_mutex);
+
+ if (!lpr_enabled) {
+ mutex_unlock(&lpr_mutex);
+ return rc;
+ }
+
+
+ omap2_disp_get_dss();
+
+ /* restore DSS divisors */
+ dispc_reg_merge(DISPC_DIVISOR, rmode.divisors,
+ DISPC_DIVISOR_LCD | DISPC_DIVISOR_PCD);
+
+ /* split FIFOs and restore FIFO thresholds */
+ dispc_reg_merge(DISPC_CONFIG, 0, DISPC_CONFIG_FIFOMERGE);
+
+ gfx_fifo_thresholds =
+ (RMODE_GFX_FIFO_HIGH_THRES << DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT) |
+ (RMODE_GFX_FIFO_LOW_THRES << DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT);
+
+ dispc_reg_merge(DISPC_GFX_FIFO_THRESHOLD, gfx_fifo_thresholds,
+ (DISPC_GFX_FIFO_THRESHOLD_HIGH |
+ DISPC_GFX_FIFO_THRESHOLD_LOW));
+
+ dispc_reg_merge(DISPC_TIMING_H, rmode.timing_h, (DISPC_TIMING_H_HBP |
+ DISPC_TIMING_H_HFP |
+ DISPC_TIMING_H_HSW));
+
+ dispc_reg_merge(DISPC_TIMING_V, rmode.timing_v, (DISPC_TIMING_V_VBP |
+ DISPC_TIMING_V_VFP |
+ DISPC_TIMING_V_VSW));
+ /* TODO: adjust porches and pulses if bigger fps is not acceptable */
+
+ digitalen = dispc_reg_in(DISPC_CONTROL) & DISPC_CONTROL_DIGITALENABLE;
+
+ /* disable DSS before adjusting DSS clock */
+ omap2_disp_disable(HZ/5);
+
+ /* restore DSS run mode rate */
+ rc = clk_set_rate(dss1f, rmode.rate);
+
+ omap2_disp_save_ctx(OMAP2_GRAPHICS);
+
+ spin_lock_irqsave(&dss_lock, flags);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ if (digitalen)
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+
+ omap2_disp_save_ctx(OMAP_DSS_DISPC_GENERIC);
+ spin_unlock_irqrestore(&dss_lock, flags);
+
+ omap2_disp_reg_sync(OMAP2_OUTPUT_LCD);
+
+ omap2_disp_put_dss();
+
+ lpr_enabled = 0;
+
+ mutex_unlock(&lpr_mutex);
+ return rc;
+}
+#endif /* CONFIG_ARCH_OMAP34XX */
+
+/* Start before devices */
+subsys_initcall(omap2_disp_init);
+
+EXPORT_SYMBOL(omap2_disp_request_layer);
+EXPORT_SYMBOL(omap2_disp_release_layer);
+EXPORT_SYMBOL(omap2_disp_disable_layer);
+EXPORT_SYMBOL(omap2_disp_enable_layer);
+EXPORT_SYMBOL(omap2_disp_config_vlayer);
+EXPORT_SYMBOL(omap2_disp_config_gfxlayer);
+EXPORT_SYMBOL(omap2_disp_start_vlayer);
+EXPORT_SYMBOL(omap2_disp_start_gfxlayer);
+
+EXPORT_SYMBOL(omap2_disp_set_bg_color);
+EXPORT_SYMBOL(omap2_disp_get_bg_color);
+EXPORT_SYMBOL(omap2_disp_set_dithering);
+EXPORT_SYMBOL(omap2_disp_get_dithering);
+EXPORT_SYMBOL(omap2_disp_get_panel_size);
+EXPORT_SYMBOL(omap2_disp_set_panel_size);
+EXPORT_SYMBOL(omap2_disp_disable_output_dev);
+EXPORT_SYMBOL(omap2_disp_enable_output_dev);
+EXPORT_SYMBOL(omap2_disp_set_tvstandard);
+EXPORT_SYMBOL(omap2_disp_get_tvstandard);
+EXPORT_SYMBOL(omap2_disp_set_tvlcd);
+EXPORT_SYMBOL(omap2_disp_get_tvlcd);
+EXPORT_SYMBOL(omap2_disp_config_lcd);
+EXPORT_SYMBOL(omap2_disp_lcdcfg_polfreq);
+EXPORT_SYMBOL(omap2_disp_set_pcd);
+
+EXPORT_SYMBOL(omap2_disp_set_dma_params);
+EXPORT_SYMBOL(omap2_disp_get_output_dev);
+EXPORT_SYMBOL(omap2_disp_set_output_dev);
+
+#ifdef CONFIG_ARCH_OMAP34XX
+EXPORT_SYMBOL(omap2_disp_set_alphablend);
+EXPORT_SYMBOL(omap2_disp_get_alphablend);
+EXPORT_SYMBOL(omap2_disp_set_global_alphablend_value);
+EXPORT_SYMBOL(omap2_disp_get_global_alphablend_value);
+#endif
+
+EXPORT_SYMBOL(omap24xx_ll_config_disp_clocks);
+EXPORT_SYMBOL(omap2_disp_set_dssfclk);
+EXPORT_SYMBOL(omap2_disp_get_dss);
+EXPORT_SYMBOL(omap2_disp_put_dss);
+
+EXPORT_SYMBOL(omap2_disp_get_all_clks);
+EXPORT_SYMBOL(omap2_disp_put_all_clks);
+
+EXPORT_SYMBOL(omap2_disp_set_default_colorconv);
+EXPORT_SYMBOL(omap2_disp_set_colorconv);
+EXPORT_SYMBOL(omap2_disp_set_colorkey);
+EXPORT_SYMBOL(omap2_disp_get_colorkey);
+EXPORT_SYMBOL(omap2_disp_enable_colorkey);
+EXPORT_SYMBOL(omap2_disp_disable_colorkey);
+EXPORT_SYMBOL(omap2_disp_reg_sync_bit);
+
+EXPORT_SYMBOL(omap2_disp_set_gfx_palette);
+EXPORT_SYMBOL(omap2_disp_pixels_per_clock);
+
+EXPORT_SYMBOL(omap2_disp_set_vrfb);
+EXPORT_SYMBOL(omap2_disp_save_initstate);
+EXPORT_SYMBOL(omap2_disp_reg_sync);
+EXPORT_SYMBOL(omap2_disp_reg_sync_done);
+EXPORT_SYMBOL(omap2_disp_disable);
+
+EXPORT_SYMBOL(omap2_disp_register_isr);
+EXPORT_SYMBOL(omap2_disp_unregister_isr);
+EXPORT_SYMBOL(omap2_disp_irqenable);
+EXPORT_SYMBOL(omap2_disp_irqdisable);
+
+EXPORT_SYMBOL(current_colorconv_values);
diff --git a/drivers/i2c/chips/Makefile b/drivers/i2c/chips/Makefile
index 1f81ebd..d93c87c 100644
--- a/drivers/i2c/chips/Makefile
+++ b/drivers/i2c/chips/Makefile
@@ -23,7 +23,7 @@ obj-$(CONFIG_GPIOEXPANDER_OMAP) += gpio_expander_omap.o
obj-$(CONFIG_MENELAUS) += menelaus.o
obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
-obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o
+obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-pwrirq.o twl4030_power.o
obj-$(CONFIG_TWL4030_GPIO) += twl4030-gpio.o
obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o
obj-$(CONFIG_TWL4030_POWEROFF) += twl4030-poweroff.o
diff --git a/drivers/i2c/chips/twl4030_power.c
b/drivers/i2c/chips/twl4030_power.c
new file mode 100644
index 0000000..975af5d
--- /dev/null
+++ b/drivers/i2c/chips/twl4030_power.c
@@ -0,0 +1,540 @@
+/*
+ * arch/arm/plat-omap/power_companion.c
+ *
+ * This file contains code to control TWL4030 power compaion chip operation.
+ *
+ * Copyright (C) 2006 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <asm/arch/power_companion.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/prcm.h>
+#include <asm/semaphore.h>
+
+/* Note: H4 uses the Menelaus companion chip. Currently it is assumed u-boot
+ * has set up the chip. For Triton2, some part of this is done by the
loader.
+ * However, it turns out that a polled mode u-boot I2C setup can take a long
+ * time. So major init sequences are better done here. T2 needs to setup
+ * sequences before it can effectively shut down its HF clock and handle more
+ * complex power needs.
+ */
+
+int power_companion_initialized = 0;
+
+struct semaphore pwr_reg_lock;
+
+static int vaux1_ldo_use_count;
+
+int twl4030_vaux1_ldo_use(void)
+{
+ vaux1_ldo_use_count++;
+
+ /* If first module to use the VAUX2 voltage, enable the voltage */
+ if (vaux1_ldo_use_count == 1) {
+ if (0 != t2_out(PM_RECEIVER, ENABLE_VAUX1_DEDICATED,
+ TWL4030_VAUX1_DEDICATED)) {
+ vaux1_ldo_use_count--;
+ return -EIO;
+ }
+ if (0 != t2_out(PM_RECEIVER, ENABLE_VAUX1_DEV_GRP,
+ TWL4030_VAUX1_DEV_GRP)) {
+ vaux1_ldo_use_count--;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_vaux1_ldo_use);
+
+int twl4030_vaux1_ldo_unuse(void)
+{
+ if (vaux1_ldo_use_count == 0)
+ return 0;
+
+ /* If VAUX2 voltage is not used by any modules, disable the voltage */
+ vaux1_ldo_use_count--;
+ if (vaux1_ldo_use_count == 0) {
+ /*
+ * The VAUX2 voltage is not used by any module
+ * Disable the voltage
+ */
+ if (0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX1_DEDICATED)) {
+ vaux1_ldo_use_count++;
+ return -EIO;
+ }
+ if (0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX1_DEV_GRP)) {
+ vaux1_ldo_use_count++;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_vaux1_ldo_unuse);
+
+static int vaux2_ldo_use_count = 0;
+
+int twl4030_vaux2_ldo_use(void)
+{
+ vaux2_ldo_use_count++;
+
+ /* If first module to use the VAUX2 voltage, enable the voltage */
+ if(vaux2_ldo_use_count == 1){
+ if(0!= t2_out(PM_RECEIVER, ENABLE_VAUX2_DEDICATED,
+ TWL4030_VAUX2_DEDICATED)) {
+ vaux2_ldo_use_count--;
+ return -EIO;
+ }
+ if(0!= t2_out(PM_RECEIVER, ENABLE_VAUX2_DEV_GRP,
+ TWL4030_VAUX2_DEV_GRP)) {
+ vaux2_ldo_use_count--;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+
+int twl4030_vaux2_ldo_unuse(void)
+{
+ if (vaux2_ldo_use_count == 0)
+ return 0;
+
+ /* If VAUX2 voltage is not used by any modules, disable the voltage */
+ vaux2_ldo_use_count--;
+ if(vaux2_ldo_use_count == 0){
+ /*
+ * The VAUX2 voltage is not used by any module
+ * Disable the voltage
+ */
+ if( 0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX2_DEDICATED)) {
+ vaux2_ldo_use_count++;
+ return -EIO;
+ }
+ if( 0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX2_DEV_GRP)) {
+ vaux2_ldo_use_count++;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_vaux2_ldo_use);
+EXPORT_SYMBOL(twl4030_vaux2_ldo_unuse);
+
+static int vaux3_ldo_use_count = 0;
+int twl4030_vaux3_ldo_use(void)
+{
+ vaux3_ldo_use_count++;
+
+ /* If first module to use the VAUX2 voltage, enable the voltage */
+ if(vaux3_ldo_use_count == 1){
+ if(0!= t2_out(PM_RECEIVER, ENABLE_VAUX3_DEDICATED,
+ TWL4030_VAUX3_DEDICATED)) {
+ vaux3_ldo_use_count--;
+ return -EIO;
+ }
+ if(0!= t2_out(PM_RECEIVER, ENABLE_VAUX3_DEV_GRP,
+ TWL4030_VAUX3_DEV_GRP)) {
+ vaux3_ldo_use_count--;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+int twl4030_vaux3_ldo_unuse(void)
+{
+ if (vaux3_ldo_use_count == 0)
+ return 0;
+
+ /* If VAUX3 voltage is not used by any modules, disable the voltage */
+ vaux3_ldo_use_count--;
+ if(vaux3_ldo_use_count == 0){
+ /*
+ * The VAUX3 voltage is not used by any module
+ * Disable the voltage
+ */
+ if( 0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX3_DEDICATED)) {
+ vaux3_ldo_use_count++;
+ return -EIO;
+ }
+
+ if( 0 != t2_out(PM_RECEIVER, 0x00, TWL4030_VAUX3_DEV_GRP)) {
+ vaux3_ldo_use_count++;
+ return -EIO;
+ }
+ }
+ return 0;
+}
+EXPORT_SYMBOL(twl4030_vaux3_ldo_use);
+EXPORT_SYMBOL(twl4030_vaux3_ldo_unuse);
+
+int enable_vmode_companion_voltage_scaling(int vdd, int floor, int roof,
+ int mode)
+{
+ int e = 0;
+
+ /* set floor, roof voltage, enable jump mode, enable scaling */
+ if (vdd == PRCM_VDD1) {
+ e |= t2_out(PM_RECEIVER, floor, R_VDD1_VFLOOR);
+ e |= t2_out(PM_RECEIVER, roof, R_VDD1_VROOF);
+ e |= t2_out(PM_RECEIVER, mode, R_VDD1_STEP);
+ e |= t2_out(PM_RECEIVER, EN_SCALE, R_VDD1_VMODE_CFG);
+ }
+ else if (vdd == PRCM_VDD2) {
+ e |= t2_out(PM_RECEIVER, floor, R_VDD2_VFLOOR);
+ e |= t2_out(PM_RECEIVER, roof, R_VDD2_VROOF);
+ e |= t2_out(PM_RECEIVER, mode, R_VDD2_STEP);
+ e |= t2_out(PM_RECEIVER, EN_SCALE, R_VDD2_VMODE_CFG);
+ }
+ if(e){
+ printk(KERN_ERR "Error enabling voltage scaling\n");
+ e = -EIO;
+ }
+ return e;
+}
+EXPORT_SYMBOL(enable_vmode_companion_voltage_scaling);
+
+int disable_vmode_companion_voltage_scaling(void)
+{
+ int e = 0;
+ e = t2_out(PM_RECEIVER, DIS_SCALE, R_VDD1_VMODE_CFG);
+ if(e)
+ e = -EIO;
+ return e;
+}
+EXPORT_SYMBOL(disable_vmode_companion_voltage_scaling);
+
+int write_val_companion_reg(u8 mod_no, u8 value, u8 reg)
+{
+ int e = 0;
+
+ down(&pwr_reg_lock);
+ e |= t2_out(mod_no, value, reg);
+ up(&pwr_reg_lock);
+ if(e){
+ printk(KERN_ERR "TWL4030 Power Companion Register Access Error\n");
+ e = -EIO;
+ }
+ return e;
+}
+EXPORT_SYMBOL(write_val_companion_reg);
+
+int set_bits_companion_reg(u8 mod_no, u8 value, u8 reg)
+{
+ int e = 0;
+ u8 RdReg;
+
+ down(&pwr_reg_lock);
+ e |= t2_in(mod_no, &RdReg, reg);
+ RdReg |= value;
+ e |= t2_out(mod_no, RdReg, reg);
+ up(&pwr_reg_lock);
+ if(e){
+ printk(KERN_ERR "TWL4030 Power Companion Register Access Error\n");
+ e = -EIO;
+ }
+ return e;
+}
+EXPORT_SYMBOL(set_bits_companion_reg);
+
+int clear_bits_companion_reg(u8 mod_no, u8 value, u8 reg)
+{
+ int e = 0;
+ u8 RdReg;
+
+ down(&pwr_reg_lock);
+ e |= t2_in(mod_no, &RdReg, reg);
+ RdReg &= ~value;
+ e |= t2_out(mod_no, RdReg, reg);
+ up(&pwr_reg_lock);
+ if(e){
+ printk(KERN_ERR "TWL4030 Power Companion Register Access Error\n");
+ e = -EIO;
+ }
+ return e;
+}
+EXPORT_SYMBOL(clear_bits_companion_reg);
+
+static int protect_pm_master(void)
+{
+ int e = 0;
+ e = t2_out(PM_MASTER, KEY_LOCK, R_PROTECT_KEY);
+ return e;
+}
+
+static int unprotect_pm_master(void)
+{
+ int e = 0;
+ e |= t2_out(PM_MASTER, KEY_UNLOCK1, R_PROTECT_KEY);
+ e |= t2_out(PM_MASTER, KEY_UNLOCK2, R_PROTECT_KEY);
+ return e;
+}
+
+static int init_pwr_intc(void)
+{
+ int e;
+
+ /* Set interrupt to clear when we write it. Enable interrupt
+ * exclusively between INT1 and INT2
+ */
+ e = t2_out(PM_INT, (SIH_COR|SIH_EXCLEN), R_PWR_SIH_CTRL);
+
+ /* mask all PWR INT1/2 interrupts */
+ e |= t2_out(PM_INT, 0xFF, R_PWR_IMR1);
+ e |= t2_out(PM_INT, 0xFF, R_PWR_IMR2);
+
+ /* disable falling and rising edge of all PWR sources */
+ e |=t2_out(PM_INT, 0x00, R_PWR_EDR1);
+ e |=t2_out(PM_INT, 0x00, R_PWR_EDR2);
+
+ /* clear all PWR INT1/2 interrupts */
+ e |= t2_out(PM_INT, 0xFF, R_PWR_ISR1);
+ e |= t2_out(PM_INT, 0xFF, R_PWR_ISR2);
+
+ return e;
+}
+
+/* Set up an action to shut down T2's clocks and wake them up
+ * following P1. Depending on usage this sequence might be
+ * reduced to just a unicast to the HFCLKOUT resource.
+ */
+static int config_sleep_wake_sequence(void)
+{
+ #define A2S_I 2
+ #define AS2_J 4
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ #define S2A_I 2
+#else
+ #define S2A_I 3
+#endif
+ #define S2A_J 4
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ u8 sleep_on_seq[A2S_I][AS2_J] = {{0x20, 0xF0, 0x04, 0x2C},
+ {0x21, 0x00, 0x02, 0x3F} };
+
+ u8 sleep_off_seq[S2A_I][S2A_J] = {{0x20, 0xFE, 0x30, 0x2E},
+ {0x21, 0x0E, 0x37, 0x2F} };
+#else
+ u8 sleep_on_seq[A2S_I][AS2_J] = {{0x14, 0x78, 0x04, 0x2C},
+ {0x1E, 0x78, 0x02, 0x3F} };
+
+ u8 sleep_off_seq[S2A_I][S2A_J] = {{0x01, 0x7E, 0x30, 0x2E},
+ {0x1A, 0x7E, 0x37, 0x2F},
+ {0x1E, 0x7E, 0x02, 0x3F} };
+#endif
+ int e=0, i=0, j=0;
+ u8 data;
+ /* CLKREQ is pulled high on the 2430SDP, therefore, we need to take
+ * it out of the HFCLKOUT DEV_GRP for P1 else HFCLKOUT can't be stopped.
+ */
+ e |=t2_out(PM_RECEIVER, 0x20, R_HFCLKOUT_DEV_GRP);
+
+ /* Set ACTIVE to SLEEP SEQ address in T2 memory*/
+ e |=t2_out(PM_MASTER, 0x2B, R_SEQ_ADD_A2S);
+ /* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
+ e |=t2_out(PM_MASTER, 0x2D, R_SEQ_ADD_SA12);
+ /* Set SLEEP to ACTIVE SEQ address for P3 */
+ e |=t2_out(PM_MASTER, 0x2D, R_SEQ_ADD_S2A3);
+
+ /* Install Active->Sleep (A2S) sequence */
+ while (i < A2S_I){
+ while (j < AS2_J){
+ data = (((0x2B + i) << 2) + j ); /*set starting t2-addr*/
+ e |= t2_out(PM_MASTER, data, R_MEMORY_ADDRESS); /*select t2-addr*/
+ data = sleep_on_seq[i][j]; /* get data */
+ e |= t2_out(PM_MASTER, data, R_MEMORY_DATA); /*data into t2-addr*/
+ j++;
+ }
+ j=0;
+ i++;
+ }
+
+ i = j = 0;
+
+ /* Install Sleep->Active (S2A) sequence */
+ while (i < S2A_I){
+ while (j < S2A_J){
+ data = (((0x2D + i) << 2) + j ); /* set starting t2-addr */
+ e |= t2_out(PM_MASTER, data, R_MEMORY_ADDRESS); /* sel t2-addr */
+ data = sleep_off_seq[i][j]; /* get data */
+ e |= t2_out(PM_MASTER, data, R_MEMORY_DATA); /* put into t2-addr */
+ j++;
+ }
+ j=0;
+ i++;
+ }
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ /* Disabling AC charger effect on sleep-active transitions */
+ e |= t2_in(PM_MASTER, &data, R_CFG_P1_TRANSITION);
+ data &= 0x0;
+ e |= t2_out(PM_MASTER, data , R_CFG_P1_TRANSITION);
+#endif
+ /* P1/P2/P3 LVL_WAKEUP should be on LEVEL */
+ e |= t2_out(PM_MASTER, LVL_WAKEUP, R_P1_SW_EVENTS);
+ e |= t2_out(PM_MASTER, LVL_WAKEUP, R_P2_SW_EVENTS);
+ e |= t2_out(PM_MASTER, LVL_WAKEUP, R_P3_SW_EVENTS);
+
+ if(e)
+ printk(KERN_ERR "TWL4030 Power Companion seq config error\n");
+
+ return e;
+}
+
+#ifdef CONFIG_OMAP_VOLT_VSEL
+/*
+ * This function sets the VSEL values in the Triton Power IC. This is done in
+ * the software configurable mode.
+ */
+int set_voltage_level (u8 vdd, u8 vsel)
+{
+ int e = 0;
+
+ /* Disabling the SmartReflex */
+ if ((e = clear_bits_companion_reg(PM_RECEIVER,
+ DCDC_GLOBAL_CFG_ENABLE_SRFLX,
+ R_DCDC_GLOBAL_CFG))) {
+ printk (KERN_INFO "Unable to disable SR\n");
+ return e;
+ }
+
+ if (vdd == PRCM_VDD1) {
+ /* Enable in software configuration mode, by disabling the
+ * hardware mode.
+ */
+ if ((e = clear_bits_companion_reg(PM_RECEIVER,
+ VDD1_VMODE_CFG_ENABLE_VMODE,
+ R_VDD1_VMODE_CFG))) {
+ printk (KERN_INFO "Unable to set Power IC in software \
+ controlled mode\n");
+ return e;
+ }
+
+ /* Set the step mode to single step */
+ if ((e = set_bits_companion_reg (PM_RECEIVER,
+ VDD1_STEP_STEP_REG_0,
+ R_VDD1_STEP))) {
+ printk (KERN_INFO "Unable to set the Voltage Step to \
+ zero\n");
+ return e;
+ }
+
+ /* Set the VSEL value */
+ if ((e = write_val_companion_reg (PM_RECEIVER,
+ vsel,
+ R_VDD1_VSEL))) {
+ printk (KERN_INFO "Unable to set the Voltage level to \
+ vsel\n");
+ return e;
+ }
+ }
+ else { /* VDD2 */
+ /* Presently only 2 OPP levels (i.e. OPP1 and OPP2) are supported */
+
+ /* Enable in software configuration mode, by disabling the
+ * hardware mode.
+ */
+ if ((e = clear_bits_companion_reg(PM_RECEIVER,
+ VDD2_VMODE_CFG_ENABLE_VMODE,
+ R_VDD2_VMODE_CFG))) {
+ printk (KERN_INFO "Unable to set Power IC in software \
+ controlled mode\n");
+ return e;
+ }
+
+ /* Set the step mode to single step */
+ if ((e = set_bits_companion_reg (PM_RECEIVER,
+ VDD2_STEP_STEP_REG_0,
+ R_VDD2_STEP))) {
+ printk (KERN_INFO "Unable to set the Voltage Step to \
+ zero\n");
+ return e;
+ }
+
+ /* Set the VSEL value */
+ if ((e = write_val_companion_reg (PM_RECEIVER,
+ vsel,
+ R_VDD2_VSEL))) {
+ printk (KERN_INFO "Unable to set the Voltage level to \
+ vsel\n");
+ return e;
+ }
+ }
+ /* 10 microsecond delay for the single step voltage to stabilize */
+ udelay (10);
+
+ return e;
+}
+EXPORT_SYMBOL(set_voltage_level);
+#endif /* CONFIG_OMAP_VOLT_VSEL */
+
+int power_companion_init(void)
+{
+ struct clk *osc;
+ u32 rate, ctrl = HFCLK_FREQ_26_MHZ;
+ int e = 0;
+
+ if(power_companion_initialized != 0)
+ return 0;
+
+ osc = clk_get(NULL,"osc_ck");
+ rate = clk_get_rate(osc);
+ clk_put(osc);
+
+ switch(rate) {
+ case 19200000 : ctrl = HFCLK_FREQ_19p2_MHZ; break;
+ case 26000000 : ctrl = HFCLK_FREQ_26_MHZ; break;
+ case 38400000 : ctrl = HFCLK_FREQ_38p4_MHZ; break;
+ }
+ ctrl |= HIGH_PERF_SQ;
+
+ /* Semaphore lock to prevent concurrent access */
+ init_MUTEX(&pwr_reg_lock);
+
+ e |= unprotect_pm_master();
+ e |= t2_out(PM_MASTER, ctrl, R_CFG_BOOT); /* effect->MADC+USB ck en */
+ e |= init_pwr_intc();
+ e |= config_sleep_wake_sequence(); /* Set action for P1-SLEEP1 */
+ e |= protect_pm_master();
+
+#ifdef CONFIG_OMAP_VOLT_VMODE
+ if (cpu_is_omap24xx())
+ e |= enable_vmode_companion_voltage_scaling(PRCM_VDD1, V_1p05,
+ V_1p3, EN_JMP);
+ else if (cpu_is_omap3430()) {
+ e |= enable_vmode_companion_voltage_scaling(PRCM_VDD1, V_1p05,
+ V_1p2, EN_JMP);
+ e |= enable_vmode_companion_voltage_scaling(PRCM_VDD2, V_1p15,
+ V_1p15, EN_JMP);
+ }
+#elif defined(CONFIG_OMAP_VOLT_SR) || defined(CONFIG_OMAP_VOLT_SR_BYPASS)
+ /* Enabling the SmartReflex */
+ e = set_bits_companion_reg(PM_RECEIVER, DCDC_GLOBAL_CFG_ENABLE_SRFLX,
+ R_DCDC_GLOBAL_CFG);
+ if (e)
+ printk(KERN_INFO "Unable to enable SR\n");
+#endif
+
+ if(e){
+ printk(KERN_ERR "TWL4030 Power Companion Init Error\n");
+ e = -EIO;
+ } else {
+ power_companion_initialized = 1;
+ printk(KERN_INFO "TWL4030 Power Companion Active\n");
+ }
+ return e;
+}
+EXPORT_SYMBOL(power_companion_init);
diff --git a/drivers/media/video/omap/Kconfig
b/drivers/media/video/omap/Kconfig
index c8d1f4c..ac5a4e9 100644
--- a/drivers/media/video/omap/Kconfig
+++ b/drivers/media/video/omap/Kconfig
@@ -5,3 +5,6 @@ config VIDEO_OMAP_CAMERA
depends on VIDEO_DEV && (ARCH_OMAP16XX || ARCH_OMAP24XX)
help
V4L2 camera driver support for OMAP1/2 based boards.
+
+config VIDEO_OMAP24XX_TVOUT
+ bool "TV out support"
diff --git a/drivers/video/omap/Kconfig b/drivers/video/omap/Kconfig
index bdeb8fb..554a136 100644
--- a/drivers/video/omap/Kconfig
+++ b/drivers/video/omap/Kconfig
@@ -74,4 +74,6 @@ config FB_OMAP_DMA_TUNE
answer yes. Answer no if you have a dedicated video
memory, or don't use any of the accelerated features.
-
+config FB_OMAP_LCD_VGA
+ tristate "OMAP 3430 SDP VGA Display"
+ depends on ARCH_OMAP34XX
diff --git a/drivers/video/omap/Makefile b/drivers/video/omap/Makefile
index fe7ee5d..be08029 100644
--- a/drivers/video/omap/Makefile
+++ b/drivers/video/omap/Makefile
@@ -2,13 +2,16 @@
# Makefile for the new OMAP framebuffer device driver
#
+ifeq ($(CONFIG_ARCH_OMAP3),y)
+ obj-$(CONFIG_FB_OMAP) += omap_disp_out.o
+ obj-$(CONFIG_FB_OMAP) += omap_fb.o
+else
obj-$(CONFIG_FB_OMAP) += omapfb.o
objs-yy := omapfb_main.o
objs-y$(CONFIG_ARCH_OMAP1) += lcdc.o
objs-y$(CONFIG_ARCH_OMAP2) += dispc.o
-objs-y$(CONFIG_ARCH_OMAP3) += dispc.o
objs-$(CONFIG_ARCH_OMAP1)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
objs-$(CONFIG_ARCH_OMAP2)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += rfbi.o
@@ -29,11 +32,10 @@ objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o
objs-y$(CONFIG_MACH_SX1) += lcd_sx1.o
objs-y$(CONFIG_MACH_OMAP_APOLLON) += lcd_apollon.o
-objs-y$(CONFIG_MACH_OMAP_2430SDP) += lcd_2430sdp.o
-objs-y$(CONFIG_MACH_OMAP_3430SDP) += lcd_2430sdp.o
objs-y$(CONFIG_MACH_OMAP3EVM) += lcd_omap3evm.o
objs-y$(CONFIG_MACH_OMAP3_BEAGLE) += lcd_omap3beagle.o
objs-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o
+endif
omapfb-objs := $(objs-yy)
diff --git a/drivers/video/omap/omap_disp_out.c
b/drivers/video/omap/omap_disp_out.c
new file mode 100644
index 0000000..2085960
--- /dev/null
+++ b/drivers/video/omap/omap_disp_out.c
@@ -0,0 +1,1757 @@
+/*
+ * drivers/video/omap/omap2_disp_out.c
+ *
+ * Driver for LCD and TV output on OMAP24xx SDPs
+ * - Tested on OMAP2420 H4
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * History:
+ * 30-Mar-2006 Khasim Added LCD data lines 18/16 support
+ * 15-Apr-2006 Khasim Modified proc fs to sysfs
+ * 20-Apr-2006 Khasim Modified PM/DPM support for Mobi-Linux
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/proc_fs.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#ifdef CONFIG_TRACK_RESOURCES
+#include <linux/device.h>
+#endif
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+#include <asm/delay.h>
+#include <linux/delay.h>
+#include <asm/arch/display.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clock.h>
+#if defined(CONFIG_MACH_OMAP_2430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR)
+#include <asm/arch/twl4030.h>
+#endif
+#include <linux/workqueue.h>
+#include <asm/arch/power_companion.h>
+#ifdef CONFIG_PM
+#include <linux/notifier.h>
+#include <linux/pm.h>
+#endif
+#include <linux/platform_device.h>
+#include "omap_fb.h"
+
+#define DRIVER "omap2_disp_out"
+#define DRIVER_DESC "OMAP Display output driver"
+
+#define OMAP2_LCD_DRIVER "omap2_lcd"
+#define OMAP2_TV_DRIVER "omap2_tv"
+
+
+#ifdef CONFIG_MACH_OMAP_H4
+#define OMAP24xx_LCD_DEVICE "h4_lcd"
+#define OMAP24xx_TV_DEVICE "h4_tv"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_2430SDP
+#define OMAP24xx_LCD_DEVICE "sdp2430_lcd"
+#define OMAP24xx_TV_DEVICE "sdp2430_tv"
+#endif
+
+#if defined(CONFIG_MACH_OMAP_3430SDP) ||
defined(CONFIG_MACH_OMAP_3430LABRADOR) || defined(CONFIG_MACH_OMAP3_BEAGLE)
+#if 0
+#define OMAP24xx_LCD_DEVICE "sdp3430_lcd"
+#define OMAP24xx_TV_DEVICE "sdp3430_tv"
+#else
+#define OMAP24xx_LCD_DEVICE "omap2_lcd"
+#define OMAP24xx_TV_DEVICE "omap2_tv"
+#endif
+#endif
+
+#ifdef CONFIG_FB_OMAP_LCD_VGA
+#define H4_LCD_XRES 480
+#define H4_LCD_YRES 640
+#define H4_LCD_PIXCLOCK_MAX 41700 /* in pico seconds */
+#define H4_LCD_PIXCLOCK_MIN 38000 /* in pico seconds */
+#else
+#ifdef CONFIG_OMAP3430_ES2
+#define H4_LCD_XRES 240
+#define H4_LCD_YRES 320
+#define H4_LCD_PIXCLOCK_MAX 167000 /* in pico seconds */
+#define H4_LCD_PIXCLOCK_MIN 152000 /* in pico seconds */
+#else
+#define H4_LCD_XRES 240
+#define H4_LCD_YRES 320
+#define H4_LCD_PIXCLOCK_MAX 185186 /* freq 5.4 MHz */
+#define H4_LCD_PIXCLOCK_MIN 138888 /* freq 7.2 MHz */
+#endif
+#endif
+
+#define H4_TV_XRES 640
+#define H4_TV_YRES 480
+
+#ifdef CONFIG_MACH_OMAP_2430SDP
+#define LCD_PANEL_ENABLE_GPIO 154
+#define LCD_PANEL_BACKLIGHT_GPIO 91
+#endif
+
+#if defined(CONFIG_ARCH_OMAP3430)
+#if defined(CONFIG_MACH_OMAP_3430LABRADOR)
+#define LCD_PANEL_ENABLE_GPIO 15
+#define LCD_PANEL_BACKLIGHT_GPIO 7
+#elif defined(CONFIG_OMAP3430_ES2)
+#define LCD_PANEL_ENABLE_GPIO 5
+#define LCD_PANEL_BACKLIGHT_GPIO 8
+#else
+#define LCD_PANEL_ENABLE_GPIO 28
+#define LCD_PANEL_BACKLIGHT_GPIO 24
+#endif
+#endif
+
+#define CONFIG_OMAP2_LCD
+#define ENABLE_VDAC_DEDICATED 0x03
+#define ENABLE_VDAC_DEV_GRP 0x20
+#define ENABLE_VPLL2_DEDICATED 0x05
+#define ENABLE_VPLL2_DEV_GRP 0xE0
+
+#ifdef CONFIG_VIDEO_OMAP24XX_TVOUT
+#define CONFIG_OMAP2_TV
+#define MENELAUS_I2C_ADAP_ID 0
+#endif
+
+extern int omap24xx_get_dss1_clock(void);
+extern ssize_t
+fb_out_show(struct device *cdev, struct device_attribute *attr, char *buf);
+
+extern ssize_t
+fb_out_store(struct device *cdev, struct device_attribute *attr, const char
*buffer, size_t count);
+
+extern int fb_out_layer;
+extern int omap24xxfb_set_output_layer(int layer);
+
+extern int twl4030_request_gpio(int gpio);
+extern int twl4030_free_gpio(int gpio);
+extern int twl4030_set_gpio_dataout(int gpio, int enable);
+extern int twl4030_set_gpio_direction(int gpio, int is_input);
+
+
+#ifdef CONFIG_ARCH_OMAP34XX
+extern int lpr_enabled;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CONFIG_OMAP2_LCD
+
+static int lcd_in_use;
+static int lcd_backlight_state=1;
+
+static int previous_lcd_backlight_state=1;
+
+#ifdef CONFIG_MACH_OMAP_H4
+static int h4_read_gpio_expa(u8 *val);
+static int h4_write_gpio_expa(u8 val);
+#endif
+
+static void lcd_backlight_off(struct work_struct *work);
+static void lcd_backlight_on(struct work_struct *work);
+
+#define MOD_INC_USE_COUNT
+#define MOD_DEC_USE_COUNT
+
+DECLARE_WORK(lcd_bklight_on, lcd_backlight_on);
+DECLARE_WORK(lcd_bklight_off, lcd_backlight_off);
+
+static void lcd_panel_enable(struct work_struct *work);
+static void lcd_panel_disable(struct work_struct *work);
+
+DECLARE_WORK(lcd_panel_on, lcd_panel_enable);
+DECLARE_WORK(lcd_panel_off, lcd_panel_disable);
+
+static void
+power_lcd_backlight(int level)
+{
+ switch (level) {
+ case LCD_OFF:
+ if(!in_interrupt())
+ lcd_backlight_off(NULL);
+ else
+ schedule_work(&lcd_bklight_off);
+ break;
+ default:
+ if(!in_interrupt())
+ lcd_backlight_on(NULL);
+ else
+ schedule_work(&lcd_bklight_on);
+ break;
+ }
+}
+
+static void
+power_lcd_panel(int level)
+{
+ switch (level) {
+ case LCD_OFF:
+ if(!in_interrupt())
+ lcd_panel_disable(NULL);
+ else
+ schedule_work(&lcd_panel_off);
+ break;
+ default:
+ if(!in_interrupt())
+ lcd_panel_enable(NULL);
+ else
+ schedule_work(&lcd_panel_on);
+ break;
+ }
+}
+
+#ifdef CONFIG_MACH_OMAP_H4
+
+/* Write to GPIO EXPA on the board.
+ * The GPIO expanders need an independent I2C client driver.
+ */
+static int
+h4_write_gpio_expa(u8 val)
+{
+ struct i2c_adapter *adap;
+ int err;
+ struct i2c_msg msg[1];
+ unsigned char data[1];
+
+ adap = i2c_get_adapter(0);
+ if (!adap)
+ return -ENODEV;
+ msg->addr = 0x20; /* I2C address of GPIO EXPA */
+ msg->flags = 0;
+ msg->len = 1;
+ msg->buf = data;
+ data[0] = val;
+ err = i2c_transfer(adap, msg, 1);
+ if (err >= 0)
+ return 0;
+ return err;
+}
+
+/* Read from GPIO EXPA on the board.
+ * The GPIO expanders need an independent I2C client driver.
+ */
+static int
+h4_read_gpio_expa(u8 *val)
+{
+ struct i2c_adapter *adap;
+ int err;
+ struct i2c_msg msg[1];
+ unsigned char data[1];
+
+ adap = i2c_get_adapter(0);
+ if (!adap)
+ return -ENODEV;
+ msg->addr = 0x20; /* I2C address of GPIO EXPA */
+ msg->flags = I2C_M_RD;
+ msg->len = 1;
+ msg->buf = data;
+ err = i2c_transfer(adap, msg, 1);
+ *val = data[0];
+ if (err >= 0)
+ return 0;
+ return err;
+}
+#endif
+
+static void
+lcd_panel_enable(struct work_struct *work)
+{
+#ifdef CONFIG_MACH_OMAP_H4
+ unsigned char expa;
+ int err;
+
+ /* read current state of GPIO EXPA outputs */
+ if ((err = h4_read_gpio_expa(&expa))) {
+ printk(KERN_ERR DRIVER
+ "Error reading GPIO EXPA\n");
+ return;
+ }
+ /* Set GPIO EXPA P7 (LCD_ENVDD) to power-up LCD and
+ * set GPIO EXPA P5 (LCD_ENBKL) to turn on backlight
+ */
+ if ((err = h4_write_gpio_expa(expa | 0x80))) {
+ printk(KERN_ERR DRIVER
+ "Error writing to GPIO EXPA\n");
+ return;
+ }
+#endif
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 1);
+ /* power to the RGB lines from T2 is issued separately in
+ * omap2_dss-rgb_enable */
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 1);
+#endif
+}
+void
+omap2_dss_rgb_enable(void)
+{
+#ifdef CONFIG_MACH_OMAP_2430SDP
+ twl4030_vaux2_ldo_use();
+#else
+ if(is_sil_rev_less_than(OMAP3430_REV_ES2_0)) {
+ if( 0 != twl4030_vaux3_ldo_use())
+ printk(KERN_WARNING "omap2_disp: twl4030_vaux3_ldo_use returns error \n");
+ }
+ else {
+
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ENABLE_VPLL2_DEDICATED,TWL4030_VPLL2_DEDICATED);
+
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ENABLE_VPLL2_DEV_GRP,TWL4030_VPLL2_DEV_GRP);
+
+ mdelay(4);
+ }
+#endif
+}
+
+EXPORT_SYMBOL(omap2_dss_rgb_enable);
+
+
+static void
+lcd_panel_disable(struct work_struct *work)
+{
+#ifdef CONFIG_MACH_OMAP_H4
+ unsigned char expa;
+ int err;
+
+ /* read current state of GPIO EXPA outputs */
+ if ((err = h4_read_gpio_expa(&expa))) {
+ printk(KERN_ERR DRIVER
+ "Error reading GPIO EXPA\n");
+ return;
+ }
+
+ /* Clear GPIO EXPA P7 (LCD_ENVDD) to power-uoff LCD and
+ * clear GPIO EXPA P5 (LCD_ENBKL) to turn off backlight
+ */
+ if ((err = h4_write_gpio_expa(expa & ~0x80))) {
+ printk(KERN_ERR DRIVER
+ "Error writing to GPIO EXPA\n");
+ return;
+ }
+#endif
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 0);
+ /* power to the RGB lines is disabled in omap2_dss_rgb_disable */
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_set_gpio_dataout(LCD_PANEL_ENABLE_GPIO, 0);
+#endif
+}
+
+void
+omap2_dss_rgb_disable(void)
+{
+#ifdef CONFIG_MACH_OMAP_2430SDP
+ twl4030_vaux2_ldo_unuse();
+#else
+ if(is_sil_rev_less_than(OMAP3430_REV_ES2_0)) {
+ if( 0 != twl4030_vaux3_ldo_unuse())
+ printk(KERN_WARNING "omap2_disp:
twl4030_vaux3_ldo_unuse returns error \n");
+ }
+ else {
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ 0x0,TWL4030_VPLL2_DEDICATED);
+
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ 0x0,TWL4030_VPLL2_DEV_GRP);
+ mdelay(4);
+ }
+#endif
+
+}
+EXPORT_SYMBOL(omap2_dss_rgb_disable);
+
+static void
+lcd_backlight_on(struct work_struct *work)
+{
+#ifdef CONFIG_MACH_OMAP_H4
+ unsigned char expa;
+ int err;
+
+ /* read current state of GPIO EXPA outputs */
+ if ((err = h4_read_gpio_expa(&expa))) {
+ printk(KERN_ERR DRIVER
+ "Error reading GPIO EXPA\n");
+ return;
+ }
+
+ /* Set GPIO EXPA P7 (LCD_ENVDD) to power-up LCD and
+ * set GPIO EXPA P5 (LCD_ENBKL) to turn on backlight
+ */
+ if ((err = h4_write_gpio_expa(expa | 0x20))) {
+ printk(KERN_ERR DRIVER
+ "Error writing to GPIO EXPA\n");
+ return;
+ }
+ lcd_backlight_state = LCD_ON;
+#endif
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_set_gpio_dataout(LCD_PANEL_BACKLIGHT_GPIO, 1);
+ lcd_backlight_state = LCD_ON;
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_set_gpio_dataout(LCD_PANEL_BACKLIGHT_GPIO, 1);
+ lcd_backlight_state = LCD_ON;
+#endif
+}
+
+static void
+lcd_backlight_off(struct work_struct *work)
+{
+#ifdef CONFIG_MACH_OMAP_H4
+ unsigned char expa;
+ int err;
+
+ /* read current state of GPIO EXPA outputs */
+ if ((err = h4_read_gpio_expa(&expa))) {
+ printk(KERN_ERR DRIVER
+ "Error reading GPIO EXPA\n");
+ return;
+ }
+
+ /* Clear GPIO EXPA P7 (LCD_ENVDD) to power-uoff LCD and
+ * clear GPIO EXPA P5 (LCD_ENBKL) to turn off backlight
+ */
+ if ((err = h4_write_gpio_expa(expa & ~0x20))) {
+ printk(KERN_ERR DRIVER
+ "Error writing to GPIO EXPA\n");
+ return;
+ }
+ lcd_backlight_state = LCD_OFF;
+#endif
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_set_gpio_dataout(LCD_PANEL_BACKLIGHT_GPIO, 0);
+ lcd_backlight_state = LCD_OFF;
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_set_gpio_dataout(LCD_PANEL_BACKLIGHT_GPIO, 0);
+ lcd_backlight_state = LCD_OFF;
+#endif
+}
+
+void enable_backlight(void)
+{
+ /* If already enabled, return*/
+ if (lcd_in_use)
+ return;
+ if (previous_lcd_backlight_state == LCD_ON) {
+ power_lcd_backlight(LCD_ON);
+#if 0
+ power_lcd_panel(LCD_ON);
+#endif
+ }
+ lcd_in_use = 1;
+}
+EXPORT_SYMBOL(enable_backlight);
+
+void disable_backlight(void)
+{
+ /* If LCD is already disabled, return*/
+ if (!lcd_in_use)
+ return;
+ previous_lcd_backlight_state = lcd_backlight_state;
+ power_lcd_backlight(LCD_OFF);
+#if 0
+ power_lcd_panel(LCD_OFF);
+#endif
+ lcd_in_use = 0;
+}
+EXPORT_SYMBOL(disable_backlight);
+
+static int gpio_reserved = 0;
+
+#ifndef CONFIG_LCD_IOCTL
+static
+#endif
+int omap_lcd_init(struct omap_lcd_info *info)
+{
+#ifdef CONFIG_FB_OMAP_LCD_VGA
+ u32 pixclock = H4_LCD_PIXCLOCK_MAX,/* picoseconds */
+ left_margin = 79, /* pixclocks */
+ right_margin = 89, /* pixclocks */
+ upper_margin = 1, /* line clocks */
+ lower_margin = 0, /* line clocks */
+ hsync_len = 3, /* pixclocks */
+ vsync_len = 2, /* line clocks */
+ sync = 1, /* hsync & vsync polarity */
+ acb = 0x28, /* AC-bias pin frequency */
+ ipc = 1, /* Invert pixel clock */
+ onoff = 1; /* HSYNC/VSYNC Pixel clk Control*/
+#else
+#ifdef CONFIG_OMAP3430_ES2
+ u32 pixclock = H4_LCD_PIXCLOCK_MAX,/* picoseconds */
+ left_margin = 39, /* pixclocks */
+ right_margin = 45, /* pixclocks */
+ upper_margin = 1, /* line clocks */
+ lower_margin = 0, /* line clocks */
+ hsync_len = 3, /* pixclocks */
+ vsync_len = 2, /* line clocks */
+ sync = 1, /* hsync & vsync polarity */
+ acb = 0x28, /* AC-bias pin frequency */
+ ipc = 1, /* Invert pixel clock */
+ onoff = 1; /* HSYNC/VSYNC Pixel clk Control*/
+#else
+ u32 pixclock = H4_LCD_PIXCLOCK_MAX,/* picoseconds */
+ left_margin = 40, /* pixclocks */
+ right_margin = 4, /* pixclocks */
+ upper_margin = 8, /* line clocks */
+ lower_margin = 2, /* line clocks */
+ hsync_len = 4, /* pixclocks */
+ vsync_len = 2, /* line clocks */
+ sync = 0, /* hsync & vsync polarity */
+ acb = 0, /* AC-bias pin frequency */
+ ipc = 0, /* Invert pixel clock */
+ onoff = 0; /* HSYNC/VSYNC Pixel clk Control*/
+
+#endif
+#endif
+ u32 clkdiv;
+
+#ifdef CONFIG_LCD_IOCTL
+ if (info) {
+ pixclock = info->pixclock,
+ left_margin = info->left_margin,
+ right_margin = info->right_margin,
+ upper_margin = info->upper_margin,
+ lower_margin = info->lower_margin,
+ hsync_len = info->hsync_len,
+ vsync_len = info->vsync_len,
+ sync = info->sync,
+ acb = info->acb,
+ ipc = info->ipc,
+ onoff = info->onoff;
+ }
+
+ if (gpio_reserved == 1)
+ goto bypass_gpio;
+#endif
+
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_request_gpio(LCD_PANEL_ENABLE_GPIO); /* LCD panel */
+ omap_request_gpio(LCD_PANEL_BACKLIGHT_GPIO); /* LCD backlight */
+ omap_set_gpio_direction(LCD_PANEL_ENABLE_GPIO, 0); /* output */
+ omap_set_gpio_direction(LCD_PANEL_BACKLIGHT_GPIO, 0); /* output */
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_request_gpio(LCD_PANEL_ENABLE_GPIO); /* LCD panel */
+ twl4030_request_gpio(LCD_PANEL_BACKLIGHT_GPIO); /* LCD backlight */
+ twl4030_set_gpio_direction(LCD_PANEL_ENABLE_GPIO, 0); /* output */
+ twl4030_set_gpio_direction(LCD_PANEL_BACKLIGHT_GPIO, 0); /* output */
+#endif
+
+#ifdef CONFIG_LCD_IOCTL
+bypass_gpio:
+ gpio_reserved = 1;
+#endif
+ omap2_dss_rgb_enable();
+ omap2_disp_get_dss();
+
+ omap2_disp_set_panel_size(OMAP2_OUTPUT_LCD, H4_LCD_XRES, H4_LCD_YRES);
+
+ /* clkdiv = pixclock / (omap2 dss1 clock period) */
+ clkdiv = pixclock / (1000000000UL/omap24xx_get_dss1_clock());
+ clkdiv /= 1000;
+
+ omap2_disp_config_lcd(clkdiv,
+ left_margin - 1, // hbp
+ right_margin - 1, // hfp
+ hsync_len - 1, // hsw
+ upper_margin, // vbp
+ lower_margin, // vfp
+ vsync_len - 1 // vsw
+ );
+
+ omap2_disp_lcdcfg_polfreq( sync, // horizontal sync active low
+ sync, // vertical sync active low
+ acb, // ACB
+ ipc, // IPC
+ onoff // ONOFF
+ );
+
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ udelay(20);
+ enable_backlight();
+ power_lcd_panel(LCD_ON);
+ omap2_disp_put_dss();
+
+ printk(KERN_DEBUG DRIVER
+ "LCD panel %dx%d\n", H4_LCD_XRES, H4_LCD_YRES);
+ return 0;
+}
+
+static int
+lcd_exit(void)
+{
+ if (!lcd_in_use)
+ return 0;
+
+ omap2_disp_get_dss();
+ omap2_disp_disable_output_dev(OMAP2_OUTPUT_LCD);
+ omap2_disp_put_dss();
+
+#if defined(CONFIG_MACH_OMAP_2430SDP) || defined(CONFIG_MACH_OMAP_3430SDP)
+ omap_free_gpio(LCD_PANEL_ENABLE_GPIO); /* LCD panel */
+ omap_free_gpio(LCD_PANEL_BACKLIGHT_GPIO); /* LCD backlight */
+#elif defined(CONFIG_MACH_OMAP_3430LABRADOR)
+ twl4030_free_gpio(LCD_PANEL_ENABLE_GPIO); /* LCD panel */
+ twl4030_free_gpio(LCD_PANEL_BACKLIGHT_GPIO); /* LCD backlight */
+#endif
+
+ lcd_in_use = 0;
+
+ return 0;
+}
+/*
------------------------------------------------------------------------------
*/
+/* Power and device Management */
+
+static int __init
+lcd_probe(struct platform_device *odev)
+{
+ return omap_lcd_init(0);
+}
+
+#ifdef CONFIG_PM
+static int lcd_suspend(struct platform_device *odev, pm_message_t state);
+static int lcd_resume(struct platform_device *odev);
+#endif
+
+static struct platform_driver omap2_lcd_driver = {
+ .driver = {
+ .name = OMAP2_LCD_DRIVER,
+ },
+ .probe = lcd_probe,
+#ifdef CONFIG_PM
+ .suspend = lcd_suspend,
+ .resume = lcd_resume,
+#endif
+};
+
+static struct platform_device lcd_device = {
+ .name = OMAP24xx_LCD_DEVICE,
+ .id = 9,
+};
+
+#ifdef CONFIG_PM
+static int
+lcd_suspend(struct platform_device *odev, pm_message_t state)
+{
+ if (!lcd_in_use)
+ return 0;
+ disable_backlight();
+ omap2_dss_rgb_disable();
+
+ return 0;
+}
+
+static int
+lcd_resume(struct platform_device *odev)
+{
+ if (lcd_in_use)
+ return 0;
+ omap2_dss_rgb_enable();
+ udelay(20);
+ enable_backlight();
+
+ return 0;
+}
+
+#endif /* CONFIG_PM */
+#endif /* CONFIG_OMAP2_LCD */
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef CONFIG_OMAP2_TV
+
+static int tv_in_use;
+
+static void h4_i2c_tvout_off(struct work_struct *work);
+static void h4_i2c_tvout_on(struct work_struct *work);
+
+DECLARE_WORK(h4_tvout_on, h4_i2c_tvout_on);
+DECLARE_WORK(h4_tvout_off, h4_i2c_tvout_off);
+
+static void
+power_tv(int level)
+{
+ switch(level) {
+ case TV_OFF:
+ if(!in_interrupt())
+ h4_i2c_tvout_off(NULL);
+ else
+ schedule_work(&h4_tvout_off);
+ break;
+ default:
+ if(!in_interrupt())
+ h4_i2c_tvout_on(NULL);
+ else
+ schedule_work(&h4_tvout_on);
+ break;
+ }
+}
+
+static void
+h4_i2c_tvout_off(struct work_struct *work)
+{
+#if defined (CONFIG_MACH_OMAP_H4) || defined (CONFIG_TWL4030_CORE_M1)
+ struct i2c_adapter *adap;
+ int err;
+ struct i2c_msg msg[1];
+ unsigned char data[2];
+ /*
+ * Turn OFF TV block (AVDD and VREF) in menelaus chip
+ * MENELAUS_LDO_CTRL8 (0x11 -> 0x03)
+ */
+ adap = i2c_get_adapter(MENELAUS_I2C_ADAP_ID);
+ if (!adap) {
+ printk(KERN_ERR DRIVER
+ "Unable to get I2C adapter \n");
+ }
+ msg->addr = 0x72;/* I2C address of Menelaus Chip */
+ msg->flags = 0;
+ msg->len = 2;
+ msg->buf = data;
+ data[0] = 0x11; /* LD0_CTRL8 */
+ data[1] = 0x00; /* Disable bits for the 0.5V reference LDO */
+ err = i2c_transfer(adap, msg, 1);
+ if (err > 2) {
+ printk(KERN_ERR DRIVER
+ "Disabling TV block through Menelaus failed %d\n",err);
+ }
+#endif
+#if defined CONFIG_OMAP2_TV
+ omap2_disp_get_all_clks();
+ omap2_disp_set_tvref(TVREF_OFF);
+ omap2_disp_put_all_clks();
+#endif
+
+#if defined(CONFIG_TWL4030_CORE_T2) && defined(CONFIG_I2C_TWL4030_CORE)
+ omap2_disp_get_all_clks();
+ omap2_disp_set_tvref(TVREF_OFF);
+ omap2_disp_put_all_clks();
+ twl4030_i2c_write_u8
(TWL4030_MODULE_PM_RECEIVER,0x00,TWL4030_VDAC_DEDICATED);
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,0x00,TWL4030_VDAC_DEV_GRP);
+#endif
+}
+
+static void
+h4_i2c_tvout_on(struct work_struct *work)
+{
+#if defined (CONFIG_MACH_OMAP_H4) || defined (CONFIG_TWL4030_CORE_M1)
+ struct i2c_adapter *adap;
+ int err;
+ struct i2c_msg msg[1];
+ unsigned char data[2];
+
+ /*
+ * Turn ON TV block (AVDD and VREF) in menelaus chip
+ * MENELAUS_LDO_CTRL8 (0x11 -> 0x03)
+ */
+ adap = i2c_get_adapter(MENELAUS_I2C_ADAP_ID);
+ if (!adap) {
+ printk(KERN_ERR DRIVER
+ "Unable to get I2C adapter \n");
+ }
+ msg->addr = 0x72;/* I2C address of Menelaus Chip */
+ msg->flags = 0;
+ msg->len = 2;
+ msg->buf = data;
+ data[0] = 0x11; /* LD0_CTRL8 */
+ data[1] = 0x03; /* Enable bits for the 0.5V reference
+ * and the VADAC LDO
+ */
+ err = i2c_transfer(adap, msg, 1);
+ if (err > 2) {
+ printk(KERN_ERR DRIVER
+ "Enabling TV block through Menelaus failed %d\n",err);
+ }
+#endif
+#if defined (CONFIG_OMAP2_TV)
+ omap2_disp_get_all_clks();
+ omap2_disp_set_tvref(TVREF_ON);
+ omap2_disp_put_all_clks();
+#endif
+#if defined(CONFIG_TWL4030_CORE_T2) && defined(CONFIG_I2C_TWL4030_CORE)
+ omap2_disp_get_all_clks();
+ omap2_disp_set_tvref(TVREF_ON);
+ omap2_disp_put_all_clks();
+
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ENABLE_VDAC_DEDICATED,TWL4030_VDAC_DEDICATED);
+ twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+ ENABLE_VDAC_DEV_GRP,TWL4030_VDAC_DEV_GRP);
+#endif
+}
+
+static int
+tv_init(void)
+{
+ omap2_disp_get_all_clks();
+ power_tv(TV_ON);
+ omap2_disp_set_tvstandard(NTSC_M);
+ omap2_disp_set_panel_size(OMAP2_OUTPUT_TV, H4_TV_XRES, H4_TV_YRES);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+ omap2_disp_put_all_clks();
+ printk(KERN_DEBUG DRIVER
+ "TV %dx%d interlaced\n", H4_TV_XRES, H4_TV_YRES);
+ tv_in_use = 1;
+ return 0;
+}
+
+static int
+tv_exit(void)
+{
+ if (!tv_in_use)
+ return 0;
+
+ omap2_disp_get_all_clks();
+ omap2_disp_disable_output_dev(OMAP2_OUTPUT_TV);
+ power_tv(TV_OFF);
+ omap2_disp_put_all_clks();
+ tv_in_use = 0;
+ return 0;
+}
+
+static int __init tv_probe(struct platform_device *odev);
+#ifdef CONFIG_PM
+static int tv_suspend(struct platform_device *odev, pm_message_t state);
+static int tv_resume(struct platform_device *odev);
+#endif
+
+static struct platform_driver omap2_tv_driver = {
+ .driver = {
+ .name = OMAP2_TV_DRIVER,
+ },
+ .probe = tv_probe,
+#ifdef CONFIG_PM
+ .suspend = tv_suspend,
+ .resume = tv_resume,
+#endif
+};
+
+static struct platform_device tv_device = {
+ .name = OMAP24xx_TV_DEVICE,
+ .id = 10,
+};
+
+static int __init
+tv_probe(struct platform_device *odev)
+{
+ return tv_init();
+}
+
+#ifdef CONFIG_PM
+static int
+tv_suspend(struct platform_device *odev, pm_message_t state)
+{
+ if (!tv_in_use)
+ return 0;
+
+ /* TODO-- need to delink DSS and TV clocks.. For now, TV is put to
+ * off in fb_blank and put_dss */
+
+ tv_in_use = 0;
+ return 0;
+}
+
+static int
+tv_resume(struct platform_device *odev)
+{
+ if (tv_in_use)
+ return 0;
+
+ /* TODO-- need to delink DSS and TV clocks.. For now, TV is put to
+ * on in fb_blank and get_dss */
+ tv_in_use = 1;
+ return 0;
+}
+
+#endif /* CONFIG_PM */
+
+#endif /* CONFIG_OMAP2_TV */
+
+/*---------------------------------------------------------------------------*/
+/* Sysfs support */
+
+struct board_properties {
+ struct module *owner;
+};
+static struct board_properties *bd;
+
+struct dispc_device {
+ struct board_properties *props;
+ struct device class_dev;
+};
+static struct dispc_device *new_bd;
+
+
+static void dispc_class_release(struct class *dev)
+{
+ if(new_bd != NULL) kfree(new_bd);
+ if(bd != NULL) kfree(bd);
+}
+
+struct class dispc_class = {
+ .name = "display_control",
+ .class_release = dispc_class_release,
+};
+
+static ssize_t
+read_layer_out(char *buf, int layer)
+{
+ int p = 0;
+ int output_dev = omap2_disp_get_output_dev(layer);
+
+ switch (output_dev) {
+ case OMAP2_OUTPUT_LCD : p = sprintf(buf, "lcd\n");
+ break;
+ case OMAP2_OUTPUT_TV : p = sprintf(buf, "tv\n");
+ break;
+ }
+ return(p);
+}
+
+static ssize_t
+write_layer_out(const char *buffer, size_t count,int layer)
+{
+ int out_dev;
+ if (!buffer || (count == 0))
+ return 0;
+
+ /* only 'lcd' or 'tv' are valid inputs */
+ if (strncmp(buffer, "lcd", 3) == 0)
+ out_dev = OMAP2_OUTPUT_LCD;
+#ifdef CONFIG_OMAP2_TV
+ else if (strncmp(buffer, "tv", 2) == 0)
+ out_dev = OMAP2_OUTPUT_TV;
+#endif
+ else
+ return -EINVAL;
+
+ omap2_disp_get_all_clks();
+
+ if (fb_out_layer != OMAP2_GRAPHICS)
+ {
+ omap2_disp_disable_layer(fb_out_layer);
+ omap2_disp_release_layer (fb_out_layer);
+ }
+ mdelay(1);
+ omap2_disp_set_output_dev(layer, out_dev);
+ mdelay(1);
+
+ if(fb_out_layer != OMAP2_GRAPHICS)
+ omap24xxfb_set_output_layer(fb_out_layer);
+ omap2_disp_put_all_clks();
+ return count;
+}
+
+static ssize_t
+graphics_show(struct device *cdev, struct device_attribute *attr, char *buf)
+{
+ return(read_layer_out(buf,OMAP2_GRAPHICS));
+}
+
+static ssize_t
+graphics_store(struct device *cdev, struct device_attribute *attr, const char
*buffer, size_t count)
+{
+ return(write_layer_out(buffer,count,OMAP2_GRAPHICS));
+}
+
+static ssize_t
+video1_show(struct device *cdev, struct device_attribute *attr, char *buf)
+{
+ return(read_layer_out(buf,OMAP2_VIDEO1));
+}
+
+static ssize_t
+video1_store(struct device *cdev, struct device_attribute *attr, const char
*buffer, size_t count)
+{
+ return(write_layer_out(buffer,count,OMAP2_VIDEO1));
+}
+
+static ssize_t
+video2_show(struct device *cdev, struct device_attribute *attr, char *buf)
+{
+ return(read_layer_out(buf,OMAP2_VIDEO2));
+}
+
+static ssize_t
+video2_store(struct device *cdev, struct device_attribute *attr, const char
*buffer, size_t count)
+{
+ return(write_layer_out(buffer,count,OMAP2_VIDEO2));
+}
+
+static ssize_t
+lcdbacklight_show(struct device *cdev, struct device_attribute *attr, char
*buf)
+{
+ int p =0;
+
+ switch (lcd_backlight_state) {
+ case LCD_ON: p = sprintf(buf, "on\n");
+ break;
+ case LCD_OFF: p = sprintf(buf, "off\n");
+ break;
+ }
+ return p;
+}
+
+static ssize_t
+lcdbacklight_store(struct device *cdev, struct device_attribute *attr, const
char *buffer, size_t count)
+{
+ /*
+ * If the LCD is already in suspend state do not accept any changes to
+ * backlight
+ */
+
+ if (!lcd_in_use)
+ return -EINVAL;
+
+ if (!buffer || (count == 0))
+ return 0;
+
+ if (strncmp(buffer,"on",2) == 0){
+ power_lcd_backlight(LCD_ON);
+ }
+ else if (strncmp(buffer, "off", 3) == 0){
+ power_lcd_backlight(LCD_OFF);
+ }
+ else{
+ return -EINVAL;
+ }
+ return count;
+}
+
+static ssize_t
+lcd_data_lines_show(struct device *cdev, struct device_attribute *attr, char
*buf)
+{
+ int p =0;
+ int current_lcddatalines_state;
+
+ current_lcddatalines_state = omap2_disp_get_lcddatalines();
+
+ switch (current_lcddatalines_state) {
+ case LCD_DATA_LINE_18BIT: p = sprintf(buf, "18 bits\n");
+ break;
+ case LCD_DATA_LINE_16BIT: p = sprintf(buf, "16 bits\n");
+ break;
+ }
+ return (p);
+}
+
+static ssize_t
+lcd_data_lines_store(struct device *cdev, struct device_attribute *attr,
const char *buffer, size_t count)
+{
+ int no_of_data_lines;
+
+ if (!buffer || (count == 0))
+ return 0;
+
+ if (strncmp(buffer,"18",2) == 0)
+ no_of_data_lines = LCD_DATA_LINE_18BIT;
+ else if (strncmp(buffer, "16", 2) == 0)
+ no_of_data_lines = LCD_DATA_LINE_16BIT;
+ else
+ return -EINVAL;
+
+ omap2_disp_set_lcddatalines(no_of_data_lines);
+ return count;
+}
+
+static ssize_t
+dithering_show(struct device *cdev, struct device_attribute *attr, char *buf)
+{
+ int p=0;
+ int current_dither_state;
+
+ omap2_disp_get_dss();
+ current_dither_state = omap2_disp_get_dithering();
+ switch (current_dither_state) {
+ case DITHERING_ON: p = sprintf(buf, "on\n");
+ break;
+ case DITHERING_OFF: p = sprintf(buf, "off\n");
+ break;
+ }
+ omap2_disp_put_dss();
+ return p;
+}
+
+static ssize_t
+dithering_store(struct device *cdev, struct device_attribute *attr, const
char *buffer, size_t count)
+{
+ int dither_state;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+ if (strncmp(buffer,"on",2) == 0){
+ dither_state = DITHERING_ON;
+ }
+ else if (strncmp(buffer, "off", 3) == 0){
+ dither_state = DITHERING_OFF;
+ }
+ else
+ return -EINVAL;
+ omap2_disp_get_dss();
+ omap2_disp_set_dithering(dither_state);
+ omap2_disp_put_dss();
+ return count;
+}
+
+
+#ifdef CONFIG_ARCH_OMAP34XX
+static ssize_t
+lcd_alphablend_show(struct device *cdev, struct device_attribute *attr, char
*buf)
+{
+ int p=0;
+ int alphablend_state;
+
+ omap2_disp_get_dss();
+ alphablend_state = omap2_disp_get_alphablend(OMAP2_OUTPUT_LCD);
+ switch (alphablend_state) {
+ case 0: p = sprintf(buf, "off\n");
+ break;
+ case 1: p = sprintf(buf, "on\n");
+ break;
+ }
+ omap2_disp_put_dss();
+ return p;
+}
+
+static ssize_t
+lcd_alphablend_store(struct device *cdev, struct device_attribute *attr,
const char *buffer, size_t count)
+{
+ int alpha_state;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+ if (strncmp(buffer,"on",2) == 0){
+ alpha_state = 1;
+ }
+ else if (strncmp(buffer, "off", 3) == 0){
+ alpha_state = 0;
+ }
+ else
+ return -EINVAL;
+ omap2_disp_get_dss();
+ omap2_disp_set_alphablend(OMAP2_OUTPUT_LCD,alpha_state);
+ omap2_disp_put_dss();
+ return count;
+}
+
+static ssize_t
+tv_alphablend_show(struct device *cdev, struct device_attribute *attr, char
*buf)
+{
+ int p=0;
+ int alphablend_state;
+
+ omap2_disp_get_dss();
+ alphablend_state = omap2_disp_get_alphablend(OMAP2_OUTPUT_TV);
+ switch (alphablend_state) {
+ case 0: p = sprintf(buf, "off\n");
+ break;
+ case 1: p = sprintf(buf, "on\n");
+ break;
+ }
+ omap2_disp_put_dss();
+ return p;
+}
+
+static ssize_t
+tv_alphablend_store(struct device *cdev, struct device_attribute *attr, const
char *buffer, size_t count)
+{
+ int alpha_state;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+ if (strncmp(buffer,"on",2) == 0){
+ alpha_state = 1;
+ }
+ else if (strncmp(buffer, "off", 3) == 0){
+ alpha_state = 0;
+ }
+ else
+ return -EINVAL;
+ omap2_disp_get_dss();
+ omap2_disp_set_alphablend(OMAP2_OUTPUT_TV,alpha_state);
+ omap2_disp_put_dss();
+ return count;
+}
+static ssize_t
+gfx_global_alpha_show(struct device *cdev, struct device_attribute *attr,
char *buf)
+{
+ int p=0;
+ unsigned char alphablend_value;
+
+ omap2_disp_get_dss();
+ alphablend_value = omap2_disp_get_global_alphablend_value(OMAP2_GRAPHICS);
+ p= sprintf(buf, "%d \n",alphablend_value);
+ omap2_disp_put_dss();
+ return p;
+}
+
+static ssize_t
+gfx_global_alpha_store(struct device *cdev, struct device_attribute *attr,
const char *buffer, size_t count)
+{
+ unsigned char alpha_value;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+
+ if (sscanf(buffer,"%hhu",&alpha_value) != 1) {
+ printk(KERN_ERR "gfx_global_alpha_store: Invalid value \n");
+ return -EINVAL;
+ }
+
+ omap2_disp_get_dss();
+ omap2_disp_set_global_alphablend_value(OMAP2_GRAPHICS,alpha_value);
+ omap2_disp_put_dss();
+ return count;
+}
+
+
+static ssize_t
+vid2_global_alpha_show(struct device *cdev, struct device_attribute *attr,
char *buf)
+{
+ int p=0;
+ int alphablend_value;
+
+ omap2_disp_get_dss();
+ alphablend_value = omap2_disp_get_global_alphablend_value(OMAP2_VIDEO2);
+ p= sprintf(buf, "%d \n",alphablend_value);
+ omap2_disp_put_dss();
+ return p;
+}
+
+static ssize_t
+vid2_global_alpha_store(struct device *cdev, struct device_attribute *attr,
const char *buffer, size_t count)
+{
+ int alpha_value;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+
+ if (sscanf(buffer,"%d",&alpha_value) != 1) {
+ printk(KERN_ERR "gfx_global_alpha_store: Invalid value \n");
+ return -EINVAL;
+ }
+
+ omap2_disp_get_dss();
+ omap2_disp_set_global_alphablend_value(OMAP2_VIDEO2,alpha_value);
+ omap2_disp_put_dss();
+ return count;
+}
+
+
+static ssize_t lpr_show(struct device *cdev, struct device_attribute *attr,
char *buf)
+{
+ int p = 0;
+
+ switch (lpr_enabled) {
+ case 0: p = sprintf(buf, "disable\n");
+ break;
+
+ case 1: p = sprintf(buf, "enable\n");
+ break;
+ }
+ return p;
+}
+
+static ssize_t lpr_store(struct device *cdev, struct device_attribute *attr,
const char *buffer,
+ size_t count)
+{
+ int rc;
+
+ if (!buffer || (count == 0))
+ return 0;
+
+ if (strncmp(buffer, "enable", 6) == 0) {
+ if ((rc = omap2_disp_lpr_enable())) {
+ printk("can't enable lpr!\n");
+ return rc;
+ }
+ }
+ else if (strncmp(buffer, "disable", 7) == 0) {
+ if ((rc = omap2_disp_lpr_disable())) {
+ printk("can't disable lpr!\n");
+ return rc;
+ }
+ }
+ else {
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+static ssize_t gfx_fifo_low_threshold_show(struct device *cdev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int thrs;
+
+ omap2_disp_get_dss();
+ thrs = omap2_disp_get_gfx_fifo_low_threshold();
+ omap2_disp_put_dss();
+
+ return sprintf(buf, "%d\n", thrs);
+}
+
+static ssize_t gfx_fifo_low_threshold_store(struct device *cdev,
+ struct device_attribute *attr, const char *buffer,
+ size_t count)
+{
+ unsigned int v;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+
+ if (sscanf(buffer, "%d", &v) != 1) {
+ printk(KERN_ERR "gfx_fifo_low_threshold: Invalid value\n");
+ return -EINVAL;
+ }
+
+ omap2_disp_get_dss();
+ omap2_disp_set_gfx_fifo_low_threshold(v);
+ omap2_disp_put_dss();
+
+ return count;
+}
+
+static ssize_t gfx_fifo_high_threshold_show(struct device *cdev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int thrs;
+
+ omap2_disp_get_dss();
+ thrs = omap2_disp_get_gfx_fifo_high_threshold();
+ omap2_disp_put_dss();
+
+ return sprintf(buf, "%d\n", thrs);
+}
+
+static ssize_t gfx_fifo_high_threshold_store(struct device *cdev,
+ struct device_attribute *attr, const char *buffer,
+ size_t count)
+{
+ unsigned int v;
+
+ if (!buffer || (count == 0)){
+ return 0;
+ }
+
+ if (sscanf(buffer, "%d", &v) != 1) {
+ printk(KERN_ERR "gfx_fifo_high_threshold: Invalid value\n");
+ return -EINVAL;
+ }
+
+ omap2_disp_get_dss();
+ omap2_disp_set_gfx_fifo_high_threshold(v);
+ omap2_disp_put_dss();
+
+ return count;
+}
+
+
+#endif
+
+#ifdef CONFIG_OMAP2_TV
+static ssize_t
+tv_standard_show(struct device *cdev, struct device_attribute *attr, char
*buf)
+{
+ int p = 0;
+ int current_tvstd;
+
+ omap2_disp_get_dss();
+ current_tvstd = omap2_disp_get_tvstandard();
+
+ switch (current_tvstd) {
+ case PAL_BDGHI: p = sprintf(buf, "pal_bdghi\n");
+ break;
+ case PAL_NC: p = sprintf(buf, "pal_nc\n");
+ break;
+ case PAL_N: p = sprintf(buf, "pal_n\n");
+ break;
+ case PAL_M: p = sprintf(buf, "pal_m\n");
+ break;
+ case PAL_60: p = sprintf(buf, "pal_60\n");
+ break;
+ case NTSC_M: p = sprintf(buf, "ntsc_m\n");
+ break;
+ case NTSC_J: p = sprintf(buf, "ntsc_j\n");
+ break;
+ case NTSC_443: p = sprintf(buf, "ntsc_443\n");
+ break;
+ }
+ omap2_disp_put_dss();
+ return (p);
+}
+
+static ssize_t
+tv_standard_store(struct device *cdev, struct device_attribute *attr, const
char *buffer, size_t count)
+{
+ int tv_std;
+
+ if (!buffer || (count == 0))
+ return 0;
+
+ if (strncmp(buffer, "pal_bdghi", 9) == 0)
+ tv_std = PAL_BDGHI;
+ else if (strncmp(buffer, "pal_nc", 6) == 0)
+ tv_std = PAL_NC;
+ else if (strncmp(buffer, "pal_n", 5) == 0)
+ tv_std = PAL_N;
+ else if (strncmp(buffer, "pal_m", 5) == 0)
+ tv_std = PAL_M;
+ else if (strncmp(buffer, "pal_60", 6) == 0)
+ tv_std = PAL_60;
+ else if (strncmp(buffer, "ntsc_m", 6) == 0)
+ tv_std = NTSC_M;
+ else if (strncmp(buffer, "ntsc_j", 6) == 0)
+ tv_std = NTSC_J;
+ else if (strncmp(buffer, "ntsc_443", 8) == 0)
+ tv_std = NTSC_443;
+ else
+ return -EINVAL;
+ omap2_disp_get_all_clks();
+ omap2_disp_set_tvstandard(tv_std);
+ omap2_disp_put_all_clks();
+ return count;
+
+}
+#endif
+
+#define DECLARE_ATTR(_name,_mode,_show,_store) \
+{ \
+ .attr = { .name = __stringify(_name), .mode = _mode, .owner =
THIS_MODULE }, \
+ .show = _show, \
+ .store = _store, \
+}
+
+static struct device_attribute bl_class_device_attributes[] = {
+ DECLARE_ATTR(dithering, S_IRWXUGO, dithering_show, dithering_store),
+ DECLARE_ATTR(graphics, S_IRWXUGO, graphics_show, graphics_store),
+ DECLARE_ATTR(video1, S_IRWXUGO, video1_show, video1_store),
+ DECLARE_ATTR(video2, S_IRWXUGO, video2_show, video2_store),
+ DECLARE_ATTR(lcdbacklight, S_IRWXUGO, lcdbacklight_show,
lcdbacklight_store),
+ DECLARE_ATTR(lcd_data_lines, S_IRWXUGO, lcd_data_lines_show,
lcd_data_lines_store),
+ DECLARE_ATTR(frame_buffer, S_IRWXUGO, fb_out_show, fb_out_store),
+
+#ifdef CONFIG_ARCH_OMAP34XX
+ DECLARE_ATTR(lcd_alphablend, S_IRWXUGO, lcd_alphablend_show,
lcd_alphablend_store),
+ DECLARE_ATTR(tv_alphablend, S_IRWXUGO, tv_alphablend_show,
tv_alphablend_store),
+ DECLARE_ATTR(gfx_global_alpha, S_IRWXUGO, gfx_global_alpha_show,
gfx_global_alpha_store),
+ DECLARE_ATTR(vid2_global_alpha, S_IRWXUGO, vid2_global_alpha_show,
vid2_global_alpha_store),
+ DECLARE_ATTR(lpr, S_IRWXUGO, lpr_show, lpr_store),
+ DECLARE_ATTR(gfx_fifo_low_threshold, S_IRWXUGO,
+ gfx_fifo_low_threshold_show,
+ gfx_fifo_low_threshold_store),
+ DECLARE_ATTR(gfx_fifo_high_threshold, S_IRWXUGO,
+ gfx_fifo_high_threshold_show,
+ gfx_fifo_high_threshold_store),
+#endif
+ #ifdef CONFIG_OMAP2_TV
+ DECLARE_ATTR(tv_standard, 0644, tv_standard_show, tv_standard_store),
+ #endif
+};
+
+static int
+create_sysfs_files(void)
+{
+
+ int rc=0,i,ret;
+
+ if((ret = class_register(&dispc_class)) != 0 )
+ return ret;
+
+ bd = kmalloc(sizeof(struct board_properties), GFP_KERNEL);
+ if (unlikely(!bd))
+ return -ENOMEM;
+
+ bd->owner = THIS_MODULE;
+ new_bd = kmalloc(sizeof(struct dispc_device), GFP_KERNEL);
+ if (unlikely(!new_bd))
+ return -ENOMEM;
+
+ new_bd->props = bd;
+ memset(&new_bd->class_dev, 0, sizeof(new_bd->class_dev));
+ new_bd->class_dev.class = &dispc_class;
+ strlcpy(new_bd->class_dev.bus_id, "omap_disp_control", KOBJ_NAME_LEN);
+ rc = device_register(&new_bd->class_dev);
+
+ if (unlikely(rc)) {
+ kfree(new_bd);
+ return -EPERM;
+ }
+ for (i = 0; i < ARRAY_SIZE(bl_class_device_attributes); i++) {
+ rc = device_create_file(&new_bd->class_dev,
&bl_class_device_attributes[i]);
+ if (unlikely(rc)) {
+ while (--i >= 0){
+ device_remove_file(&new_bd->class_dev,
+ &bl_class_device_attributes[i]);
+ }
+ device_unregister(&new_bd->class_dev);
+ /* No need to kfree(new_bd) since release() method does it for us*/
+ return -EPERM;
+ }
+ }
+ return 0;
+}
+
+static void
+remove_sysfs_files(void)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(bl_class_device_attributes); i++) {
+ device_remove_file(&new_bd->class_dev,
+ &bl_class_device_attributes[i]);
+ }
+ device_unregister(&new_bd->class_dev);
+}
+
+static int __init
+omap2_dispout_init(void)
+{
+ if (create_sysfs_files() < 0) {
+ printk(KERN_ERR DRIVER
+ "Could not create sysfs files for display control\n");
+ return -ENODEV;
+ }
+
+#ifdef CONFIG_OMAP2_LCD
+ /* Register the driver with LDM */
+ if (platform_driver_register(&omap2_lcd_driver)) {
+ printk(KERN_ERR DRIVER ": failed to register omap2_lcd driver\n");
+ return -ENODEV;
+ }
+
+ /* Register the device with LDM */
+ if (platform_device_register(&lcd_device)) {
+ printk(KERN_ERR DRIVER ": failed to register lcd device\n");
+ platform_driver_unregister(&omap2_lcd_driver);
+ return -ENODEV;
+ }
+#endif
+
+#ifdef CONFIG_OMAP2_TV
+ /* Register the driver with LDM */
+ if (platform_driver_register(&omap2_tv_driver)) {
+ printk(KERN_ERR DRIVER ": failed to register omap2_tv driver\n");
+ return -ENODEV;
+ }
+
+ /* Register the device with LDM */
+ if (platform_device_register(&tv_device)) {
+ printk(KERN_ERR DRIVER ": failed to register tv device\n");
+ platform_driver_unregister(&omap2_tv_driver);
+ return -ENODEV;
+ }
+#endif
+
+ return 0;
+
+}
+device_initcall(omap2_dispout_init);
+
+static void __exit
+omap2_dispout_exit(void)
+{
+ remove_sysfs_files();
+
+#ifdef CONFIG_OMAP2_LCD
+ lcd_exit();
+ platform_device_unregister(&lcd_device);
+ platform_driver_unregister(&omap2_lcd_driver);
+#endif
+
+#ifdef CONFIG_OMAP2_TV
+ tv_exit();
+ platform_device_unregister(&tv_device);
+ platform_driver_unregister(&omap2_tv_driver);
+#endif
+}
+module_exit(omap2_dispout_exit);
+
+
+/*---------------------------------------------------------------------------*/
+/* Framebuffer related */
+
+/* We're intializing the virtual framebuffer dimensions to
+ * (H4_XRES, H4_YRES*3) in order to support triple buffering. The
+ * onscreen framebuffer can be flipped via the panning ioctl by specifying
+ * offsets of (0, 0), (0, H4_YRES), or (0, 2*H4_YRES).
+ */
+
+static struct fb_var_screeninfo h4_lcd_var = {
+ .xres = H4_LCD_XRES,
+ .yres = H4_LCD_YRES,
+ .xres_virtual = H4_LCD_XRES,
+ .yres_virtual = H4_LCD_YRES*3,
+ .xoffset = 0,
+ .yoffset = 0,
+ .bits_per_pixel = 16,
+ .grayscale = 0,
+ .red = {11, 5, 0},
+ .green = { 5, 6, 0},
+ .blue = { 0, 5, 0},
+ .transp = { 0, 0, 0},
+ .nonstd = 0,
+ .activate = FB_ACTIVATE_NOW,
+ .height = -1,
+ .width = -1,
+ .accel_flags = 0,
+ .pixclock = H4_LCD_PIXCLOCK_MAX,/* picoseconds */
+ .left_margin = 40, /* pixclocks */
+ .right_margin = 4, /* pixclocks */
+ .upper_margin = 8, /* line clocks */
+ .lower_margin = 2, /* line clocks */
+ .hsync_len = 4, /* pixclocks */
+ .vsync_len = 2, /* line clocks */
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .rotate = 0,
+ .reserved[0] = 0,
+};
+
+static struct fb_var_screeninfo ntsc_tv_var = {
+/* NTSC frame size is 720 * 480,
+ * but due to overscan, about 640 x 430 is visible
+ */
+ .xres = 640,
+ .yres = 430,
+ .xres_virtual = 720,
+ .yres_virtual = 480 * 3,
+ .xoffset = 0,
+ .yoffset = 0,
+ .bits_per_pixel = 16,
+ .grayscale = 0,
+ .red = {11, 5, 0},
+ .green = { 5, 6, 0},
+ .blue = { 0, 5, 0},
+ .transp = { 0, 0, 0},
+ .nonstd = 0,
+ .activate = FB_ACTIVATE_NOW,
+ .height = -1,
+ .width = -1,
+ .accel_flags = 0,
+ .pixclock = 0, /* picoseconds */
+ .left_margin = 0, /* pixclocks */
+ .right_margin = 0, /* pixclocks */
+ .upper_margin = 0, /* line clocks */
+ .lower_margin = 0, /* line clocks */
+ .hsync_len = 0, /* pixclocks */
+ .vsync_len = 0, /* line clocks */
+ .sync = 0,
+ .vmode = FB_VMODE_INTERLACED,
+ .rotate = 0,
+ .reserved[0] = 0,
+};
+
+static struct fb_var_screeninfo pal_tv_var = {
+/* PAL frame size is 720 * 546,
+ * but due to overscan, about 640 x 520 is visible
+ */
+ .xres = 640,
+ .yres = 480,
+ .xres_virtual = 720,
+ .yres_virtual = 576 * 3,
+ .xoffset = 0,
+ .yoffset = 0,
+ .bits_per_pixel = 16,
+ .grayscale = 0,
+ .red = {11, 5, 0},
+ .green = { 5, 6, 0},
+ .blue = { 0, 5, 0},
+ .transp = { 0, 0, 0},
+ .nonstd = 0,
+ .activate = FB_ACTIVATE_NOW,
+ .height = -1,
+ .width = -1,
+ .accel_flags = 0,
+ .pixclock = 0, /* picoseconds */
+ .left_margin = 0, /* pixclocks */
+ .right_margin = 0, /* pixclocks */
+ .upper_margin = 0, /* line clocks */
+ .lower_margin = 0, /* line clocks */
+ .hsync_len = 0, /* pixclocks */
+ .vsync_len = 0, /* line clocks */
+ .sync = 0,
+ .vmode = FB_VMODE_INTERLACED,
+ .rotate = 0,
+ .reserved[0] = 0,
+};
+
+
+void
+get_panel_default_var(struct fb_var_screeninfo *var, int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ memcpy((struct fb_var_screeninfo *) var,
+ &h4_lcd_var, sizeof(*var));
+ }
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ int tv = omap2_disp_get_tvstandard();
+ if(tv == PAL_BDGHI ||
+ tv == PAL_NC ||
+ tv == PAL_N ||
+ tv == PAL_M ||
+ tv == PAL_60){
+ memcpy((struct fb_var_screeninfo *) var,
+ &pal_tv_var, sizeof(*var));
+ }else {
+ memcpy((struct fb_var_screeninfo *) var,
+ &ntsc_tv_var, sizeof(*var));
+ }
+ }
+}
+
+u32
+get_panel_pixclock_max(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ return H4_LCD_PIXCLOCK_MAX;
+ }
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ return ~0;
+ }
+
+ return -EINVAL;
+}
+
+u32
+get_panel_pixclock_min(int output_dev)
+{
+ if (output_dev == OMAP2_OUTPUT_LCD) {
+ return H4_LCD_PIXCLOCK_MIN;
+ }
+ else if (output_dev == OMAP2_OUTPUT_TV) {
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+EXPORT_SYMBOL(get_panel_default_var);
+EXPORT_SYMBOL(get_panel_pixclock_max);
+EXPORT_SYMBOL(get_panel_pixclock_min);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/omap/omap_fb.c b/drivers/video/omap/omap_fb.c
new file mode 100644
index 0000000..d864214
--- /dev/null
+++ b/drivers/video/omap/omap_fb.c
@@ -0,0 +1,2285 @@
+/*
+ * drivers/video/omap24xxfb.c
+ *
+ * Framebuffer driver for OMAP24xx display controller.
+ *
+ * Copyright (C) 2004-2005-2006 Texas Instruments, Inc.
+ *
+ * Author: Andy Lowe (sou...@mvista.com)
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/ioport.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/smp_lock.h>
+#include <linux/interrupt.h>
+#include <linux/console.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <asm/irq.h>
+// #include <asm/arch/bus.h>
+#include <asm/arch/clock.h>
+#include <asm/uaccess.h>
+
+#ifdef CONFIG_PM
+#define PM_DEBUG 1
+#include <linux/notifier.h>
+#include <linux/pm.h>
+#endif
+
+#ifdef CONFIG_DPM
+#include <linux/dpm.h>
+#endif
+
+#include <asm/arch/display.h>
+#include "omap_fb.h"
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBGENTER printk(KERN_INFO "%s: Enter\n", __FUNCTION__);
+#define DBGENTER_c printk(KERN_INFO "%s: Enter, con=%d\n", __FUNCTION__,
con);
+#define DBGLEAVE printk(KERN_INFO "%s: Exit\n", __FUNCTION__);
+#else
+#define DBGENTER
+#define DBGLEAVE
+#define DBGENTER_c
+#endif
+
+#define OMAPFB_DEVICE "omap24xxfb"
+#define OMAPFB_DRIVER "omap24xxfb"
+#define FB_NAME "omap24xxfb" /* 16 chars max */
+
+#define SCHEDULE_WAIT 0
+#define BUSY_WAIT 1
+
+/* To use the rotation feature, include this in your boot params:
+ video=omap24xxfb:rotation=[0|90|180|270]
+*/
+
+int omap24xxfb_rotation = -1; // -1 = no rotation support
+int omap24xxfb_mirroring = 0; // the status of mirroring
+
+#define omap_rotation_index(rotation_deg) \
+ (rotation_deg == 90)?(270/90): \
+ (rotation_deg == 270)?(90/90): \
+ (rotation_deg == 180)?(180/90): \
+ (0/90)
+
+#define omap_rot_mirror_index(rotation_deg) \
+ (rotation_deg == 90)?(90/90): \
+ (rotation_deg == 270)?(270/90): \
+ (rotation_deg == 180)?(0/90): \
+ (180/90)
+
+struct omap24xxfb_info {
+ /* The fb_info structure must be first! */
+ struct fb_info info;
+
+ dma_addr_t mmio_base_phys;
+ dma_addr_t fb_base_phys;
+ unsigned long fb_size;
+ unsigned long mmio_base;
+ unsigned long fb_base;
+
+ wait_queue_head_t vsync_wait;
+ unsigned long vsync_cnt;
+
+ u32 pseudo_palette[17];
+ u32 *palette;
+ dma_addr_t palette_phys;
+
+ /* Period of the graphics clock in picoseconds.
+ * This is is the input to the pixel clock divider.
+ */
+ unsigned long gfx_clk_period;
+ unsigned int hsync; /* horizontal sync frequency in Hz */
+ unsigned int vsync; /* vertical sync frequency in Hz */
+ unsigned long timeout; /* register update timeout period in ticks */
+
+ int alloc_fb_mem;
+ int asleep;
+ int blanked;
+
+ int rotation_support;
+ int rotation_deg;
+ dma_addr_t sms_rot_phy[4];
+ unsigned long sms_rot_virt[4];
+ unsigned long vrfb_size;
+};
+
+static struct omap24xxfb_info *saved_oinfo;
+static struct fb_var_screeninfo default_var;
+
+int fb_out_layer = OMAP2_GRAPHICS;
+extern void get_panel_default_var(struct fb_var_screeninfo *var, int
output_dev);
+extern u32 get_panel_pixclock_max(int output_dev);
+extern u32 get_panel_pixclock_min(int output_dev);
+extern void enable_backlight(void);
+extern void disable_backlight(void);
+int omap24xx_get_dss1_clock(void);
+extern int omap24xxfb_set_output_layer(int layer);
+
+
+#ifdef CONFIG_TRACK_RESOURCES
+/* device name needed for resource tracking layer */
+struct device_driver omap_fb_drv = {
+ .name = "omap_fb",
+};
+
+struct device omap_fb_dev = {
+ .driver = &omap_fb_drv,
+};
+#endif
+
+/******************************************************************************/
+/* Platform-specific customization for the framebuffer driver.
+ */
+
+/* omap24xxfb_gfx_clk_period() must return the period (in picoseconds) of the
+ * graphics timebase clock. This clock is the input to the pixel clock
+ * divider.
+ *
+ * prototype:
+ * unsigned long omap24xxfb_gfx_clk_period(void);
+ */
+#define omap24xxfb_gfx_clk_period()
(1000000000UL/(omap24xx_get_dss1_clock()/1000))
+
+/* omap24xxfb_fb_base() must return the physical base address of the
+ * framebuffer. If the address is non-zero, then the framebuffer memory is
+ * ioremap'd. If the address is zero, then the framebuffer memory is
+ * dynamically allocated by the driver.
+ *
+ * prototype:
+ * unsigned long omap24xxfb_fb_base(void);
+ */
+#define omap24xxfb_fb_base() 0
+
+/* omap24xxfb_fb_size() must return the size of the framebuffer in bytes.
+ * The framebuffer is only ioremap'd (or kmalloc'd) at driver initialization
+ * time. It does not change when the video mode (resolution and color depth)
+ * changes, so it must be large enough for all video modes that are to be
+ * supported.
+ *
+ * In non-rotation mode, we're allocating a framebuffer 3 times the size of
+ * the physical display. This is to support triple buffering. The panning
ioctl
+ * can be used to switch between the three different framebuffer regions, so
+ * you effectively have an onscreen framebuffer and two offscreen
framebuffers.
+ *
+ * prototype:
+ * unsigned long omap24xxfb_fb_size(void);
+ */
+#define omap24xxfb_fb_size(rotation) \
+ rotation ? (2048 * 576 * (16/8)) : (720 * 576 * (16/8) * 3)
+/* 720 x 576 is the max framebuffer size we allow for TV (PAL) */
+
+/* omap24xxfb_vrfb_size() must return the size of the virtual rotated
+ * framebuffer.
+ *
+ * prototype:
+ * unsigned long omap24xxfb_fb_size(void);
+ */
+#define omap24xxfb_vrfb_size() (MAX_PIXELS_PER_LINE * 576 * (16/8))
+
+/* omap24xx_display_pixclock_max() must return the maximum pixclock period
+ * supported by the display.
+ *
+ * prototype:
+ * unsigned int omap24xx_display_pixclock_max(void);
+ */
+#define omap24xx_display_pixclock_max(ouput_dev) \
+ (get_panel_pixclock_max(output_dev))
+
+/* omap24xx_display_pixclock_min() must return the minimum pixclock period
+ * supported by the display.
+ *
+ * prototype:
+ * unsigned int omap24xx_display_pixclock_min(void);
+ */
+#define omap24xx_display_pixclock_min(output_dev) \
+ (get_panel_pixclock_min(output_dev))
+
+/* omap24xxfb_default_var() must return a pointer to a default
+ * fb_var_screeninfo struct that will be used to set the initial video mode.
+ * If this video mode is invalid (as determined by omap24xxfb_check_var) then
+ * the driver will fail to initialize.
+ *
+ * prototype:
+ * struct fb_var_screeninfo *omap24xxfb_default_var(void);
+ */
+
+static struct fb_var_screeninfo *
+omap24xxfb_default_var(void)
+{
+ struct fb_var_screeninfo *v = &default_var;
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+ u32 tmp;
+
+ get_panel_default_var(v, output_dev);
+
+ if (omap24xxfb_rotation >= 0) {
+ v->xres_virtual = v->yres_virtual = max(v->xres, v->yres);
+
+ switch(omap24xxfb_rotation) {
+ case 0:
+ default:
+ v->xoffset = 0;
+ v->yoffset = 0;
+ v->rotate = 0;
+ break;
+ case 90:
+ tmp = v->xres, v->xres = v->yres, v->yres = tmp;
+ v->xoffset = 0;
+ v->yoffset = 0;
+ v->rotate = 90;
+ break;
+ case 180:
+ v->xoffset = 0;
+ v->yoffset = 0;
+ v->rotate = 180;
+ break;
+ case 270:
+ tmp = v->xres, v->xres = v->yres, v->yres = tmp;
+ v->xoffset = 0;
+ v->yoffset = 0;
+ v->rotate = 270;
+ break;
+ }
+ }
+ return v;
+}
+
+/* omap24xxfb_check_mode() must check the video mode specified in a
+ * fb_var_screeninfo struct and return 0 if the mode is supported and
non-zero
+ * if the mode is not supported. omap24xxfb_check_mode() is permitted to
+ * modify the var to make it conform to a supported mode.
+ *
+ * prototype:
+ * int omap24xxfb_check_mode(const struct omap24xxfb_info *oinfo,
+ * struct fb_var_screeninfo *var);
+ */
+static int
+omap24xxfb_check_mode(const struct omap24xxfb_info *oinfo,
+ struct fb_var_screeninfo *var)
+{
+ u32 pixclock, clkdiv;
+ u32 display_xres, display_yres;
+ int output_dev;
+
+ omap2_disp_get_dss();
+ output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ omap2_disp_get_panel_size(output_dev, &display_xres, &display_yres);
+ if (oinfo->rotation_support) {
+
+ if (var->rotate % 90 != 0) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ if (!((var->bits_per_pixel == 8) ||
+ (var->bits_per_pixel == 16))) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ switch (var->rotate) {
+ case 0:
+ case 180:
+ default:
+ if ((var->xres > display_xres) ||
+ (var->yres > display_yres)) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ break;
+ case 90:
+ case 270:
+ if ((var->xres > display_yres) ||
+ (var->yres > display_xres)) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ break;
+ }
+ }
+ else {
+ if ((var->xres > display_xres) ||
+ (var->yres > display_yres)) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ }
+
+ pixclock = (var->pixclock > 0) ? var->pixclock :
+ omap24xx_display_pixclock_max(output_dev);
+
+ if (pixclock < omap24xx_display_pixclock_min(output_dev)){
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ clkdiv = pixclock / oinfo->gfx_clk_period;
+ pixclock = oinfo->gfx_clk_period * clkdiv;
+ if (pixclock > omap24xx_display_pixclock_max(output_dev)) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ /* due to round-down error in division, the pixclock may fall below
+ the lower threshold of the panel. Fix that by adding 1 to clkdiv.
+ */
+ if (pixclock < omap24xx_display_pixclock_min(output_dev))
+ clkdiv = clkdiv + 1;
+
+ if (clkdiv < 2) /* minimum divisor is 2 */
+ clkdiv = 2;
+ else if (clkdiv > 255)
+ clkdiv = 255; /* maximum divisor is 255 */
+
+ /* recalculate pixclock and change the var structure */
+ pixclock = oinfo->gfx_clk_period * clkdiv;
+ var->pixclock = pixclock;
+ omap2_disp_put_dss();
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+struct omap24xxfb_suspend_data {
+ /* Power management suspend lockout stuff */
+ int suspended;
+ wait_queue_head_t suspend_wq;
+};
+static struct omap24xxfb_suspend_data fb_suspend_data;
+
+#define omap24xxfb_suspend_lockout_fp(s,f) \
+ if ((s)->suspended) {\
+ if ((f)->f_flags & O_NONBLOCK)\
+ return -EBUSY;\
+ wait_event_interruptible((s)->suspend_wq,\
+ (s)->suspended == 0);\
+ }
+#define omap24xxfb_suspend_lockout(s) \
+ if ((s)->suspended) {\
+ wait_event_interruptible((s)->suspend_wq,\
+ (s)->suspended == 0);\
+ }
+#else
+#define omap24xxfb_suspend_lockout_fp(s, f) do {} while(0)
+#define omap24xxfb_suspend_lockout(s) do {} while(0)
+#endif /*ifdef CONFIG_PM */
+
+
+/******************************************************************************/
+
+/* Bits-per-pixel and color depth aren't quite the same thing. The OMAP24xx
+ * display controller supports color depths of 1, 2, 4, 8, 12, 16, and 24
bits.
+ * Color depth and bits-per-pixel are the same for depths of 1, 2, 4, 8, and
+ * 16 bits, but for a color depth of 12 bits the pixel data is padded to
+ * 16 bits-per-pixel, and for a color depth of 24 bits the pixel data is
padded
+ * to 32 bits-per-pixel.
+ */
+static inline int
+var_to_depth(const struct fb_var_screeninfo *var)
+{
+ DBGENTER;
+ switch (var->bits_per_pixel) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ default:
+ return var->bits_per_pixel;
+ case 16:
+ if ((var->red.length + var->green.length
+ + var->blue.length) == 12)
+ {
+ return 12;
+ }
+ else
+ return 16;
+ case 32:
+ if (var->transp.length > 0)
+ return 32;
+ else
+ return 24;
+ }
+ DBGLEAVE;
+}
+
+
+/* Calculate the horizontal sync frequency in Hertz
+ * with a resolution of 250Hz.
+ */
+static unsigned int
+horizontal_sync_freq(const struct fb_var_screeninfo *var)
+{
+ unsigned int hsf, hs, nom, den;
+ unsigned int xres, yres;
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ DBGENTER;
+
+ /* Calculate the number of pixels per clock. */
+ omap2_disp_pixels_per_clock(&nom, &den);
+
+ /* get the horizontal display resolution */
+ omap2_disp_get_panel_size(output_dev, &xres, &yres);
+
+ hs = (xres*den)/nom
+ + (var->left_margin + var->right_margin + var->hsync_len);
+
+ if ((var->pixclock > 0) && (hs > 0))
+ hsf = (4000000000UL/(var->pixclock*hs))*250;
+ /* pixclock is in picoseconds
+ * 10^12 / (pixclock*hs) = 4 * 10^9 * 250 / (pixclock*hs)
+ */
+ else
+ hsf = 0;
+
+ DBGLEAVE;
+ return hsf;
+}
+
+/* Calculate the vertical sync frequency in Hertz. */
+static unsigned int
+vertical_sync_freq(const struct fb_var_screeninfo *var)
+{
+ unsigned int vsf, vs;
+ unsigned int xres, yres;
+
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ DBGENTER;
+ /* get the vertical display resolution */
+ omap2_disp_get_panel_size(output_dev, &xres, &yres);
+
+ vs = yres + var->upper_margin + var->lower_margin + var->vsync_len;
+
+ if (vs > 0)
+ vsf = horizontal_sync_freq(var)/vs;
+ else
+ vsf = 0;
+
+ DBGLEAVE;
+ return vsf;
+}
+
+/* Interrupt service routine. */
+static void
+omap24xxfb_isr(void *arg, struct pt_regs *regs)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) arg;
+
+ ++oinfo->vsync_cnt;
+ wake_up_interruptible(&oinfo->vsync_wait);
+}
+
+/* Wait for a vsync interrupt. This routine sleeps so it can only be called
+ * from process context.
+ */
+static int
+omap24xxfb_wait_for_vsync(struct omap24xxfb_info *oinfo)
+{
+ wait_queue_t wqt;
+ unsigned long cnt;
+ int ret;
+ unsigned int mask = 0;
+ DBGENTER;
+
+ mask = (DISPC_IRQSTATUS_EVSYNC_ODD | DISPC_IRQSTATUS_EVSYNC_EVEN
+ | DISPC_IRQSTATUS_VSYNC);
+ omap2_disp_irqenable(omap24xxfb_isr,mask);
+
+ init_waitqueue_entry(&wqt, current);
+
+ cnt = oinfo->vsync_cnt;
+ ret = wait_event_interruptible_timeout(oinfo->vsync_wait,
+ cnt != oinfo->vsync_cnt, oinfo->timeout);
+
+ /*
+ * If the GFX is on TV, then wait for another VSYNC
+ * to compensate for Interlaced scan
+ */
+ if(omap2_disp_get_output_dev(OMAP2_GRAPHICS) == OMAP2_OUTPUT_TV){
+ if(ret<0){
+ cnt = oinfo->vsync_cnt;
+ ret = wait_event_interruptible_timeout(oinfo->vsync_wait,
+ cnt != oinfo->vsync_cnt, oinfo->timeout);
+ }
+ }
+ omap2_disp_irqdisable(omap24xxfb_isr,~(mask));
+
+ DBGLEAVE;
+
+ if (ret < 0)
+ return ret;
+ if (ret == 0)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+#ifdef DEBUG
+static void
+omap24xxfb_synclost_isr(void *arg, struct pt_regs *regs)
+{
+ printk("<sl digital>");
+}
+#endif
+
+/* The GO bit needs to be set for the shadowed registers to take effect in
+ * hardware. Once the hardware is ready, the GO bit will be reset. Per the
+ * hardware specifications, we should not change any display controller
+ * registers until the GO bit is reset.
+ * This function polls the GO bit and waits until it is reset.
+ * If the function may be called when the interrupts are disabled (jiffies
+ * not running). In such cases, the 'count' variable helps to exit the loop
+ * incase the bit gets stuck.
+ */
+static void
+wait_for_reg_sync(int busy_wait, unsigned long timeout)
+{
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+ int count = 200;
+
+ timeout = jiffies + timeout;
+ while (!omap2_disp_reg_sync_done(output_dev) &&
+ time_before(jiffies, timeout) && count) {
+
+ if (busy_wait || in_interrupt()) {
+ udelay(100);
+ count--;
+ }
+ else {
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(1);
+#ifdef CONFIG_PM
+ if (fb_suspend_data.suspended)
+ return;
+#endif
+ }
+ }
+ if (!omap2_disp_reg_sync_done(output_dev)) {
+ printk(KERN_WARNING "timeout waiting for display controller "
+ "to save registers\n");
+ }
+}
+
+ /*
+ * fbops functions
+ */
+
+/*
+ * omap24xxfb_check_var - Validates a var passed in.
+ * @var: frame buffer variable screen structure
+ * @info: frame buffer structure that represents a single frame buffer
+ *
+ * Returns negative errno on error, or zero on success. The var info on
+ * exit may be different than the var info on entry.
+ *
+ * This function accepts any bits-per-pixel value in the range 0 to 32
+ * (0 to 8 for monochrome displays). If the specified number of
+ * bits-per-pixel isn't supported, then the next greater number of
+ * bits-per-pixel will be substituted. This function differentiates
+ * between color depths of 12 and 16 (which both have 16 bits-per-pixel)
+ * by checking to see if the sum of the lengths of the RGB fields is 12,
+ * in which case the color depth is assumed to be 12. Except for
+ * differentiating between 12-bit and 16-bit color depths, the values
+ * passed in var->red, var->green, and var->blue are ignored and replaced
+ * with the correct values for the specified color depth.
+ *
+ * The xres/yres variables in the var screeninfo specify the size of the
+ * graphics window. The graphics window size must not be larger than the
+ * physical display size nor larger than the size of the framebuffer.
+ * The xres_virtual/yres_virtual values in the var screeninfo specify the
+ * size of the framebuffer in memory. The framebuffer must not be smaller
+ * than the size of the graphics window. The display must not be smaller
+ * than the graphics window. The display size depends on whether the
+ * framebuffer is displayed on LCD or a TV. The xoffset/yoffset variables
+ * in the var screeninfo specify the offset of the graphics window within
+ * the framebuffer. There is no means for the user to specify the offset
+ * of the graphics window on the display, so that offset will always be
+ * zero unless the board-specific mode changing function implements some
+ * other behavior, such as centering.
+ */
+static int
+omap24xxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ const struct omap24xxfb_info *oinfo =
+ (const struct omap24xxfb_info *) info->par;
+ struct fb_var_screeninfo v;
+ u32 hbp, hfp, hsw, vbp, vfp, vsw;
+ u32 display_xres, display_yres;
+ int output_dev;
+
+ omap2_disp_get_dss();
+ output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ DBGENTER;
+ memcpy(&v, var, sizeof(v));
+
+ /* do board-specific checks on the var */
+ if (omap24xxfb_check_mode(oinfo, &v)){
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ switch (v.bits_per_pixel) {
+ case 0 ... 1:
+ v.bits_per_pixel = 1;
+ break;
+ case 2:
+ v.bits_per_pixel = 2;
+ break;
+ case 3 ... 4:
+ v.bits_per_pixel = 4;
+ break;
+ case 5 ... 8:
+ v.bits_per_pixel = 8;
+ break;
+ case 9 ... 16:
+ if (v.grayscale) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ v.bits_per_pixel = 16;
+ break;
+ case 17 ... 32:
+ if (v.grayscale) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ v.bits_per_pixel = 32;
+ break;
+ default:
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ switch (var_to_depth(&v)) {
+ case 1:
+ v.red.offset = v.green.offset = v.blue.offset = 0;
+ v.red.length = v.green.length = v.blue.length = 1;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 2:
+ v.red.offset = v.green.offset = v.blue.offset = 0;
+ v.red.length = v.green.length = v.blue.length = 2;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 4:
+ v.red.offset = v.green.offset = v.blue.offset = 0;
+ v.red.length = v.green.length = v.blue.length = 4;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 8:
+ v.red.offset = v.green.offset = v.blue.offset = 0;
+ v.red.length = v.green.length = v.blue.length = 8;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 12:
+ v.red.offset = 8;
+ v.green.offset = 4;
+ v.blue.offset = 0;
+ v.red.length = v.green.length = v.blue.length = 4;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 16:
+ v.red.offset = 11;
+ v.green.offset = 5;
+ v.blue.offset = 0;
+ v.red.length = 5;
+ v.green.length = 6;
+ v.blue.length = 5;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ case 24:
+ v.red.offset = 16;
+ v.green.offset = 8;
+ v.blue.offset = 0;
+ v.red.length = v.blue.length = v.green.length = 8;
+ v.transp.offset = v.transp.length = 0;
+ break;
+ default:
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ omap2_disp_get_panel_size(output_dev, &display_xres, &display_yres);
+ if (display_xres > MAX_PIXELS_PER_LINE ||
+ display_yres > MAX_LINES) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ if (display_xres == 0 || display_yres == 0) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ if (v.xres_virtual < v.xres || v.yres_virtual < v.yres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ if (!oinfo->rotation_support) {
+ if (display_xres < v.xres || display_yres < v.yres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ } else {
+ switch(v.rotate) {
+ case 0:
+ case 180:
+ default:
+ if (display_xres < v.xres ||
+ display_yres < v.yres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ break;
+ case 90:
+ case 270:
+ if (display_xres < v.yres ||
+ display_yres < v.xres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ break;
+ }
+ }
+
+ if (v.xoffset > v.xres_virtual - v.xres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ if (v.yoffset > v.yres_virtual - v.yres) {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+ if ((v.bits_per_pixel < 8) && (((v.xres_virtual % 8) != 0)
+ || ((v.xres % 8) != 0) || ((v.xoffset % 8) != 0)))
+ {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ /* check if we have enough video memory to support this framebuffer */
+ if (((!oinfo->rotation_support) &&
+ (((v.xres_virtual*v.yres_virtual*v.bits_per_pixel)/8)
+ > info->fix.smem_len))
+ ||
+ ((oinfo->rotation_support) &&
+ (((MAX_PIXELS_PER_LINE*v.yres_virtual*v.bits_per_pixel)/8)
+ > info->fix.smem_len)))
+
+ {
+ omap2_disp_put_dss();
+ return -EINVAL;
+ }
+
+ /* calculate horizontal timing parameters in pixclocks */
+ hbp = (v.left_margin > 0) ? (v.left_margin - 1) : 0;
+ if (hbp > 255)
+ hbp = 255;
+ hfp = (v.right_margin > 0) ? (v.right_margin - 1) : 0;
+ if (hfp > 255)
+ hfp = 255;
+ hsw = (v.hsync_len > 0) ? (v.hsync_len - 1) : 0;
+ if (hsw > 63)
+ hsw = 63;
+ v.left_margin = hbp + 1;
+ v.right_margin = hfp + 1;
+ v.hsync_len = hsw + 1;
+
+ /* calculate vertical timing parameters in line clocks */
+ vbp = v.upper_margin;
+ if (vbp > 255)
+ vbp = 255;
+ vfp = v.lower_margin;
+ if (vfp > 255)
+ vfp = 255;
+ vsw = (v.vsync_len > 0) ? (v.vsync_len - 1) : v.vsync_len;
+ if (vsw > 63)
+ vsw = 63;
+ v.upper_margin = vbp;
+ v.lower_margin = vfp;
+ v.vsync_len = vsw + 1;
+
+ v.red.msb_right = v.green.msb_right = v.blue.msb_right
+ = v.transp.msb_right = 0;
+
+ v.nonstd = 0;
+ v.accel_flags = 0;
+
+ memcpy(var, &v, sizeof(v));
+ omap2_disp_put_dss();
+
+ DBGLEAVE;
+ return 0;
+}
+
+/* Calculates the Graphics pipleline DMA parameters */
+
+static int
+omap24xxfb_set_dma_params(const struct fb_var_screeninfo *var,
+ const struct fb_fix_screeninfo *fix,
+ int rotation, int mirroring)
+{
+ int context = 0;
+ u32 view_address_base;
+ u32 start, total_width, img_width;
+ u32 row_inc, pix_inc;
+ u32 xoffset, yoffset;
+
+ if ((rotation > 0) && (rotation % 90 != 0))
+ return -EINVAL;
+
+ if (!mirroring) {
+ if (rotation < 0) {
+ view_address_base = fix->smem_start;
+
+ start = view_address_base
+ + var->yoffset*fix->line_length
+ + (var->xoffset*var->bits_per_pixel)/8;
+
+ total_width = fix->line_length;
+
+ img_width = (var->xres *
+ var->bits_per_pixel)/8;
+ }
+ else {
+ view_address_base = SMS_ROT_VIRT_BASE(context, 0);
+
+ switch (rotation) {
+ /* to the user, xres and yres are interchanged between
+ 0/180 deg and 90/270 deg, but the DMA still has to use the
+ panel's dimension and orientation.
+ */
+ case 0:
+ case 180:
+ default:
+ xoffset = var->xoffset;
+ if (rotation == 180)
+ xoffset += var->xres_virtual - var->xres;
+
+ start = view_address_base
+ + var->yoffset*fix->line_length
+ + (xoffset*var->bits_per_pixel)/8;
+
+ total_width = fix->line_length;
+
+ img_width = (var->xres *
+ var->bits_per_pixel)/8;
+ break;
+ case 90:
+ case 270:
+ yoffset = var->yoffset;
+ if (rotation == 90)
+ yoffset += var->yres_virtual - var->yres;
+
+ start = view_address_base
+ + var->xoffset*fix->line_length
+ + (yoffset*var->bits_per_pixel)/8;
+
+ total_width = fix->line_length;
+ img_width = (var->yres *
+ var->bits_per_pixel)/8;
+ break;
+ }
+ }
+ pix_inc = 1;
+ row_inc = 1 + total_width - img_width;
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS, OMAP2_OUTPUT_LCD,
+ start, start, row_inc, pix_inc);
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS, OMAP2_OUTPUT_TV,
+ start, (start + total_width),
+ (row_inc + total_width), pix_inc);
+ }
+ else { /* mirroring */
+ if (rotation < 0) {
+ view_address_base = fix->smem_start;
+
+ img_width = (var->xres *
+ var->bits_per_pixel)/8;
+
+ start = view_address_base
+ + var->yoffset*fix->line_length
+ + (var->xoffset*var->bits_per_pixel)/8
+
+ + (var->xres - 1) * var->bits_per_pixel/8;
+
+ total_width = fix->line_length;
+
+ pix_inc = - 2 * (var->bits_per_pixel/8) + 1;
+ row_inc = total_width
+ + (var->xres - 2) * var->bits_per_pixel/8 + 1;
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS,
+ OMAP2_OUTPUT_LCD,
+ start, start,
+ row_inc,
+ pix_inc);
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS,
+ OMAP2_OUTPUT_TV,
+ start, (start + total_width),
+ (row_inc + total_width),
+ pix_inc);
+ }
+ else {
+ view_address_base = SMS_ROT_VIRT_BASE(context, 0);
+ switch (rotation) {
+ case 0:
+ case 180:
+ default:
+ xoffset = var->xoffset;
+ if (rotation == 0) {
+ xoffset += var->xres_virtual -
var->xres;
+ }
+
+ start = view_address_base
+ + (var->yres - var->yoffset - 1) * fix->line_length
+ - (xoffset*var->bits_per_pixel)/8;
+
+ total_width = fix->line_length;
+
+ img_width = (var->xres *
+ var->bits_per_pixel)/8;
+ break;
+ case 90:
+ case 270:
+ yoffset = var->yoffset;
+ if (rotation == 270) {
+ yoffset += var->yres_virtual -
var->yres;
+ }
+
+ start = view_address_base
+ + (var->xres - var->xoffset - 1) * fix->line_length
+ + (yoffset*var->bits_per_pixel)/8;
+
+ total_width = fix->line_length;
+
+ img_width = (var->yres *
+ var->bits_per_pixel)/8;
+ break;
+ }
+ pix_inc = 1;
+ row_inc = - (total_width + img_width) + 1;
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS,
+ OMAP2_OUTPUT_LCD,
+ start, start,
+ row_inc,
+ pix_inc);
+
+ omap2_disp_set_dma_params(OMAP2_GRAPHICS,
+ OMAP2_OUTPUT_TV,
+ start, (start - total_width),
+ (row_inc - total_width),
+ pix_inc);
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * omap24xxfb_set_par - Alters the hardware state.
+ * @info: frame buffer structure that represents a single frame buffer
+ *
+ * Using the fb_var_screeninfo in fb_info we set the resolution of
+ * this particular framebuffer. This function alters the par AND the
+ * fb_fix_screeninfo stored in fb_info. It does not alter var in
+ * fb_info since we are using that data. This means we depend on the
+ * data in var inside fb_info to be supported by the hardware.
+ * omap24xxfb_check_var is always called before omap24xxfb_set_par to
+ * ensure this.
+ *
+ */
+
+static int
+omap24xxfb_set_par(struct fb_info *info)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+ struct fb_var_screeninfo *var = &info->var;
+ u32 clkdiv, hbp, hfp, hsw, vbp, vfp, vsw;
+ int ret = 0;
+
+ DBGENTER;
+
+ if (oinfo->asleep)
+ return 0;
+
+ omap2_disp_get_dss();
+ /* update the fix screeninfo */
+ if (oinfo->rotation_support) {
+ oinfo->rotation_deg = var->rotate;
+ info->fix.line_length = MAX_PIXELS_PER_LINE *
+ var->bits_per_pixel / 8;
+ }
+ else
+ info->fix.line_length =
+ (var->xres_virtual*var->bits_per_pixel)/8;
+
+ info->fix.visual = ((var_to_depth(var) <= 8) ?
+ FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR);
+
+ /* Graphics window parameters */
+ if ((oinfo->rotation_support) &&
+ ((oinfo->rotation_deg == 90) || (oinfo->rotation_deg == 270))) {
+ omap2_disp_config_gfxlayer(var->yres, var->xres,
+ var_to_depth(var));
+ } else { // no rotation, or 0 or 180 degrees rotation
+ omap2_disp_config_gfxlayer(var->xres, var->yres,
+ var_to_depth(var));
+ }
+
+ omap2_disp_set_gfx_palette(oinfo->palette_phys);
+
+ /* Rotation */
+ if (oinfo->rotation_support) {
+ int width = 0, height = 0;
+
+ if ((var->rotate == 90) || (var->rotate == 270)) {
+ width = var->xres_virtual;
+ height = var->yres_virtual;
+ } else {
+ width = var->yres_virtual;
+ height = var->xres_virtual;
+ }
+ omap2_disp_set_vrfb(0, oinfo->fb_base_phys,
+ width, height, var->bits_per_pixel/8);
+
+ if(omap24xxfb_mirroring){
+
+ info->fix.smem_start =
+ oinfo->sms_rot_phy[omap_rot_mirror_index(oinfo->rotation_deg)];
+ info->screen_base =
+ (char *)
(oinfo->sms_rot_virt[omap_rot_mirror_index(oinfo->rotation_deg)]);
+ }
+ else{
+ info->fix.smem_start =
+ oinfo->sms_rot_phy[omap_rotation_index(oinfo->rotation_deg)];
+ info->screen_base =
+ (char *)(oinfo->sms_rot_virt[omap_rotation_index(oinfo->rotation_deg)]);
+ }
+ }
+
+ /* Graphics DMA parameters */
+ ret = omap24xxfb_set_dma_params(var, &info->fix,
+ (oinfo->rotation_support ? var->rotate : -1),
+ omap24xxfb_mirroring);
+
+ /* LCD parameters */
+ clkdiv = var->pixclock / oinfo->gfx_clk_period;
+ /* horizontal timing parameters in pixclocks */
+ hbp = (var->left_margin > 0) ? (var->left_margin - 1) : 0;
+ hfp = (var->right_margin > 0) ? (var->right_margin - 1) : 0;
+ hsw = (var->hsync_len > 0) ? (var->hsync_len - 1) : 0;
+ /* vertical timing parameters in line clocks */
+ vbp = var->upper_margin;
+ vfp = var->lower_margin;
+ vsw = (var->vsync_len > 0) ? (var->vsync_len - 1) : var->vsync_len;
+
+ oinfo->hsync = horizontal_sync_freq(var);
+ oinfo->vsync = vertical_sync_freq(var);
+ if (oinfo->vsync > 0)
+ oinfo->timeout = ((HZ + oinfo->vsync - 1)/oinfo->vsync)*2;
+ else
+ oinfo->timeout = HZ/5; /* 200ms default timeout */
+
+ omap2_disp_config_lcd(clkdiv, hbp, hfp, hsw, vbp, vfp, vsw);
+
+ if (!ret) {
+ if(fb_out_layer == OMAP2_GRAPHICS)
+ omap2_disp_start_gfxlayer();
+ else{
+ omap24xxfb_set_output_layer(fb_out_layer);
+ omap2_disp_start_gfxlayer();
+ }
+ wait_for_reg_sync(SCHEDULE_WAIT, oinfo->timeout);
+ }
+ omap2_disp_put_dss();
+ return ret;
+}
+
+
+int
+omap24xxfb_set_output_layer(int layer)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) saved_oinfo;
+ int ret = 0;
+ struct fb_var_screeninfo *var = &oinfo->info.var;
+
+ struct v4l2_pix_format pix;
+ struct v4l2_rect crop;
+ struct v4l2_window win;
+ int rotate = -1;
+
+ memset(&pix, 0, sizeof(pix));
+ memset(&crop, 0, sizeof(crop));
+ memset(&win, 0, sizeof(win));
+
+ pix.pixelformat = V4L2_PIX_FMT_RGB565;
+ pix.colorspace = V4L2_COLORSPACE_SRGB;
+
+ pix.field = V4L2_FIELD_NONE;
+ pix.width = var->xres;
+ pix.height = var->yres;
+ pix.bytesperline = pix.width * 2;
+ pix.priv = 0;
+ pix.sizeimage = pix.bytesperline * pix.height;
+
+ crop.left = 0;
+ crop.top = 0;
+ crop.width = var->xres;
+ crop.height = var->yres;
+
+ win.w.width = var->xres;
+ win.w.height = var->yres;
+ win.w.left = var->xoffset;
+ win.w.top = var->yoffset;
+
+
+ DBGENTER;
+
+ if(layer == OMAP2_GRAPHICS){
+ #ifdef DEBUG
+ printk("Switching FB to GFX pipeline \n");
+ #endif
+ omap24xxfb_set_par(&saved_oinfo->info);
+ }
+ else{
+ #ifdef DEBUG
+ printk("Switching FB to video pipeline%d \n",layer);
+ printk("var.xres=%d, var.yres=%d
\n",oinfo->info.var.xres,oinfo->info.var.yres);
+ printk("var.xoffset=%d, var.yoffset=%d
\n",oinfo->info.var.xoffset,oinfo->info.var.yoffset);
+ #endif
+ mdelay(1);
+
+ rotate = (oinfo->rotation_support) ? var->rotate : -1;
+
omap2_disp_config_vlayer(layer,&pix,&crop,&win,rotate,omap24xxfb_mirroring);
+ mdelay(1);
+ omap2_disp_start_vlayer(layer,&pix,&crop,&win, (rotate>=0)?
SMS_ROT_VIRT_BASE(0,0):oinfo->info.fix.smem_start,rotate,omap24xxfb_mirroring);
+ wait_for_reg_sync(SCHEDULE_WAIT, oinfo->timeout);
+ }
+
+ DBGLEAVE;
+ return ret;
+
+}
+
+/*
+ * omap24xxfb_setcolreg - Sets a color register.
+ * @regno: Which register in the CLUT we are programming
+ * @red: The red value which can be up to 16 bits wide
+ * @green: The green value which can be up to 16 bits wide
+ * @blue: The blue value which can be up to 16 bits wide.
+ * @transp: If supported the alpha value which can be up to 16 bits wide.
+ * @info: frame buffer info structure
+ *
+ * Returns non-zero on error, or zero on success.
+ */
+static int
+omap24xxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp, struct fb_info *info)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ if (regno >= 256) /* maximum number of palette entries */
+ return 1;
+
+ omap2_disp_get_dss();
+ if (info->var.grayscale) {
+ /* grayscale = 0.30*R + 0.59*G + 0.11*B */
+ red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
+ }
+
+ /* Truecolor has hardware-independent 16-entry pseudo-palette */
+ if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
+ u32 v;
+
+ if (regno >= 16) {
+ omap2_disp_put_dss();
+ return 1;
+ }
+
+ red >>= (16 - info->var.red.length);
+ green >>= (16 - info->var.green.length);
+ blue >>= (16 - info->var.blue.length);
+
+ v = (red << info->var.red.offset) |
+ (green << info->var.green.offset) |
+ (blue << info->var.blue.offset);
+
+ switch (info->var.bits_per_pixel) {
+ case 16:
+ ((u16*)(info->pseudo_palette))[regno] = v;
+ break;
+ case 32:
+ ((u32*)(info->pseudo_palette))[regno] = v;
+ break;
+ default:
+ omap2_disp_put_dss();
+ return 1;
+ }
+ omap2_disp_put_dss();
+ return 0;
+ }
+
+ red >>= 8;
+ green >>= 8;
+ blue >>= 8;
+ (oinfo->palette)[regno] = (red << 16) | (green << 8) | (blue << 0);
+ if(regno == 255){
+ omap2_disp_set_gfx_palette(oinfo->palette_phys);
+ omap2_disp_reg_sync(output_dev);
+ }
+ omap2_disp_put_dss();
+
+ DBGLEAVE;
+ return 0;
+}
+
+
+/*
+ * omap24xxfb_pan_display - Pans the display.
+ * @var: frame buffer variable screen structure
+ * @info: frame buffer structure that represents a single frame buffer
+ *
+ * Pan the display using the `xoffset' and `yoffset' fields of the `var'
+ * structure. We don't support wrapping and ignore the FB_VMODE_YWRAP
+ * flag.
+ *
+ * If the values don't fit, return -EINVAL.
+ *
+ * Returns negative errno on error, or zero on success.
+ */
+static int
+omap24xxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+ int ret;
+
+ DBGENTER;
+
+ if (var->xoffset > info->var.xres_virtual - info->var.xres)
+ return -EINVAL;
+ if (var->yoffset > info->var.yres_virtual - info->var.yres)
+ return -EINVAL;
+ if ((info->var.bits_per_pixel < 8) && ((var->xoffset % 8) != 0))
+ {
+ return -EINVAL;
+ }
+
+ if (oinfo->asleep)
+ return 0;
+
+ omap2_disp_get_dss();
+ /* Graphics DMA parameters */
+ ret = omap24xxfb_set_dma_params(var, &info->fix,
+ (oinfo->rotation_support ? var->rotate : -1),
+ omap24xxfb_mirroring);
+
+ if (!ret) {
+ if (fb_out_layer == OMAP2_GRAPHICS)
+ omap2_disp_start_gfxlayer();
+ else{
+ omap2_disp_start_gfxlayer();
+ omap24xxfb_set_output_layer(fb_out_layer);
+ }
+
+ wait_for_reg_sync(SCHEDULE_WAIT, oinfo->timeout);
+ }
+
+ omap2_disp_put_dss();
+
+ DBGLEAVE;
+ return ret;
+}
+
+/**
+ * omap24xxfb_blank - NOT a required function. Blanks the display.
+ *
+ * @blank_mode: the blank mode we want.
+ * @info: frame buffer structure that represents a single frame buffer
+ *
+ * Blank the screen if blank_mode != 0, else unblank.
+ */
+static int
+omap24xxfb_blank(int blank_mode, struct fb_info *info)
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+
+ DBGENTER;
+
+ /* No need for suspend lockout because if the framebuffer device is
+ * suspended, then the console is already blanked.
+ */
+ if (oinfo->asleep)
+ return 0;
+
+ if ((blank_mode) && (!oinfo->blanked)) {
+ /* blank--disable display controller */
+ /* wait until Vsync */
+ if (omap24xxfb_wait_for_vsync(oinfo) != 0)
+ printk("omap24xxfb_blank: vsyn wait failed \n");
+ omap2_disp_disable_layer(OMAP2_GRAPHICS);
+ omap2_disp_disable_layer(fb_out_layer);
+ omap2_disp_disable(HZ/5);
+ disable_backlight();
+ omap2_disp_put_dss();
+ omap2_dss_rgb_disable();
+ oinfo->blanked = 1;
+ }
+ else if ((!blank_mode) && (oinfo->blanked)) {
+ /* unblank--enable display controller */
+ omap2_dss_rgb_enable();
+ omap2_disp_get_dss();
+ omap2_disp_enable_layer(OMAP2_GRAPHICS);
+ omap2_disp_enable_layer(fb_out_layer);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+ oinfo->blanked = 0;
+ udelay(20);
+ enable_backlight();
+ }
+
+ DBGLEAVE;
+ return 0;
+}
+
+/**
+ * omap24xxfb_sync - NOT a required function. Normally the accel engine
+ * for a graphics card take a specific amount of time.
+ * Often we have to wait for the accelerator to finish
+ * its operation before we can write to the framebuffer
+ * so we can have consistent display output.
+ *
+ * @info: frame buffer structure that represents a single frame buffer
+ */
+static int
+omap24xxfb_sync(struct fb_info *info)
+{
+ return 0;
+}
+
+/**
+ * omap24xxfb_set_mirroring - enables and disables mirroring
+ */
+static int
+omap24xxfb_set_mirroring (struct fb_info *info, int mirroring)
+{
+ int ret = 0;
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+
+ omap24xxfb_mirroring = mirroring;
+ ret = omap24xxfb_set_dma_params(&info->var, &info->fix,
(oinfo->rotation_support ? info->var.rotate : -1), omap24xxfb_mirroring);
+ if (!ret)
+ {
+ if (fb_out_layer == OMAP2_GRAPHICS)
+ omap2_disp_start_gfxlayer();
+ else{
+ omap24xxfb_set_output_layer(fb_out_layer);
+ omap2_disp_start_gfxlayer();
+ }
+
+
+ wait_for_reg_sync(SCHEDULE_WAIT, oinfo->timeout);
+ }
+
+ return ret;
+}
+
+/**
+ * omap24xxfb_ioctl - handler for private ioctls.
+ */
+static int
+omap24xxfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
+
+{
+ struct omap24xxfb_info *oinfo = (struct omap24xxfb_info *) info->par;
+ void __user *argp = (void __user *)arg;
+ int mirroring;
+ int ret;
+ struct omap_lcd_info *lcd_inf;
+
+ DBGENTER;
+ omap2_disp_get_dss();
+
+ omap24xxfb_suspend_lockout(&fb_suspend_data);
+
+ switch (cmd) {
+ case FBIO_WAITFORVSYNC:
+ /* This ioctl accepts an integer argument to specify a
+ * display. We only support one display, so we will
+ * simply ignore the argument.
+ */
+ ret = omap24xxfb_wait_for_vsync(oinfo);
+ omap2_disp_put_dss();
+ return ret;
+ case FBIO_MIRROR:
+ /* This ioctl accepts an integer argument to specify the
+ * mirroring status.
+ */
+ if (!copy_from_user(&mirroring, argp, sizeof(mirroring))) {
+ ret = omap24xxfb_set_mirroring (info, mirroring);
+ omap2_disp_put_dss();
+ return ret;
+ }
+#ifdef CONFIG_LCD_IOCTL
+ /* This ioctl accepts a structure of type lcd_info and
+ * uses that to configure the LCD
+ */
+ case FBIO_LCD_PUT_SCREENINFO:
+ lcd_inf = (struct omap_lcd_info *)arg;
+ ret = omap_lcd_init(lcd_inf);
+ return ret;
+
+#endif
+ }
+ omap2_disp_put_dss();
+ DBGLEAVE;
+ return -EINVAL;
+}
+
+/*---------------------------------------------------------------------------*/
+ /*
+ * Frame buffer operations
+ */
+
+static struct fb_ops omap24xxfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = omap24xxfb_check_var,
+ .fb_set_par = omap24xxfb_set_par,
+ .fb_setcolreg = omap24xxfb_setcolreg,
+ .fb_blank = omap24xxfb_blank,
+ .fb_pan_display = omap24xxfb_pan_display,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+
+ .fb_rotate = NULL,
+ .fb_sync = omap24xxfb_sync,
+ .fb_ioctl = omap24xxfb_ioctl,
+};
+
+/*---------------------------------------------------------------------------*/
+#ifdef CONFIG_PM
+
+static int awake = 0;
+
+
+/* PM suspend */
+static int omap24xxfb_suspend(struct platform_device *dev, pm_message_t
state)
+{
+ struct omap24xxfb_info *oinfo = saved_oinfo;
+
+ acquire_console_sem();
+ fb_set_suspend(&oinfo->info, 1);
+ release_console_sem();
+
+ printk(KERN_DEBUG "Suspend Check Awake\n");
+ if (!awake)
+ return 0;
+
+ printk(KERN_DEBUG "Disable LCD\n");
+
+ omap24xxfb_blank(1, &oinfo->info);
+ awake = 0;
+ oinfo->asleep = 1;
+
+ return 0;
+}
+
+/* PM resume */
+static int omap24xxfb_resume(struct platform_device *dev)
+{
+ struct omap24xxfb_info *oinfo = saved_oinfo;
+
+ printk(KERN_DEBUG "Resume Check Awake\n");
+
+ /* If already awake then leave */
+ if (awake)
+ return 0;
+
+ printk(KERN_DEBUG "Enable LCD\n");
+ oinfo->asleep = 0;
+
+ /* unblank the screen */
+ omap24xxfb_blank(0, &oinfo->info);
+ awake = 1;
+ acquire_console_sem();
+ fb_set_suspend(&oinfo->info, 0);
+ release_console_sem();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DPM
+
+static struct constraints omap24xxfb_constraints = {
+ .count = 2,
+ .param = {
+ {DPM_MD_V, OMAP24XX_V_MIN, OMAP24XX_V_MAX},
+ {DPM_MD_SLEEP_MODE, PM_SUSPEND_STANDBY, PM_SUSPEND_MEM},
+ },
+};
+
+/* This routine is called by DPM to notify the driver before and after a
+ * frequency scale. The pixel clock divisor has to be changed after a
+ * frequency change to maintain the refresh rate.
+ */
+static int
+omap24xxfb_scale(struct notifier_block *op, unsigned long level, void *ptr)
+{
+ struct omap24xxfb_info *oinfo = saved_oinfo;
+ struct fb_info *info;
+ u32 clkdiv, pixclock;
+ struct fb_videomode mode;
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+ info = &oinfo->info;
+
+ switch (level) {
+ case SCALE_PRECHANGE:
+ /* disable the graphics layer because there should be
+ no memory accesses (possibly through DMA) while
+ scaling frequency, on boards with DDR memory - Errata
+ */
+ omap2_disp_disable_layer(OMAP2_GRAPHICS);
+ wait_for_reg_sync(BUSY_WAIT, oinfo->timeout);
+ break;
+ case SCALE_POSTCHANGE:
+ /*
+ * The Core frequency might have dropped resulting in DSS fclk drop
+ * But we would like to continue with the same DSS fclk
+ */
+ omap2_disp_set_dssfclk();
+
+ /* set the PCD divisor according to the new gfx_clock_period.
+ gfx_clock_period is in picoseconds
+ dss1_clk is in kHz */
+ oinfo->gfx_clk_period = omap24xxfb_gfx_clk_period();
+
+ clkdiv = info->var.pixclock / oinfo->gfx_clk_period;
+ pixclock = oinfo->gfx_clk_period * clkdiv;
+
+ /* due to round-down error in division, the pixclock
+ may fall below the lower threshold of the panel.
+ Fix that by adding 1 to clkdiv.
+ */
+ if (pixclock < omap24xx_display_pixclock_min(output_dev))
+ clkdiv = clkdiv + 1;
+ if (clkdiv < 2) /* minimum divisor is 2 */
+ clkdiv = 2;
+ else if (clkdiv > 255)
+ clkdiv = 255; /* maximum divisor is 255 */
+
+ /* recalculate pixclock and change the var structure */
+ pixclock = oinfo->gfx_clk_period * clkdiv;
+ info->var.pixclock = pixclock;
+
+ fb_var_to_videomode(&mode, &info->var);
+ fb_add_videomode(&mode, &info->modelist);
+
+ omap2_disp_set_pcd(clkdiv);
+ /* enable the graphics layer and the display controller */
+ omap2_disp_enable_layer(OMAP2_GRAPHICS);
+ break;
+ }
+ return 0;
+}
+
+static struct notifier_block omap24xxfb_pre_scale = {
+ .notifier_call = omap24xxfb_scale,
+};
+
+static struct notifier_block omap24xxfb_post_scale = {
+ .notifier_call = omap24xxfb_scale,
+};
+
+#endif
+
+static int
+omap24xxfb_probe (struct platform_device *dev)
+{
+ return 0;
+}
+
+static void
+omap24xxfb_release (struct device *dev)
+{
+ return;
+}
+
+static struct platform_driver omap24xxfb_driver = {
+ .driver = {
+ .name = OMAPFB_DRIVER,
+ },
+ .probe = omap24xxfb_probe,
+#ifdef CONFIG_PM
+ .suspend = omap24xxfb_suspend,
+ .resume = omap24xxfb_resume,
+#endif
+};
+
+static struct platform_device omap24xxfb_device = {
+ .name = OMAPFB_DEVICE,
+ .id = 6,
+
+ .dev = {
+#ifdef CONFIG_DPM
+ .constraints = &omap24xxfb_constraints,
+#endif
+ .release = omap24xxfb_release,
+ },
+};
+
+int omap24xx_get_dss1_clock(void)
+{
+#ifdef CONFIG_TRACK_RESOURCES
+ struct device *dev = &omap_fb_dev;
+#else
+ struct device *dev = NULL;
+#endif
+ struct clk *dss1f;
+ char *dss1_fck = cpu_is_omap34xx() ? "dss1_alwon_fck" : "dss1_fck";
+
+ dss1f = clk_get(dev, dss1_fck);
+ return clk_get_rate(dss1f);
+}
+
+/*---------------------------------------------------------------------------*/
+
+#ifndef MODULE
+int omap24xxfb_setup(char *options)
+{
+ char *this_opt;
+
+ printk(KERN_INFO "omap24xxfb: Options \"%s\"\n", options);
+
+ if (!options || !*options)
+ return 0;
+
+ while((this_opt = strsep(&options, ",")) != NULL) {
+ if (!*this_opt) continue;
+ if (!strncmp(this_opt, "rotation=", 9)) {
+ int deg = simple_strtoul(this_opt + 9, NULL, 0);
+
+ if (deg == 0 || deg == 90 || deg == 180 || deg == 270)
+ omap24xxfb_rotation = deg;
+ else
+ omap24xxfb_rotation = -1;
+
+ printk(KERN_INFO "omap24xxfb: Rotation %s\n",
+ (omap24xxfb_rotation == -1) ?
+ "none (supported: \"rotation=[0|90|180|270]\")":
+ this_opt);
+ } else
+ printk(KERN_INFO "omap24xxfb: Invalid parameter \"%s\" "
+ "(supported: \"rotation=[0|90|180|270]\")\n",
+ this_opt);
+ }
+ return 0;
+}
+#endif
+
+#ifdef DEBUG_VRFB
+void test_vrfb_line(struct omap24xxfb_info *oinfo,
+ int line, int from, int upto, int total)
+{
+ int j=0;
+
+ for (j=from; j<upto; j+=4) {
+ *((u32 *)(oinfo->sms_rot_virt[0] + line*total + j)) = 0xf1f1e1e1;
+ }
+}
+
+void test_vrfb_space(struct omap24xxfb_info *oinfo,
+ int lines, int from, int upto, int total)
+{
+ int i=0;
+ printk("test_vrfb_space: lines %d, from %d to %d\n", lines, from, upto);
+ for (i=0; i<lines; i++) {
+ test_vrfb_line(oinfo, i, from, upto, total);
+ }
+}
+#endif
+
+static ssize_t
+read_fb_out(char *buf)
+{
+ int p = 0;
+
+ switch(fb_out_layer){
+ case OMAP2_GRAPHICS: p = sprintf(buf, "gfx\n");
+ break;
+ case OMAP2_VIDEO1: p = sprintf(buf, "video1\n");
+ break;
+ case OMAP2_VIDEO2: p = sprintf(buf, "video2\n");
+ break;
+ }
+
+ return(p);
+}
+
+static ssize_t
+write_fb_out(const char *buffer, size_t count)
+{
+ int out_layer;
+
+ if(!buffer || (count == 0))
+ return 0;
+
+ /* Only 'lcd' or 'tv' are valid inputs */
+ if(strncmp(buffer, "gmx", 3) == 0)
+ out_layer = OMAP2_GRAPHICS;
+ else if(strncmp(buffer, "video1", 6) == 0)
+ out_layer = OMAP2_VIDEO1;
+ else if(strncmp(buffer, "video2", 6) == 0)
+ out_layer = OMAP2_VIDEO2;
+ else
+ return -EINVAL;
+
+ if(out_layer != fb_out_layer){
+ /* switch the output layer */
+ /* check if the pipeline is available */
+ if(omap2_disp_request_layer(out_layer)){
+ omap2_disp_start_gfxlayer();
+ fb_out_layer = out_layer;
+ omap24xxfb_set_output_layer(out_layer);
+ }
+ }
+
+ return count;
+}
+
+ssize_t
+fb_out_show(struct device *cdev, char *buf)
+{
+ return(read_fb_out(buf));
+}
+
+ssize_t
+fb_out_store(struct device *cdev, const char *buffer, size_t count)
+{
+ return(write_fb_out(buffer,count));
+}
+
+/*
+ * Initialization
+ */
+int __init omap24xxfb_init(void)
+{
+ struct omap24xxfb_info *oinfo;
+ struct fb_info *info;
+ int output_dev = omap2_disp_get_output_dev(OMAP2_GRAPHICS);
+
+ DBGENTER;
+
+ /* Register the driver with LDM */
+ if (platform_driver_register(&omap24xxfb_driver)) {
+ printk(KERN_ERR FB_NAME ": failed to register omapfb driver\n");
+ return -ENODEV;
+ }
+
+ /* Register the device with LDM */
+ if (platform_device_register(&omap24xxfb_device)) {
+ printk(KERN_ERR FB_NAME ": failed to register omapfb device\n");
+ goto unregister_driver;
+ }
+
+#ifdef CONFIG_DPM
+ dpm_register_scale(&omap24xxfb_pre_scale,SCALE_PRECHANGE);
+ dpm_register_scale(&omap24xxfb_post_scale,SCALE_POSTCHANGE);
+#endif
+
+#ifdef CONFIG_PM
+ awake = 1;
+ fb_suspend_data.suspended = 0;
+ init_waitqueue_head(&fb_suspend_data.suspend_wq);
+#endif
+
+#ifndef MODULE
+ {
+ char *option;
+
+ if (fb_get_options("omap24xxfb", &option)) {
+ return -ENODEV;
+ }
+ omap24xxfb_setup(option); // parse options
+ }
+#endif
+
+ oinfo = kmalloc(sizeof(struct omap24xxfb_info), GFP_KERNEL);
+ if (!oinfo) {
+ printk(KERN_ERR FB_NAME ": could not allocate memory\n");
+ goto unregister_device;
+ }
+ memset(oinfo, 0, sizeof(struct omap24xxfb_info));
+ saved_oinfo = oinfo;
+
+ oinfo->rotation_support = (omap24xxfb_rotation >= 0) ? 1 : 0;
+
+ /* set the period (in picoseconds) of the graphics timebase */
+ oinfo->gfx_clk_period = omap24xxfb_gfx_clk_period();
+
+ /* Set base addrs */
+ oinfo->fb_base_phys = omap24xxfb_fb_base();
+
+ oinfo->fb_size = omap24xxfb_fb_size(oinfo->rotation_support);
+
+ if (oinfo->rotation_support) {
+ oinfo->vrfb_size = omap24xxfb_vrfb_size();
+ oinfo->rotation_deg = omap24xxfb_rotation;
+ }
+
+ oinfo->mmio_base_phys = DSS_REG_BASE;
+
+ /* A null base address indicates that the framebuffer memory should be
+ * dynamically allocated.
+ */
+ if (!oinfo->fb_base_phys)
+ oinfo->alloc_fb_mem = 1;
+
+ /* request the mem regions */
+ if (!request_mem_region(oinfo->mmio_base_phys, DSS_REG_SIZE, FB_NAME))
+ {
+ printk(KERN_ERR FB_NAME ": cannot reserve MMIO region\n");
+ goto free_par;
+ }
+
+ if (!oinfo->alloc_fb_mem) {
+ if (!request_mem_region(oinfo->fb_base_phys,
+ oinfo->fb_size, FB_NAME))
+ {
+ printk(KERN_ERR FB_NAME ": cannot reserve FB region\n");
+ goto release_mmio;
+ }
+ }
+
+ if (oinfo->rotation_support) {
+ oinfo->sms_rot_phy[0] = SMS_ROT_VIRT_BASE(0, 0);
+ oinfo->sms_rot_phy[1] = SMS_ROT_VIRT_BASE(0, 90);
+ oinfo->sms_rot_phy[2] = SMS_ROT_VIRT_BASE(0, 180);
+ oinfo->sms_rot_phy[3] = SMS_ROT_VIRT_BASE(0, 270);
+
+ if (!request_mem_region(oinfo->sms_rot_phy[0],
+ oinfo->vrfb_size, FB_NAME)) {
+ printk(KERN_ERR FB_NAME
+ ": cannot reserve FB region for 0 deg\n");
+ goto release_fb;
+ }
+ if (!request_mem_region(oinfo->sms_rot_phy[1],
+ oinfo->vrfb_size, FB_NAME)) {
+ printk(KERN_ERR FB_NAME
+ ": cannot reserve FB region for 90 deg\n");
+ goto release_rot_0;
+ }
+ if (!request_mem_region(oinfo->sms_rot_phy[2],
+ oinfo->vrfb_size, FB_NAME)) {
+ printk(KERN_ERR FB_NAME
+ ": cannot reserve FB region for 180 deg\n");
+ goto release_rot_90;
+ }
+ if (!request_mem_region(oinfo->sms_rot_phy[3],
+ oinfo->vrfb_size, FB_NAME)) {
+ printk(KERN_ERR FB_NAME
+ ": cannot reserve FB region for 270 deg\n");
+ goto release_rot_180;
+ }
+ }
+
+ /* map the regions */
+ oinfo->mmio_base =
+ (unsigned long) ioremap(oinfo->mmio_base_phys, DSS_REG_SIZE);
+ if (!oinfo->mmio_base) {
+ printk(KERN_ERR FB_NAME ": cannot map MMIO\n");
+ if (oinfo->rotation_support)
+ goto release_rot_270;
+ else
+ goto release_fb;
+ }
+
+ if (!oinfo->alloc_fb_mem) {
+ oinfo->fb_base =
+ (unsigned long) ioremap(oinfo->fb_base_phys,
+ oinfo->fb_size);
+ if (!oinfo->fb_base) {
+ printk(KERN_ERR FB_NAME ": cannot map framebuffer\n");
+ goto unmap_mmio;
+ }
+ }
+ else {
+ /* allocate coherent memory for the framebuffer */
+ oinfo->fb_base = (unsigned long) dma_alloc_coherent(NULL,
+ oinfo->fb_size, &oinfo->fb_base_phys,
+ GFP_KERNEL | GFP_DMA);
+ if (!oinfo->fb_base) {
+ printk(KERN_ERR FB_NAME ": cannot allocate "
+ "framebuffer\n");
+ goto unmap_mmio;
+ }
+ }
+ memset((void *)oinfo->fb_base, 0, oinfo->fb_size);
+
+ if (oinfo->rotation_support) {
+ if (!(oinfo->sms_rot_virt[0] =
+ (unsigned long) ioremap(oinfo->sms_rot_phy[0],
+ oinfo->vrfb_size)) ||
+ !(oinfo->sms_rot_virt[1] =
+ (unsigned long) ioremap(oinfo->sms_rot_phy[1],
+ oinfo->vrfb_size)) ||
+ !(oinfo->sms_rot_virt[2] =
+ (unsigned long) ioremap(oinfo->sms_rot_phy[2],
+ oinfo->vrfb_size)) ||
+ !(oinfo->sms_rot_virt[3] =
+ (unsigned long) ioremap(oinfo->sms_rot_phy[3],
+ oinfo->vrfb_size)))
+ {
+ printk(KERN_ERR FB_NAME ": cannot map rotated view(s)\n");
+ goto unmap_rot;
+ }
+ }
+
+ /* allocate coherent memory for the palette */
+ oinfo->palette = (u32 *) dma_alloc_coherent(NULL, sizeof(u32)*256,
+ &oinfo->palette_phys, GFP_KERNEL | GFP_DMA);
+ if (!oinfo->palette) {
+ printk(KERN_ERR FB_NAME ": cannot allocate palette memory\n");
+ goto unmap_rot;
+ }
+ memset(oinfo->palette, 0, sizeof(u32)*256);
+
+ if(!omap2_disp_request_layer(OMAP2_GRAPHICS)) {
+ printk(KERN_ERR FB_NAME ": cannot use hw graphics layer\n");
+ goto free_palette;
+ }
+
+ /* first enable the power to RGB lines.. then turhn on the LCD..
+ * as per the SHARP LCD specs */
+ omap2_dss_rgb_enable();
+ // enable_backlight();
+ omap2_disp_get_dss();
+ /* unblank--enable display controller */
+ omap2_disp_enable_layer(OMAP2_GRAPHICS);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_LCD);
+ omap2_disp_enable_output_dev(OMAP2_OUTPUT_TV);
+ udelay(20);
+ enable_backlight();
+ /* initialize the fb_info structure */
+ info = &oinfo->info;
+ info->flags = FBINFO_DEFAULT;
+ info->fbops = &omap24xxfb_ops;
+
+ if (oinfo->rotation_support){
+ /* If mirroring in rotation is enabled by default */
+ if(omap24xxfb_mirroring == 1){
+ info->screen_base =
+ (char *)
(oinfo->sms_rot_virt[omap_rot_mirror_index(oinfo->rotation_deg)]);
+ }
+ else{
+ info->screen_base = (char *)
+ (oinfo->sms_rot_virt[omap_rotation_index(oinfo->rotation_deg)]);
+ }
+ }
+ else
+ info->screen_base = (char *)(oinfo->fb_base);
+
+ info->pseudo_palette = oinfo->pseudo_palette;
+ info->par = oinfo;
+ /* Initialize variable screeninfo.
+ * The variable screeninfo can be directly specified by the user
+ * via an ioctl.
+ */
+ memcpy(&info->var, omap24xxfb_default_var(), sizeof(info->var));
+ info->var.activate = FB_ACTIVATE_NOW;
+
+ /* Initialize fixed screeninfo.
+ * The fixed screeninfo cannot be directly specified by the user, but
+ * it may change to reflect changes to the var info.
+ */
+ strlcpy(info->fix.id, FB_NAME, sizeof(info->fix.id));
+ if (oinfo->rotation_support) {
+ /* If mirroring in rotation is enabled by default */
+ if(omap24xxfb_mirroring == 1){
+ info->fix.smem_start =
+ oinfo->sms_rot_phy[omap_rot_mirror_index(oinfo->rotation_deg)];
+ }
+ else{
+ info->fix.smem_start =
+ oinfo->sms_rot_phy[omap_rotation_index(oinfo->rotation_deg)];
+ }
+ info->fix.line_length = MAX_PIXELS_PER_LINE *
+ info->var.bits_per_pixel / 8;
+ } else {
+ info->fix.smem_start = oinfo->fb_base_phys;
+ info->fix.line_length =
+ (info->var.xres_virtual*info->var.bits_per_pixel)/8;
+ }
+
+ if (oinfo->rotation_support)
+ info->fix.smem_len = oinfo->vrfb_size;
+ else
+ info->fix.smem_len = oinfo->fb_size;
+
+ info->fix.type = FB_TYPE_PACKED_PIXELS;
+ info->fix.visual = ((var_to_depth(&info->var) <= 8) ?
+ FB_VISUAL_PSEUDOCOLOR: FB_VISUAL_TRUECOLOR);
+ info->fix.xpanstep = 0;
+ info->fix.ypanstep = 1;
+ if(oinfo->rotation_support)
+ info->fix.ypanstep = 0;
+ info->fix.ywrapstep = 0;
+ info->fix.line_length =
+ (info->var.xres_virtual*info->var.bits_per_pixel)/8;
+ info->fix.type_aux = 0;
+ info->fix.mmio_start = oinfo->mmio_base_phys;
+ info->fix.mmio_len = DSS_REG_SIZE;
+ info->fix.accel = FB_ACCEL_NONE;
+
+ /* Allocate the color map to the maximum size.
+ * Color depths greater than 8 bits are true color and use a 16-bit
+ * pseudo-palette instead of an actual palette, so the maximum color
+ * map size is 256 colors.
+ */
+
+ if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
+ printk(KERN_ERR FB_NAME ": cannot allocate color map\n");
+ goto put_dss;
+ }
+ if (omap24xxfb_check_var(&info->var, info)) {
+ printk(KERN_ERR FB_NAME ": invalid default video mode\n");
+ goto dealloc_cmap;
+ }
+
+ oinfo->timeout = HZ/5;
+
+ /* initialize the vsync wait queue */
+ init_waitqueue_head(&oinfo->vsync_wait);
+
+ /* install our interrupt service routine */
+ if (omap2_disp_register_isr(omap24xxfb_isr, oinfo,0)) {
+ printk(KERN_ERR FB_NAME
+ ": could not install interrupt service routine\n");
+ goto dealloc_cmap;
+ };
+#ifdef DEBUG
+ omap2_disp_register_isr(omap24xxfb_synclost_isr, oinfo,
+ DISPC_IRQSTATUS_SYNCLOSTDIGITAL);
+#endif
+
+ omap24xxfb_set_par(info);
+
+ if (register_framebuffer((struct fb_info *) oinfo) < 0) {
+ printk(KERN_ERR FB_NAME ": could not register framebuffer\n");
+ goto uninstall_isr;
+ }
+
+ printk(KERN_INFO FB_NAME ": fb%d frame buffer device %s\n",
+ info->node,
+ (oinfo->rotation_support) ? "(rotation support)" : "");
+
+ printk(KERN_INFO FB_NAME ": display mode %dx%dx%d",
+ info->var.xres, info->var.yres,
+ var_to_depth(&info->var));
+
+ if (oinfo->rotation_support)
+ printk("@%d ", info->var.rotate);
+
+ if (output_dev == OMAP2_OUTPUT_LCD){
+ printk(" hsync %dkHz vsync %dHz",
+ oinfo->hsync/1000, oinfo->vsync);
+ }
+ printk("\n");
+
+#ifdef DEBUG_VRFB
+ if (oinfo->rotation_support) {
+ printk("lines %d, width %d line_length %d \n",
+ info->var.yres, info->var.xres, info->fix.line_length);
+ test_vrfb_space(oinfo, info->var.yres, 0, info->var.xres*2,
+ info->fix.line_length);
+ test_vrfb_space(oinfo, info->var.yres, info->var.xres*2,
+ info->fix.line_length, info->fix.line_length);
+ }
+#endif
+ omap2_disp_save_initstate(OMAP_DSS_DISPC_GENERIC);
+ omap2_disp_save_initstate(OMAP2_GRAPHICS);
+ DBGLEAVE;
+ return 0;
+
+uninstall_isr:
+ free_irq(INT_24XX_DSS_IRQ, oinfo);
+
+
+dealloc_cmap:
+ fb_dealloc_cmap(&info->cmap);
+
+put_dss:
+
+ omap2_disp_release_layer(fb_out_layer);
+ omap2_disp_put_dss();
+ disable_backlight();
+ omap2_dss_rgb_disable();
+
+free_palette:
+ dma_free_coherent(NULL, sizeof(u32)*256, oinfo->palette,
+ oinfo->palette_phys);
+
+ if (!oinfo->rotation_support)
+ goto free_fb;
+unmap_rot:
+ if (oinfo->sms_rot_virt[0])
+ iounmap((void*)oinfo->sms_rot_virt[0]);
+ if (oinfo->sms_rot_virt[1])
+ iounmap((void*)oinfo->sms_rot_virt[1]);
+ if (oinfo->sms_rot_virt[2])
+ iounmap((void*)oinfo->sms_rot_virt[2]);
+ if (oinfo->sms_rot_virt[3])
+ iounmap((void*)oinfo->sms_rot_virt[3]);
+
+free_fb:
+ if (!oinfo->alloc_fb_mem)
+ iounmap((void*)oinfo->fb_base);
+ else
+ dma_free_coherent(NULL, oinfo->fb_size, (void *)oinfo->fb_base,
+ oinfo->fb_base_phys);
+unmap_mmio:
+ iounmap((void*)oinfo->mmio_base);
+
+ if (!oinfo->rotation_support)
+ goto release_fb;
+release_rot_270:
+ release_mem_region(oinfo->sms_rot_phy[0], oinfo->vrfb_size);
+release_rot_180:
+ release_mem_region(oinfo->sms_rot_phy[1], oinfo->vrfb_size);
+release_rot_90:
+ release_mem_region(oinfo->sms_rot_phy[2], oinfo->vrfb_size);
+release_rot_0:
+ release_mem_region(oinfo->sms_rot_phy[3], oinfo->vrfb_size);
+
+release_fb:
+ if (!oinfo->alloc_fb_mem)
+ release_mem_region(oinfo->fb_base_phys, oinfo->fb_size);
+
+release_mmio:
+ release_mem_region(oinfo->mmio_base_phys, DSS_REG_SIZE);
+
+free_par:
+ kfree(oinfo);
+ saved_oinfo = NULL;
+
+unregister_device:
+#ifdef CONFIG_DPM
+ dpm_unregister_scale(&omap24xxfb_pre_scale,SCALE_PRECHANGE);
+ dpm_unregister_scale(&omap24xxfb_post_scale,SCALE_POSTCHANGE);
+#endif
+ platform_device_unregister(&omap24xxfb_device);
+unregister_driver:
+ platform_driver_unregister(&omap24xxfb_driver);
+ DBGLEAVE;
+ return -ENODEV;
+}
+
+/*
+ * Cleanup
+ */
+static void __exit omap24xxfb_cleanup(void)
+{
+ struct omap24xxfb_info *oinfo = saved_oinfo;
+
+ DBGENTER;
+
+
+ if (!oinfo)
+ return;
+
+ if(unregister_framebuffer((struct fb_info *) oinfo) < 0)
+ printk(KERN_ERR "unregister framebuffer error\n");
+
+#ifdef CONFIG_DPM
+ dpm_unregister_scale(&omap24xxfb_pre_scale,SCALE_PRECHANGE);
+ dpm_unregister_scale(&omap24xxfb_post_scale,SCALE_POSTCHANGE);
+#endif
+ platform_device_unregister(&omap24xxfb_device);
+ platform_driver_unregister(&omap24xxfb_driver);
+
+
+ omap2_disp_put_dss();
+ omap2_disp_disable_layer(OMAP2_GRAPHICS);
+ omap2_disp_disable_layer(fb_out_layer);
+ disable_backlight();
+ omap2_dss_rgb_disable();
+
+ omap2_disp_release_layer(fb_out_layer);
+
+
+ /* uninstall isr */
+ free_irq(INT_24XX_DSS_IRQ, oinfo);
+
+ fb_dealloc_cmap(&oinfo->info.cmap);
+
+ dma_free_coherent(NULL, sizeof(u32)*256, oinfo->palette,
+ oinfo->palette_phys);
+
+ if (!oinfo->alloc_fb_mem)
+ iounmap((void*)oinfo->fb_base);
+ else
+ dma_free_coherent(NULL, oinfo->fb_size,
+ (void *)oinfo->fb_base, oinfo->fb_base_phys);
+ iounmap((void*)oinfo->mmio_base);
+
+ if (!oinfo->alloc_fb_mem)
+ release_mem_region(oinfo->fb_base_phys, oinfo->fb_size);
+
+ release_mem_region(oinfo->mmio_base_phys, DSS_REG_SIZE);
+
+ if (oinfo->rotation_support) {
+ iounmap((void*)oinfo->sms_rot_virt[0]);
+ iounmap((void*)oinfo->sms_rot_virt[1]);
+ iounmap((void*)oinfo->sms_rot_virt[2]);
+ iounmap((void*)oinfo->sms_rot_virt[3]);
+
+ release_mem_region(oinfo->sms_rot_phy[0], oinfo->vrfb_size);
+ release_mem_region(oinfo->sms_rot_phy[1], oinfo->vrfb_size);
+ release_mem_region(oinfo->sms_rot_phy[2], oinfo->vrfb_size);
+ release_mem_region(oinfo->sms_rot_phy[3], oinfo->vrfb_size);
+ }
+
+ kfree(oinfo);
+ saved_oinfo = NULL;
+
+
+ printk(KERN_DEBUG "Removed framebuffer module\n");
+ DBGLEAVE;
+}
+
+/*
+ * Modularization
+ */
+
+module_init(omap24xxfb_init);
+module_exit(omap24xxfb_cleanup);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/omap/omap_fb.h b/drivers/video/omap/omap_fb.h
new file mode 100644
index 0000000..42c1dad
--- /dev/null
+++ b/drivers/video/omap/omap_fb.h
@@ -0,0 +1,363 @@
+/*
+ * drivers/video/omap24xxfb.h
+ *
+ * Framebuffer driver for OMAP24xx display controller.
+ *
+ * Author: Andy Lowe (sou...@mvista.com)
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef OMAP24XXFB_H
+#define OMAP24XXFB_H
+
+/* physical memory map definitions */
+ /* display subsystem */
+#define DSS_REG_BASE 0x48050000
+#define DSS_REG_SIZE 0x00001000
+ /* display controller */
+#define DISPC_REG_OFFSET 0x00000400
+ /* remote framebuffer interface */
+#define RFBI_REG_OFFSET 0x00000800
+ /* video encoder */
+#define VENC_REG_OFFSET 0x00000C00
+
+/* define display subsystem register offsets */
+#define DSS_CONTROL 0x040
+#define DSS_PSA_LCD_REG_1 0x050
+#define DSS_PSA_LCD_REG_2 0x054
+#define DSS_PSA_VIDEO_REG 0x058
+#define DSS_STATUS 0x05C
+
+/* define display controller register offsets */
+#define DISPC_REVISION 0x000
+
+#define DISPC_SYSCONFIG 0x010
+#define DISPC_SYSSTATUS 0x014
+#define DISPC_IRQSTATUS 0x018
+#define DISPC_IRQENABLE 0x01C
+
+#define DISPC_CONTROL 0x040
+#define DISPC_CONFIG 0x044
+#define DISPC_CAPABLE 0x048
+#define DISPC_DEFAULT_COLOR0 0x04C
+#define DISPC_DEFAULT_COLOR1 0x050
+#define DISPC_TRANS_COLOR0 0x054
+#define DISPC_TRANS_COLOR1 0x058
+#define DISPC_LINE_STATUS 0x05C
+#define DISPC_LINE_NUMBER 0x060
+#define DISPC_TIMING_H 0x064
+#define DISPC_TIMING_V 0x068
+#define DISPC_POL_FREQ 0x06C
+#define DISPC_DIVISOR 0x070
+
+#define DISPC_SIZE_DIG 0x078
+#define DISPC_SIZE_LCD 0x07C
+#define DISPC_GFX_BA0 0x080
+#define DISPC_GFX_BA1 0x084
+#define DISPC_GFX_POSITION 0x088
+#define DISPC_GFX_SIZE 0x08C
+
+#define DISPC_GFX_ATTRIBUTES 0x0A0
+#define DISPC_GFX_FIFO_THRESHOLD 0x0A4
+#define DISPC_GFX_FIFO_SIZE 0x0A8
+#define DISPC_GFX_ROW_INC 0x0AC
+#define DISPC_GFX_PIXEL_INC 0x0B0
+#define DISPC_GFX_WINDOW_SKIP 0x0B4
+#define DISPC_GFX_TABLE_BA 0x0B8
+#define DISPC_VID1_BA0 0x0BC
+#define DISPC_VID1_BA1 0x0C0
+#define DISPC_VID1_POSITION 0x0C4
+#define DISPC_VID1_SIZE 0x0C8
+#define DISPC_VID1_ATTRIBUTES 0x0CC
+#define DISPC_VID1_FIFO_THRESHOLD 0x0D0
+#define DISPC_VID1_FIFO_SIZE 0x0D4
+#define DISPC_VID1_ROW_INC 0x0D8
+#define DISPC_VID1_PIXEL_INC 0x0DC
+#define DISPC_VID1_FIR 0x0E0
+#define DISPC_VID1_PICTURE_SIZE 0x0E4
+#define DISPC_VID1_ACCU0 0x0E8
+#define DISPC_VID1_ACCU1 0x0EC
+#define DISPC_VID1_FIR_COEF_H0 0x0F0
+#define DISPC_VID1_FIR_COEF_HV0 0x0F4
+#define DISPC_VID1_FIR_COEF_H1 0x0F8
+#define DISPC_VID1_FIR_COEF_HV1 0x0FC
+#define DISPC_VID1_FIR_COEF_H2 0x100
+#define DISPC_VID1_FIR_COEF_HV2 0x104
+#define DISPC_VID1_FIR_COEF_H3 0x108
+#define DISPC_VID1_FIR_COEF_HV3 0x10C
+#define DISPC_VID1_FIR_COEF_H4 0x110
+#define DISPC_VID1_FIR_COEF_HV4 0x114
+#define DISPC_VID1_FIR_COEF_H5 0x118
+#define DISPC_VID1_FIR_COEF_HV5 0x11C
+#define DISPC_VID1_FIR_COEF_H6 0x120
+#define DISPC_VID1_FIR_COEF_HV6 0x124
+#define DISPC_VID1_FIR_COEF_H7 0x128
+#define DISPC_VID1_FIR_COEF_HV7 0x12C
+#define DISPC_VID1_CONV_COEF0 0x130
+#define DISPC_VID1_CONV_COEF1 0x134
+#define DISPC_VID1_CONV_COEF2 0x138
+#define DISPC_VID1_CONV_COEF3 0x13C
+#define DISPC_VID1_CONV_COEF4 0x140
+
+#define DISPC_VID2_BA0 0x14C
+#define DISPC_VID2_BA1 0x150
+#define DISPC_VID2_POSITION 0x154
+#define DISPC_VID2_SIZE 0x158
+#define DISPC_VID2_ATTRIBUTES 0x15C
+#define DISPC_VID2_FIFO_THRESHOLD 0x160
+#define DISPC_VID2_FIFO_SIZE 0x164
+#define DISPC_VID2_ROW_INC 0x168
+#define DISPC_VID2_PIXEL_INC 0x16C
+#define DISPC_VID2_FIR 0x170
+#define DISPC_VID2_PICTURE_SIZE 0x174
+#define DISPC_VID2_ACCU0 0x178
+#define DISPC_VID2_ACCU1 0x17C
+#define DISPC_VID2_FIR_COEF_H0 0x180
+#define DISPC_VID2_FIR_COEF_HV0 0x184
+#define DISPC_VID2_FIR_COEF_H1 0x188
+#define DISPC_VID2_FIR_COEF_HV1 0x18C
+#define DISPC_VID2_FIR_COEF_H2 0x190
+#define DISPC_VID2_FIR_COEF_HV2 0x194
+#define DISPC_VID2_FIR_COEF_H3 0x198
+#define DISPC_VID2_FIR_COEF_HV3 0x19C
+#define DISPC_VID2_FIR_COEF_H4 0x1A0
+#define DISPC_VID2_FIR_COEF_HV4 0x1A4
+#define DISPC_VID2_FIR_COEF_H5 0x1A8
+#define DISPC_VID2_FIR_COEF_HV5 0x1AC
+#define DISPC_VID2_FIR_COEF_H6 0x1B0
+#define DISPC_VID2_FIR_COEF_HV6 0x1B4
+#define DISPC_VID2_FIR_COEF_H7 0x1B8
+#define DISPC_VID2_FIR_COEF_HV7 0x1BC
+#define DISPC_VID2_CONV_COEF0 0x1C0
+#define DISPC_VID2_CONV_COEF1 0x1C4
+#define DISPC_VID2_CONV_COEF2 0x1C8
+#define DISPC_VID2_CONV_COEF3 0x1CC
+#define DISPC_VID2_CONV_COEF4 0x1D0
+#define DISPC_DATA_CYCLE1 0x1D4
+#define DISPC_DATA_CYCLE2 0x1D8
+#define DISPC_DATA_CYCLE3 0x1DC
+
+/* Define bit fields within selected registers */
+#define DISPC_REVISION_MAJOR (15 << 4)
+#define DISPC_REVISION_MAJOR_SHIFT 4
+#define DISPC_REVISION_MINOR (15 << 0)
+#define DISPC_REVISION_MINOR_SHIFT 0
+
+#define DISPC_SYSCONFIG_MIDLEMODE (3 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_FSTANDBY (0 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_NSTANDBY (1 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY (2 << 12)
+#define DISPC_SYSCONFIG_SIDLEMODE (3 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3)
+#define DISPC_SYSCONFIG_SOFTRESET (1 << 1)
+#define DISPC_SYSCONFIG_AUTOIDLE (1 << 0)
+
+#define DISPC_SYSSTATUS_RESETDONE (1 << 0)
+
+#define DISPC_IRQSTATUS_SYNCLOST (1 << 14)
+#define DISPC_IRQSTATUS_VID2ENDWINDOW (1 << 13)
+#define DISPC_IRQSTATUS_VID2FIFOUNDERFLOW (1 << 12)
+#define DISPC_IRQSTATUS_VID1ENDWINDOW (1 << 11)
+#define DISPC_IRQSTATUS_VID1FIFOUNDERFLOW (1 << 10)
+#define DISPC_IRQSTATUS_OCPERROR (1 << 9)
+#define DISPC_IRQSTATUS_PALETTEGAMMALOADING (1 << 8)
+#define DISPC_IRQSTATUS_GFXENDWINDOW (1 << 7)
+#define DISPC_IRQSTATUS_GFXFIFOUNDERFLOW (1 << 6)
+#define DISPC_IRQSTATUS_PROGRAMMEDLINENUMBER (1 << 5)
+#define DISPC_IRQSTATUS_ACBIASCOUNTSTATUS (1 << 4)
+#define DISPC_IRQSTATUS_EVSYNC_ODD (1 << 3)
+#define DISPC_IRQSTATUS_EVSYNC_EVEN (1 << 2)
+#define DISPC_IRQSTATUS_VSYNC (1 << 1)
+#define DISPC_IRQSTATUS_FRAMEDONE (1 << 0)
+
+#define DISPC_IRQENABLE_SYNCLOST (1 << 14)
+#define DISPC_IRQENABLE_VID2ENDWINDOW (1 << 13)
+#define DISPC_IRQENABLE_VID2FIFOUNDERFLOW (1 << 12)
+#define DISPC_IRQENABLE_VID1ENDWINDOW (1 << 11)
+#define DISPC_IRQENABLE_VID1FIFOUNDERFLOW (1 << 10)
+#define DISPC_IRQENABLE_OCPERROR (1 << 9)
+#define DISPC_IRQENABLE_PALETTEGAMMALOADING (1 << 8)
+#define DISPC_IRQENABLE_GFXENDWINDOW (1 << 7)
+#define DISPC_IRQENABLE_GFXFIFOUNDERFLOW (1 << 6)
+#define DISPC_IRQENABLE_PROGRAMMEDLINENUMBER (1 << 5)
+#define DISPC_IRQENABLE_ACBIASCOUNTSTATUS (1 << 4)
+#define DISPC_IRQENABLE_EVSYNC_ODD (1 << 3)
+#define DISPC_IRQENABLE_EVSYNC_EVEN (1 << 2)
+#define DISPC_IRQENABLE_VSYNC (1 << 1)
+#define DISPC_IRQENABLE_FRAMEDONE (1 << 0)
+
+#define DISPC_CONTROL_TDMUNUSEDBITS (3 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_LOWLEVEL (0 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_HIGHLEVEL (1 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_UNCHANGED (2 << 25)
+#define DISPC_CONTROL_TDMCYCLEFORMAT (3 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_1CYCPERPIX (0 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_2CYCPERPIX (1 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPERPIX (2 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPER2PIX (3 << 23)
+#define DISPC_CONTROL_TDMPARALLELMODE (3 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_8BPARAINT (0 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_9BPARAINT (1 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_12BPARAINT (2 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_16BPARAINT (3 << 21)
+#define DISPC_CONTROL_TDMENABLE (1 << 20)
+#define DISPC_CONTROL_HT (7 << 17)
+#define DISPC_CONTROL_HT_SHIFT 17
+#define DISPC_CONTROL_GPOUT1 (1 << 16)
+#define DISPC_CONTROL_GPOUT0 (1 << 15)
+#define DISPC_CONTROL_GPIN1 (1 << 14)
+#define DISPC_CONTROL_GPIN0 (1 << 13)
+#define DISPC_CONTROL_OVERLAYOPTIMIZATION (1 << 12)
+#define DISPC_CONTROL_RFBIMODE (1 << 11)
+#define DISPC_CONTROL_SECURE (1 << 10)
+#define DISPC_CONTROL_TFTDATALINES (3 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB12B (0 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB16B (1 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB18B (2 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB24B (3 << 8)
+#define DISPC_CONTROL_TFTDITHERENABLE (1 << 7)
+#define DISPC_CONTROL_GODIGITAL (1 << 6)
+#define DISPC_CONTROL_GOLCD (1 << 5)
+#define DISPC_CONTROL_M8B (1 << 4)
+#define DISPC_CONTROL_STNTFT (1 << 3)
+#define DISPC_CONTROL_MONOCOLOR (1 << 2)
+#define DISPC_CONTROL_DIGITALENABLE (1 << 1)
+#define DISPC_CONTROL_LCDENABLE (1 << 0)
+
+#define DISPC_CONFIG_TCKDIGSELECTION (1 << 13)
+#define DISPC_CONFIG_TCKDIGENABLE (1 << 12)
+#define DISPC_CONFIG_TCKLCDSELECTION (1 << 11)
+#define DISPC_CONFIG_TCKLCDENABLE (1 << 10)
+#define DISPC_CONFIG_FUNCGATED (1 << 9)
+#define DISPC_CONFIG_ACBIASGATED (1 << 8)
+#define DISPC_CONFIG_VSYNCGATED (1 << 7)
+#define DISPC_CONFIG_HSYNCGATED (1 << 6)
+#define DISPC_CONFIG_PIXELCLOCKGATED (1 << 5)
+#define DISPC_CONFIG_PIXELDATAGATED (1 << 4)
+#define DISPC_CONFIG_PALETTEGAMMATABLE (1 << 3)
+#define DISPC_CONFIG_LOADMODE_FRDATLEFR (1 << 2)
+#define DISPC_CONFIG_LOADMODE_PGTABUSETB (1 << 1)
+#define DISPC_CONFIG_PIXELGATED (1 << 0)
+
+#define DISPC_CAPABLE_GFXGAMMATABLECAPABLE (1 << 9)
+#define DISPC_CAPABLE_GFXLAYERCAPABLE (1 << 8)
+#define DISPC_CAPABLE_GFXTRANSDSTCAPABLE (1 << 7)
+#define DISPC_CAPABLE_STNDITHERINGCAPABLE (1 << 6)
+#define DISPC_CAPABLE_TFTDITHERINGCAPABLE (1 << 5)
+#define DISPC_CAPABLE_VIDTRANSSRCCAPABLE (1 << 4)
+#define DISPC_CAPABLE_VIDLAYERCAPABLE (1 << 3)
+#define DISPC_CAPABLE_VIDVERTFIRCAPABLE (1 << 2)
+#define DISPC_CAPABLE_VIDHORFIRCAPABLE (1 << 1)
+#define DISPC_CAPABLE_VIDCAPABLE (1 << 0)
+
+#define DISPC_POL_FREQ_ONOFF (1 << 17)
+#define DISPC_POL_FREQ_RF (1 << 16)
+#define DISPC_POL_FREQ_IEO (1 << 15)
+#define DISPC_POL_FREQ_IPC (1 << 14)
+#define DISPC_POL_FREQ_IHS (1 << 13)
+#define DISPC_POL_FREQ_IVS (1 << 12)
+#define DISPC_POL_FREQ_ACBI (15 << 8)
+#define DISPC_POL_FREQ_ACBI_SHIFT 8
+#define DISPC_POL_FREQ_ACB 0xFF
+#define DISPC_POL_FREQ_ACB_SHIFT 0
+
+#define DISPC_TIMING_H_HBP (0xFF << 20)
+#define DISPC_TIMING_H_HBP_SHIFT 20
+#define DISPC_TIMING_H_HFP (0xFF << 8)
+#define DISPC_TIMING_H_HFP_SHIFT 8
+#define DISPC_TIMING_H_HSW (0x3F << 0)
+#define DISPC_TIMING_H_HSW_SHIFT 0
+
+#define DISPC_TIMING_V_VBP (0xFF << 20)
+#define DISPC_TIMING_V_VBP_SHIFT 20
+#define DISPC_TIMING_V_VFP (0xFF << 8)
+#define DISPC_TIMING_V_VFP_SHIFT 8
+#define DISPC_TIMING_V_VSW (0x3F << 0)
+#define DISPC_TIMING_V_VSW_SHIFT 0
+
+#define DISPC_DIVISOR_LCD (0xFF << 16)
+#define DISPC_DIVISOR_LCD_SHIFT 16
+#define DISPC_DIVISOR_PCD 0xFF
+#define DISPC_DIVISOR_PCD_SHIFT 0
+
+#define DISPC_SIZE_LCD_LPP (0x7FF << 16)
+#define DISPC_SIZE_LCD_LPP_SHIFT 16
+#define DISPC_SIZE_LCD_PPL 0x7FF
+#define DISPC_SIZE_LCD_PPL_SHIFT 0
+
+#define DISPC_SIZE_DIG_LPP (0x7FF << 16)
+#define DISPC_SIZE_DIG_LPP_SHIFT 16
+#define DISPC_SIZE_DIG_PPL 0x7FF
+#define DISPC_SIZE_DIG_PPL_SHIFT 0
+
+#define DISPC_GFX_POSITION_GFXPOSY (0x7FF << 16)
+#define DISPC_GFX_POSITION_GFXPOSY_SHIFT 16
+#define DISPC_GFX_POSITION_GFXPOSX 0x7FF
+#define DISPC_GFX_POSITION_GFXPOSX_SHIFT 0
+
+#define DISPC_GFX_SIZE_GFXSIZEY (0x7FF << 16)
+#define DISPC_GFX_SIZE_GFXSIZEY_SHIFT 16
+#define DISPC_GFX_SIZE_GFXSIZEX 0x7FF
+#define DISPC_GFX_SIZE_GFXSIZEX_SHIFT 0
+
+#define DISPC_GFX_ATTRIBUTES_GFXENDIANNESS (1 << 10)
+#define DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE (1 << 9)
+#define DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT (1 << 8)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE (3 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST4X32 (0 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST8X32 (1 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST16X32 (2 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE (1 << 5)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT (15 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1 (0 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2 (1 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4 (2 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8 (3 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12 (4 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16 (6 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24 (8 << 1)
+#define DISPC_GFX_ATTRIBUTES_ENABLE (1 << 0)
+
+#define DISPC_VID_ATTRIBUTES_ENABLE (1 << 0)
+
+/* define the custom FBIO_WAITFORVSYNC ioctl */
+#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t)
+/* define the custom FBIO_MIRROR ioctl */
+#define FBIO_MIRROR _IOW('F', 0x21, u_int32_t)
+
+#define CONFIG_LCD_IOCTL 1
+#ifdef CONFIG_LCD_IOCTL
+
+/* define the custom FBIO_LCD_PUT_SCREENINFO ioctl */
+#define FBIO_LCD_PUT_SCREENINFO _IOW('F', 0x22, struct omap_lcd_info)
+
+struct omap_lcd_info
+{
+ unsigned int pixclock; /* pixclocks */
+ unsigned int left_margin; /* pixclocks */
+ unsigned int right_margin; /* pixclocks */
+ unsigned int upper_margin; /* lineclocks */
+ unsigned int lower_margin; /* lineclocks */
+ unsigned int hsync_len; /* pixclocks */
+ unsigned int vsync_len; /* lineclocks */
+ unsigned int sync; /* hsync & vsync polarity */
+ unsigned int acb; /* AC-bias pin frequency */
+ unsigned int ipc; /* Invert pixel clock */
+ unsigned int onoff; /* HSYNC/VSYNC Pixel clk Control*/
+};
+
+extern int omap_lcd_init(struct omap_lcd_info *info);
+extern void omap2_dss_rgb_enable(void);
+extern void omap2_dss_rgb_disable(void);
+
+#endif
+
+#endif /* ifndef OMAP24XXFB_H */
diff --git a/include/asm-arm/arch-omap/bits.h
b/include/asm-arm/arch-omap/bits.h
new file mode 100644
index 0000000..ad483ed
--- /dev/null
+++ b/include/asm-arm/arch-omap/bits.h
@@ -0,0 +1,52 @@
+/*
+ * linux/include/asm-arm/arch-omap2/bits.h
+ *
+ * Definitions of Bit offsets
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __ASM_ARCH_OMAP2_BITS_H
+#define __ASM_ARCH_OMAP2_BITS_H
+
+#define BIT0 0x00000001
+#define BIT1 0x00000002
+#define BIT2 0x00000004
+#define BIT3 0x00000008
+#define BIT4 0x00000010
+#define BIT5 0x00000020
+#define BIT6 0x00000040
+#define BIT7 0x00000080
+#define BIT8 0x00000100
+#define BIT9 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif /* __ASM_ARCH_OMAP2_BITS_H */
diff --git a/include/asm-arm/arch-omap/display.h
b/include/asm-arm/arch-omap/display.h
new file mode 100644
index 0000000..53b40ff
--- /dev/null
+++ b/include/asm-arm/arch-omap/display.h
@@ -0,0 +1,816 @@
+/*
+ * include/asm-arm/arch-omap24xx/display.h
+ *
+ * Copyright (C) 2004-2005 Texas Instruments.
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+
+ * Leveraged from original Linux 2.6 framebuffer driver for OMAP24xx
+ * Author: Andy Lowe (sou...@mvista.com)
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP2_DISP_H
+#define __ASM_ARCH_OMAP2_DISP_H
+
+#include <linux/videodev.h>
+
+/*physical memory map definitions */
+ /* display subsystem */
+#define DSS_REG_BASE 0x48050000
+#define DSS_REG_SIZE 0x00001000
+ /* DSS */
+#define DSS_REG_OFFSET 0x00000000
+ /* display controller */
+#define DISPC_REG_OFFSET 0x00000400
+ /* remote framebuffer interface */
+#define RFBI_REG_OFFSET 0x00000800
+ /* video encoder */
+#define VENC_REG_OFFSET 0x00000C00
+
+/* display subsystem register offsets */
+#define DSS_REVISION 0x000
+#define DSS_SYSCONFIG 0x010
+#define DSS_SYSSTATUS 0x014
+#define DSS_CONTROL 0x040
+#ifdef CONFIG_ARCH_OMAP3430
+#define DSS_SDI_CONTROL 0x044 /* omap3430 specific */
+#define DSS_PLL_CONTROL 0x048 /* omap3430 specific */
+#endif /* CONFIG_ARCH_OMAP3430 */
+#define DSS_PSA_LCD_REG_1 0x050
+#define DSS_PSA_LCD_REG_2 0x054
+#define DSS_PSA_VIDEO_REG 0x058
+#define DSS_STATUS 0x05C
+
+/* display controller register offsets */
+#define DISPC_REVISION 0x000
+#define DISPC_SYSCONFIG 0x010
+#define DISPC_SYSSTATUS 0x014
+#define DISPC_IRQSTATUS 0x018
+#define DISPC_IRQENABLE 0x01C
+#define DISPC_CONTROL 0x040
+#define DISPC_CONFIG 0x044
+#define DISPC_CAPABLE 0x048
+#define DISPC_DEFAULT_COLOR0 0x04C
+#define DISPC_DEFAULT_COLOR1 0x050
+#define DISPC_TRANS_COLOR0 0x054
+#define DISPC_TRANS_COLOR1 0x058
+#define DISPC_LINE_STATUS 0x05C
+#define DISPC_LINE_NUMBER 0x060
+#define DISPC_TIMING_H 0x064
+#define DISPC_TIMING_V 0x068
+#define DISPC_POL_FREQ 0x06C
+#define DISPC_DIVISOR 0x070
+#define DISPC_GLOBAL_ALPHA 0x074
+#define DISPC_SIZE_DIG 0x078
+#define DISPC_SIZE_LCD 0x07C
+#define DISPC_GFX_BA0 0x080
+#define DISPC_GFX_BA1 0x084
+#define DISPC_GFX_POSITION 0x088
+#define DISPC_GFX_SIZE 0x08C
+#define DISPC_GFX_ATTRIBUTES 0x0A0
+#define DISPC_GFX_FIFO_THRESHOLD 0x0A4
+#define DISPC_GFX_FIFO_SIZE 0x0A8
+#define DISPC_GFX_ROW_INC 0x0AC
+#define DISPC_GFX_PIXEL_INC 0x0B0
+#define DISPC_GFX_WINDOW_SKIP 0x0B4
+#define DISPC_GFX_TABLE_BA 0x0B8
+
+#define RFBI_SYSCONFIG 0x010
+
+/* The registers for the video pipelines are parameterized by the video
pipeline
+ * index: n=0 for VID1 and n=1 for VID2.
+ */
+#define DISPC_VID_BA0(n) (0x0BC + (n)*0x90)
+#define DISPC_VID_BA1(n) (0x0C0 + (n)*0x90)
+#define DISPC_VID_POSITION(n) (0x0C4 + (n)*0x90)
+#define DISPC_VID_SIZE(n) (0x0C8 + (n)*0x90)
+#define DISPC_VID_ATTRIBUTES(n) (0x0CC + (n)*0x90)
+#define DISPC_VID_FIFO_THRESHOLD(n) (0x0D0 + (n)*0x90)
+#define DISPC_VID_FIFO_SIZE(n) (0x0D4 + (n)*0x90)
+#define DISPC_VID_ROW_INC(n) (0x0D8 + (n)*0x90)
+#define DISPC_VID_PIXEL_INC(n) (0x0DC + (n)*0x90)
+#define DISPC_VID_FIR(n) (0x0E0 + (n)*0x90)
+#define DISPC_VID_PICTURE_SIZE(n) (0x0E4 + (n)*0x90)
+#define DISPC_VID_ACCU0(n) (0x0E8 + (n)*0x90)
+#define DISPC_VID_ACCU1(n) (0x0EC + (n)*0x90)
+
+/* The FIR coefficients are parameterized by the video pipeline index n = {0,
1}
+ * and the coefficient index i = {0, 1, 2, 3, 4, 5, 6, 7}.
+ */
+#define DISPC_VID_FIR_COEF_H(n, i) (0x0F0 + (i)*0x8 + (n)*0x90)
+#define DISPC_VID_FIR_COEF_HV(n, i) (0x0F4 + (i)*0x8 + (n)*0x90)
+#define DISPC_VID_CONV_COEF0(n) (0x130 + (n)*0x90)
+#define DISPC_VID_CONV_COEF1(n) (0x134 + (n)*0x90)
+#define DISPC_VID_CONV_COEF2(n) (0x138 + (n)*0x90)
+#define DISPC_VID_CONV_COEF3(n) (0x13C + (n)*0x90)
+#define DISPC_VID_CONV_COEF4(n) (0x140 + (n)*0x90)
+
+#define DISPC_DATA_CYCLE1 0x1D4
+#define DISPC_DATA_CYCLE2 0x1D8
+#define DISPC_DATA_CYCLE3 0x1DC
+
+/* bit fields within selected registers */
+#define DSS_CONTROL_VENC_OUT (1 << 6)
+#define DSS_CONTROL_TV_REF (1 << 5)
+#define DSS_CONTROL_DAC_DEMEN (1 << 4)
+#define DSS_CONTROL_VENC_CLOCK_4X_ENABLE (1 << 3)
+#define DSS_CONTROL_VENC_CLOCK_MODE (1 << 2)
+#define DSS_CONTROL_CLK (1 << 0)
+#define DSS_CONTROL_APLL_CLK 1
+#define DSS_CONTROL_DPLL_CLK 0
+#define DSS_SYSCONFIG_SOFTRESET (1 << 1)
+#define DSS_SYSSTATUS_RESETDONE (1 << 0)
+#define DSS_SYSCONFIG_SIDLEMODE (3 << 3)
+#define DSS_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3)
+#define DSS_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3)
+#define DSS_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3)
+#define DSS_SYSCONFIG_SOFTRESET (1 << 1)
+#define DSS_SYSCONFIG_AUTOIDLE (1 << 0)
+
+#define DISPC_REVISION_MAJOR (15 << 4)
+#define DISPC_REVISION_MAJOR_SHIFT 4
+#define DISPC_REVISION_MINOR (15 << 0)
+#define DISPC_REVISION_MINOR_SHIFT 0
+
+#define DISPC_SYSCONFIG_MIDLEMODE (3 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_FSTANDBY (0 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_NSTANDBY (1 << 12)
+#define DISPC_SYSCONFIG_MIDLEMODE_SSTANDBY (2 << 12)
+#define DISPC_SYSCONFIG_SIDLEMODE (3 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_FIDLE (0 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_NIDLE (1 << 3)
+#define DISPC_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3)
+#define DISPC_SYSCONFIG_SOFTRESET (1 << 1)
+#define DISPC_SYSCONFIG_AUTOIDLE (1 << 0)
+#define DISPC_SYSCONFIG_CLKACTIVITY (2 << 8)
+#define DISPC_SYSCONFIG_ENABLE_WKUP (1 << 2)
+
+#define DISPC_SYSSTATUS_RESETDONE (1 << 0)
+
+#define DISPC_IRQSTATUS_SYNCLOSTDIGITAL (1 << 15)
+#define DISPC_IRQSTATUS_SYNCLOST (1 << 14)
+#define DISPC_IRQSTATUS_VID2ENDWINDOW (1 << 13)
+#define DISPC_IRQSTATUS_VID2FIFOUNDERFLOW (1 << 12)
+#define DISPC_IRQSTATUS_VID1ENDWINDOW (1 << 11)
+#define DISPC_IRQSTATUS_VID1FIFOUNDERFLOW (1 << 10)
+#define DISPC_IRQSTATUS_OCPERROR (1 << 9)
+#define DISPC_IRQSTATUS_PALETTEGAMMALOADING (1 << 8)
+#define DISPC_IRQSTATUS_GFXENDWINDOW (1 << 7)
+#define DISPC_IRQSTATUS_GFXFIFOUNDERFLOW (1 << 6)
+#define DISPC_IRQSTATUS_PROGRAMMEDLINENUMBER (1 << 5)
+#define DISPC_IRQSTATUS_ACBIASCOUNTSTATUS (1 << 4)
+#define DISPC_IRQSTATUS_EVSYNC_ODD (1 << 3)
+#define DISPC_IRQSTATUS_EVSYNC_EVEN (1 << 2)
+#define DISPC_IRQSTATUS_VSYNC (1 << 1)
+#define DISPC_IRQSTATUS_FRAMEDONE (1 << 0)
+
+#define DISPC_IRQENABLE_SYNCLOSTDIGITAL (1 << 15)
+#define DISPC_IRQENABLE_SYNCLOST (1 << 14)
+#define DISPC_IRQENABLE_VID2ENDWINDOW (1 << 13)
+#define DISPC_IRQENABLE_VID2FIFOUNDERFLOW (1 << 12)
+#define DISPC_IRQENABLE_VID1ENDWINDOW (1 << 11)
+#define DISPC_IRQENABLE_VID1FIFOUNDERFLOW (1 << 10)
+#define DISPC_IRQENABLE_OCPERROR (1 << 9)
+#define DISPC_IRQENABLE_PALETTEGAMMALOADING (1 << 8)
+#define DISPC_IRQENABLE_GFXENDWINDOW (1 << 7)
+#define DISPC_IRQENABLE_GFXFIFOUNDERFLOW (1 << 6)
+#define DISPC_IRQENABLE_PROGRAMMEDLINENUMBER (1 << 5)
+#define DISPC_IRQENABLE_ACBIASCOUNTSTATUS (1 << 4)
+#define DISPC_IRQENABLE_EVSYNC_ODD (1 << 3)
+#define DISPC_IRQENABLE_EVSYNC_EVEN (1 << 2)
+#define DISPC_IRQENABLE_VSYNC (1 << 1)
+#define DISPC_IRQENABLE_FRAMEDONE (1 << 0)
+
+#define DISPC_CONTROL_TDMUNUSEDBITS (3 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_LOWLEVEL (0 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_HIGHLEVEL (1 << 25)
+#define DISPC_CONTROL_TDMUNUSEDBITS_UNCHANGED (2 << 25)
+#define DISPC_CONTROL_TDMCYCLEFORMAT (3 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_1CYCPERPIX (0 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_2CYCPERPIX (1 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPERPIX (2 << 23)
+#define DISPC_CONTROL_TDMCYCLEFORMAT_3CYCPER2PIX (3 << 23)
+#define DISPC_CONTROL_TDMPARALLELMODE (3 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_8BPARAINT (0 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_9BPARAINT (1 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_12BPARAINT (2 << 21)
+#define DISPC_CONTROL_TDMPARALLELMODE_16BPARAINT (3 << 21)
+#define DISPC_CONTROL_TDMENABLE (1 << 20)
+#define DISPC_CONTROL_HT (7 << 17)
+#define DISPC_CONTROL_HT_SHIFT 17
+#define DISPC_CONTROL_GPOUT1 (1 << 16)
+#define DISPC_CONTROL_GPOUT0 (1 << 15)
+#define DISPC_CONTROL_GPIN1 (1 << 14)
+#define DISPC_CONTROL_GPIN0 (1 << 13)
+#define DISPC_CONTROL_OVERLAYOPTIMIZATION (1 << 12)
+#define DISPC_CONTROL_RFBIMODE (1 << 11)
+#define DISPC_CONTROL_SECURE (1 << 10)
+#define DISPC_CONTROL_TFTDATALINES (3 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB12B (0 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB16B (1 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB18B (2 << 8)
+#define DISPC_CONTROL_TFTDATALINES_OALSB24B (3 << 8)
+#define DISPC_CONTROL_TFTDITHERENABLE (1 << 7)
+#define DISPC_CONTROL_GODIGITAL (1 << 6)
+#define DISPC_CONTROL_GOLCD (1 << 5)
+#define DISPC_CONTROL_M8B (1 << 4)
+#define DISPC_CONTROL_STNTFT (1 << 3)
+#define DISPC_CONTROL_MONOCOLOR (1 << 2)
+#define DISPC_CONTROL_DIGITALENABLE (1 << 1)
+#define DISPC_CONTROL_LCDENABLE (1 << 0)
+
+#define DISPC_CONFIG_TVALPHAENABLE (1 << 19)
+#define DISPC_CONFIG_LCDALPHAENABLE (1 << 18)
+#ifdef CONFIG_ARCH_OMAP3430
+#define DISPC_CONFIG_FIFOMERGE (1 << 14)
+#endif
+#define DISPC_CONFIG_TCKDIGSELECTION (1 << 13)
+#define DISPC_CONFIG_TCKDIGENABLE (1 << 12)
+#define DISPC_CONFIG_TCKLCDSELECTION (1 << 11)
+#define DISPC_CONFIG_TCKLCDENABLE (1 << 10)
+#define DISPC_CONFIG_FUNCGATED (1 << 9)
+#define DISPC_CONFIG_ACBIASGATED (1 << 8)
+#define DISPC_CONFIG_VSYNCGATED (1 << 7)
+#define DISPC_CONFIG_HSYNCGATED (1 << 6)
+#define DISPC_CONFIG_PIXELCLOCKGATED (1 << 5)
+#define DISPC_CONFIG_PIXELDATAGATED (1 << 4)
+#define DISPC_CONFIG_PALETTEGAMMATABLE (1 << 3)
+#define DISPC_CONFIG_LOADMODE_FRDATLEFR (1 << 2)
+#define DISPC_CONFIG_LOADMODE_PGTABUSETB (1 << 1)
+#define DISPC_CONFIG_PIXELGATED (1 << 0)
+
+#define DISPC_CAPABLE_GFXGAMMATABLECAPABLE (1 << 9)
+#define DISPC_CAPABLE_GFXLAYERCAPABLE (1 << 8)
+#define DISPC_CAPABLE_GFXTRANSDSTCAPABLE (1 << 7)
+#define DISPC_CAPABLE_STNDITHERINGCAPABLE (1 << 6)
+#define DISPC_CAPABLE_TFTDITHERINGCAPABLE (1 << 5)
+#define DISPC_CAPABLE_VIDTRANSSRCCAPABLE (1 << 4)
+#define DISPC_CAPABLE_VIDLAYERCAPABLE (1 << 3)
+#define DISPC_CAPABLE_VIDVERTFIRCAPABLE (1 << 2)
+#define DISPC_CAPABLE_VIDHORFIRCAPABLE (1 << 1)
+#define DISPC_CAPABLE_VIDCAPABLE (1 << 0)
+
+#define DISPC_POL_FREQ_ONOFF_SHIFT 17
+#define DISPC_POL_FREQ_ONOFF (1 << 17)
+#define DISPC_POL_FREQ_RF (1 << 16)
+#define DISPC_POL_FREQ_IEO (1 << 15)
+#define DISPC_POL_FREQ_IPC_SHIFT 14
+#define DISPC_POL_FREQ_IPC (1 << 14)
+#define DISPC_POL_FREQ_IHS (1 << 13)
+#define DISPC_POL_FREQ_IVS (1 << 12)
+#define DISPC_POL_FREQ_ACBI (15 << 8)
+#define DISPC_POL_FREQ_ACBI_SHIFT 8
+#define DISPC_POL_FREQ_ACB 0xFF
+#define DISPC_POL_FREQ_ACB_SHIFT 0
+
+#define DISPC_TIMING_H_HBP (0xFF << 20)
+#define DISPC_TIMING_H_HBP_SHIFT 20
+#define DISPC_TIMING_H_HFP (0xFF << 8)
+#define DISPC_TIMING_H_HFP_SHIFT 8
+#define DISPC_TIMING_H_HSW (0x3F << 0)
+#define DISPC_TIMING_H_HSW_SHIFT 0
+
+#define DISPC_TIMING_V_VBP (0xFF << 20)
+#define DISPC_TIMING_V_VBP_SHIFT 20
+#define DISPC_TIMING_V_VFP (0xFF << 8)
+#define DISPC_TIMING_V_VFP_SHIFT 8
+#define DISPC_TIMING_V_VSW (0x3F << 0)
+#define DISPC_TIMING_V_VSW_SHIFT 0
+
+#define DISPC_DIVISOR_LCD (0xFF << 16)
+#define DISPC_DIVISOR_LCD_SHIFT 16
+#define DISPC_DIVISOR_PCD 0xFF
+#define DISPC_DIVISOR_PCD_SHIFT 0
+
+#define DISPC_GLOBAL_ALPHA_VID2_GALPHA (0xFF << 16)
+#define DISPC_GLOBAL_ALPHA_VID2_GALPHA_SHIFT 16
+#define DISPC_GLOBAL_ALPHA_GFX_GALPHA 0xFF
+#define DISPC_GLOBAL_ALPHA_GFX_GALPHA_SHIFT 0
+
+#define DISPC_SIZE_LCD_LPP (0x7FF << 16)
+#define DISPC_SIZE_LCD_LPP_SHIFT 16
+#define DISPC_SIZE_LCD_PPL 0x7FF
+#define DISPC_SIZE_LCD_PPL_SHIFT 0
+
+
+#define DISPC_SIZE_DIG_LPP (0x7FF << 16)
+#define DISPC_SIZE_DIG_LPP_SHIFT 16
+#define DISPC_SIZE_DIG_PPL 0x7FF
+#define DISPC_SIZE_DIG_PPL_SHIFT 0
+
+#define DISPC_GFX_POSITION_GFXPOSY (0x7FF << 16)
+#define DISPC_GFX_POSITION_GFXPOSY_SHIFT 16
+#define DISPC_GFX_POSITION_GFXPOSX 0x7FF
+#define DISPC_GFX_POSITION_GFXPOSX_SHIFT 0
+
+#define DISPC_GFX_SIZE_GFXSIZEY (0x7FF << 16)
+#define DISPC_GFX_SIZE_GFXSIZEY_SHIFT 16
+#define DISPC_GFX_SIZE_GFXSIZEX 0x7FF
+#define DISPC_GFX_SIZE_GFXSIZEX_SHIFT 0
+
+#define DISPC_GFX_ATTRIBUTES_GFXENDIANNESS (1 << 10)
+#define DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE (1 << 9)
+#define DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT (1 << 8)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE (3 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST4X32 (0 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST8X32 (1 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_BURST16X32 (2 << 6)
+#define DISPC_GFX_ATTRIBUTES_GFXREPLICATIONENABLE (1 << 5)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT (15 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP1 (0 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP2 (1 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP4 (2 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_BITMAP8 (3 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB12 (4 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB16 (6 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGB24 (8 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_ARGB32 (12 << 1)
+#define DISPC_GFX_ATTRIBUTES_GFXFORMAT_RGBA32 (13 << 1)
+#define DISPC_GFX_ATTRIBUTES_ENABLE (1 << 0)
+#define DISPC_GFX_ATTRIBUTES_GFXREPEN 5
+
+#ifdef CONFIG_ARCH_OMAP3430
+#define DISPC_GFX_FIFO_THRESHOLD_HIGH (0xFFF << 16)
+#define DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT 16
+#define DISPC_GFX_FIFO_THRESHOLD_LOW 0xFFF
+#define DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT 0
+#else
+#define DISPC_GFX_FIFO_THRESHOLD_HIGH (0x1FF << 16)
+#define DISPC_GFX_FIFO_THRESHOLD_HIGH_SHIFT 16
+#define DISPC_GFX_FIFO_THRESHOLD_LOW 0x1FF
+#define DISPC_GFX_FIFO_THRESHOLD_LOW_SHIFT 0
+#endif /* CONFIG_ARCH_OMAP3430 */
+
+#define DISPC_VID_POSITION_VIDPOSY (0x7FF << 16)
+#define DISPC_VID_POSITION_VIDPOSY_SHIFT 16
+#define DISPC_VID_POSITION_VIDPOSX 0x7FF
+#define DISPC_VID_POSITION_VIDPOSX_SHIFT 0
+
+#define DISPC_VID_SIZE_VIDSIZEY (0x7FF << 16)
+#define DISPC_VID_SIZE_VIDSIZEY_SHIFT 16
+#define DISPC_VID_SIZE_VIDSIZEX 0x7FF
+#define DISPC_VID_SIZE_VIDSIZEX_SHIFT 0
+
+#define DISPC_VID_ATTRIBUTES_VIDROWREPEATENABLE (1 << 18)
+#define DISPC_VID_ATTRIBUTES_VIDENDIANNESS (1 << 17)
+#define DISPC_VID_ATTRIBUTES_VIDCHANNELOUT (1 << 16)
+#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE (3 << 14)
+#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST4X32 (0 << 14)
+#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST8X32 (1 << 14)
+#define DISPC_VID_ATTRIBUTES_VIDBURSTSIZE_BURST16X32 (2 << 14)
+#define DISPC_VID_ATTRIBUTES_VIDROTATION(n) ((n) << 12)
+#define DISPC_VID_ATTRIBUTES_VIDFULLRANGE (1 << 11)
+#define DISPC_VID_ATTRIBUTES_VIDREPLICATIONENABLE (1 << 10)
+#define DISPC_VID_ATTRIBUTES_VIDCOLORCONVENABLE (1 << 9)
+#define DISPC_VID_ATTRIBUTES_VIDVRESIZECONF (1 << 8)
+#define DISPC_VID_ATTRIBUTES_VIDHRESIZECONF (1 << 7)
+#define DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_VRESIZE (1 << 6)
+#define DISPC_VID_ATTRIBUTES_VIDRESIZEENABLE_HRESIZE (1 << 5)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT (15 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB16 (6 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB24 (8 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_RGB24P (9 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_YUV2 (10 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_UYVY (11 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_ARGB32 (12 << 1)
+#define DISPC_VID_ATTRIBUTES_VIDFORMAT_RGBA32 (13 << 1)
+#define DISPC_VID_ATTRIBUTES_ENABLE (1 << 0)
+
+#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEY (0x7FF << 16)
+#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEY_SHIFT 16
+#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEX 0x7FF
+#define DISPC_VID_PICTURE_SIZE_VIDORGSIZEX_SHIFT 0
+
+#define DISPC_VID_ATTRIBUTES_VIDROT 12
+#define DISPC_VID_ATTRIBUTES_VIDROWREPEAT 18
+
+/*RFBI Sysconfig values */
+#define RFBI_SYSCONFIG_SIDLEMODE_SIDLE (2 << 3)
+
+/* VENC register offsets */
+#define VENC_F_CONTROL 0x0008
+#define VENC_VIDOUT_CTRL 0x0010
+#define VENC_SYNC_CONTROL 0x0014
+#define VENC_LLEN 0x001C
+#define VENC_FLENS 0x0020
+#define VENC_HFLTR_CTRL 0x0024
+#define VENC_CC_CARR_WSS_CARR 0x0028
+#define VENC_C_PHASE 0x002C
+#define VENC_GAIN_U 0x0030
+#define VENC_GAIN_V 0x0034
+#define VENC_GAIN_Y 0x0038
+#define VENC_BLACK_LEVEL 0x003C
+#define VENC_BLANK_LEVEL 0x0040
+#define VENC_X_COLOR 0x0044
+#define VENC_M_CONTROL 0x0048
+#define VENC_BSTAMP_WSS_DATA 0x004C
+#define VENC_S_CARR 0x0050
+#define VENC_LINE21 0x0054
+#define VENC_LN_SEL 0x0058
+#define VENC_L21_WC_CTL 0x005C
+#define VENC_HTRIGGER_VTRIGGER 0x0060
+#define VENC_SAVID_EAVID 0x0064
+#define VENC_FLEN_FAL 0x0068
+#define VENC_LAL_PHASE_RESET 0x006C
+#define VENC_HS_INT_START_STOP_X 0x0070
+#define VENC_HS_EXT_START_STOP_X 0x0074
+#define VENC_VS_INT_START_X 0x0078
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y 0x007C
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X 0x0080
+#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y 0x0084
+#define VENC_VS_EXT_STOP_Y 0x0088
+#define VENC_AVID_START_STOP_X 0x0090
+#define VENC_AVID_START_STOP_Y 0x0094
+#define VENC_FID_INT_START_X_FID_INT_START_Y 0x00A0
+#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X 0x00A4
+#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y 0x00A8
+#define VENC_TVDETGP_INT_START_STOP_X 0x00B0
+#define VENC_TVDETGP_INT_START_STOP_Y 0x00B4
+#define VENC_GEN_CTRL 0x00B8
+#define VENC_DAC_TST 0x00C4
+#define VENC_DAC 0x00C8
+
+/* VENC bit fields */
+#define VENC_FCONTROL_RESET (1<<8)
+
+/* Rotation using VRFB */
+#define SMS_ROT_VIRT_BASE(context, degree) 0x70000000 \
+ | 0x4000000 * (context) \
+ | 0x1000000 * (degree/90)
+#define SMS_IMAGEHEIGHT_OFFSET 16
+#define SMS_IMAGEWIDTH_OFFSET 0
+#define SMS_PH_OFFSET 8
+#define SMS_PW_OFFSET 4
+#define SMS_PS_OFFSET 0
+
+#ifdef CONFIG_ARCH_OMAP2420
+#define OMAP_SMS_BASE (L3_24XX_BASE + 0x8000)
+#endif
+#ifdef CONFIG_ARCH_OMAP2430
+#define OMAP_SMS_BASE OMAP243X_SMS_PHYS
+#endif
+#ifdef CONFIG_ARCH_OMAP3430
+#define OMAP_SMS_BASE SMS_PHYS
+#endif
+
+#define SMS_ROT0_PHYSICAL_BA(context) *(unsigned int *)((void *)
(OMAP_SMS_BASE + 0x188 \
+ + 0x10 * context))
+#define SMS_ROT_CONTROL(context) *(unsigned int *)((void *)(OMAP_SMS_BASE +
0x180 \
+ + 0x10 * context))
+#define SMS_ROT0_SIZE(context) *(unsigned int *)((void *)(OMAP_SMS_BASE +
0x184 \
+ + 0x10 * context))
+
+/* Structure to store and restore the DSS registers */
+struct omap24xx_dispc_regs
+{
+ u32 revision; /* 0x000 */
+ u32 res1[3];
+ u32 sysconfig; /* 0x010 */
+ u32 sysstatus; /* 0x014 */
+ u32 irqstatus; /* 0x018 */
+ u32 irqenable; /* 0x01C */
+ u32 res2[8];
+ u32 control; /* 0x040 */
+ u32 config; /* 0x044 */
+ u32 capable; /* 0x048 */
+ u32 default_color0; /* 0x04C */
+ u32 default_color1; /* 0x050 */
+ u32 trans_color0; /* 0x054 */
+ u32 trans_color1; /* 0x058 */
+ u32 line_status; /* 0x05C */
+ u32 line_number; /* 0x060 */
+ u32 timing_h; /* 0x064 */
+ u32 timing_v; /* 0x068 */
+ u32 pol_freq; /* 0x06C */
+ u32 divisor; /* 0x070 */
+ u32 res3[1];
+ u32 size_dig; /* 0x078 */
+ u32 size_lcd; /* 0x07C */
+ u32 gfx_ba0; /* 0x080 */
+ u32 gfx_ba1; /* 0x084 */
+ u32 gfx_position; /* 0x088 */
+ u32 gfx_size; /* 0x08C */
+ u32 res4[4];
+ u32 gfx_attributes; /* 0x0A0 */
+ u32 gfx_fifo_threshold; /* 0x0A4 */
+ u32 gfx_fifo_size; /* 0x0A8 */
+ u32 gfx_row_inc; /* 0x0AC */
+ u32 gfx_pixel_inc; /* 0x0B0 */
+ u32 gfx_window_skip; /* 0x0B4 */
+ u32 gfx_table_ba; /* 0x0B8 */
+ u32 vid1_ba0; /* 0x0BC */
+ u32 vid1_ba1; /* 0x0C0 */
+ u32 vid1_position; /* 0x0C4 */
+ u32 vid1_size; /* 0x0C8 */
+ u32 vid1_attributes; /* 0x0CC */
+ u32 vid1_fifo_threshold; /* 0x0D0 */
+ u32 vid1_fifo_size; /* 0x0D4 */
+ u32 vid1_row_inc; /* 0x0D8 */
+ u32 vid1_pixel_inc; /* 0x0DC */
+ u32 vid1_fir; /* 0x0E0 */
+ u32 vid1_picture_size; /* 0x0E4 */
+ u32 vid1_accu0; /* 0x0E8 */
+ u32 vid1_accu1; /* 0x0EC */
+ u32 vid1_fir_coef_h0; /* 0x0F0 */
+ u32 vid1_fir_coef_hv0; /* 0x0F4 */
+ u32 vid1_fir_coef_h1; /* 0x0F8 */
+ u32 vid1_fir_coef_hv1; /* 0x0FC */
+ u32 vid1_fir_coef_h2; /* 0x100 */
+ u32 vid1_fir_coef_hv2; /* 0x104 */
+ u32 vid1_fir_coef_h3; /* 0x108 */
+ u32 vid1_fir_coef_hv3; /* 0x10C */
+ u32 vid1_fir_coef_h4; /* 0x110 */
+ u32 vid1_fir_coef_hv4; /* 0x114 */
+ u32 vid1_fir_coef_h5; /* 0x118 */
+ u32 vid1_fir_coef_hv5; /* 0x11C */
+ u32 vid1_fir_coef_h6; /* 0x120 */
+ u32 vid1_fir_coef_hv6; /* 0x124 */
+ u32 vid1_fir_coef_h7; /* 0x128 */
+ u32 vid1_fir_coef_hv7; /* 0x12C */
+ u32 vid1_conv_coef0; /* 0x130 */
+ u32 vid1_conv_coef1; /* 0x134 */
+ u32 vid1_conv_coef2; /* 0x138 */
+ u32 vid1_conv_coef3; /* 0x13C */
+ u32 vid1_conv_coef4; /* 0x140 */
+ u32 res5[2];
+ u32 vid2_ba0; /* 0x14C */
+ u32 vid2_ba1; /* 0x150 */
+ u32 vid2_position; /* 0x154 */
+ u32 vid2_size; /* 0x158 */
+ u32 vid2_attributes; /* 0x15C */
+ u32 vid2_fifo_threshold; /* 0x160 */
+ u32 vid2_fifo_size; /* 0x164 */
+ u32 vid2_row_inc; /* 0x168 */
+ u32 vid2_pixel_inc; /* 0x16C */
+ u32 vid2_fir; /* 0x170 */
+ u32 vid2_picture_size; /* 0x174 */
+ u32 vid2_accu0; /* 0x178 */
+ u32 vid2_accu1; /* 0x17C */
+ u32 vid2_fir_coef_h0; /* 0x180 */
+ u32 vid2_fir_coef_hv0; /* 0x184 */
+ u32 vid2_fir_coef_h1; /* 0x188 */
+ u32 vid2_fir_coef_hv1; /* 0x18C */
+ u32 vid2_fir_coef_h2; /* 0x190 */
+ u32 vid2_fir_coef_hv2; /* 0x194 */
+ u32 vid2_fir_coef_h3; /* 0x198 */
+ u32 vid2_fir_coef_hv3; /* 0x19C */
+ u32 vid2_fir_coef_h4; /* 0x1A0 */
+ u32 vid2_fir_coef_hv4; /* 0x1A4 */
+ u32 vid2_fir_coef_h5; /* 0x1A8 */
+ u32 vid2_fir_coef_hv5; /* 0x1AC */
+ u32 vid2_fir_coef_h6; /* 0x1B0 */
+ u32 vid2_fir_coef_hv6; /* 0x1B4 */
+ u32 vid2_fir_coef_h7; /* 0x1B8 */
+ u32 vid2_fir_coef_hv7; /* 0x1BC */
+ u32 vid2_conv_coef0; /* 0x1C0 */
+ u32 vid2_conv_coef1; /* 0x1C4 */
+ u32 vid2_conv_coef2; /* 0x1C8 */
+ u32 vid2_conv_coef3; /* 0x1CC */
+ u32 vid2_conv_coef4; /* 0x1D0 */
+ u32 data_cycle1; /* 0x1D4 */
+ u32 data_cycle2; /* 0x1D8 */
+ u32 data_cycle3; /* 0x1DC */
+#ifdef CONFIG_ARCH_OMAP3430
+ /* omap3430 specific registers */
+ u32 vid1_fir_coef_v0; /* 0x1E0 */
+ u32 vid1_fir_coef_v1; /* 0x1E4 */
+ u32 vid1_fir_coef_v2; /* 0x1E8 */
+ u32 vid1_fir_coef_v3; /* 0x1EC */
+ u32 vid1_fir_coef_v4; /* 0x1F0 */
+ u32 vid1_fir_coef_v5; /* 0x1F4 */
+ u32 vid1_fir_coef_v6; /* 0x1F8 */
+ u32 vid1_fir_coef_v7; /* 0x1FC */
+ u32 vid2_fir_coef_v0; /* 0x200 */
+ u32 vid2_fir_coef_v1; /* 0x204 */
+ u32 vid2_fir_coef_v2; /* 0x208 */
+ u32 vid2_fir_coef_v3; /* 0x20C */
+ u32 vid2_fir_coef_v4; /* 0x210 */
+ u32 vid2_fir_coef_v5; /* 0x214 */
+ u32 vid2_fir_coef_v6; /* 0x218 */
+ u32 vid2_fir_coef_v7; /* 0x21C */
+ u32 cpr_coef_r; /* 0x220 */
+ u32 cpr_coef_g; /* 0x224 */
+ u32 cpr_coef_b; /* 0x228 */
+ u32 gfx_preload; /* 0x22C */
+ u32 vid1_preload; /* 0x230 */
+ u32 vid2_preload; /* 0x234 */
+#endif /* CONFIG_ARCH_OMAP3430 */
+};
+
+/* WARN: read-only registers omitted! */
+struct omap_dss_regs {
+ u32 sysconfig;
+ u32 control;
+#ifdef CONFIG_ARCH_OMAP3430
+ u32 sdi_control;
+ u32 pll_control;
+#endif
+ struct omap24xx_dispc_regs dispc;
+};
+
+struct tvlcd_status_t {
+ int ltype;
+ int output_dev;
+ int status;
+};
+
+/* color space conversion matrices */
+const static short int cc_bt601[3][3] = { {298, 409, 0},
+{298, -208, -100},
+{298, 0, 517}
+};
+const static short int cc_bt709[3][3] = { {298, 459, 0},
+{298, -137, -55},
+{298, 0, 541}
+};
+const static short int cc_bt601_full[3][3] = { {256, 351, 0},
+{256, -179, -86},
+{256, 0, 443}
+};
+
+/*----------- following are exposed values and APIs
-------------------------*/
+
+#define OMAP2_GRAPHICS 0
+#define OMAP2_VIDEO1 1
+#define OMAP2_VIDEO2 2
+#define OMAP_DSS_GENERIC 3
+#define OMAP_DSS_DISPC_GENERIC 4
+#define DSS_CTX_NUMBER (OMAP_DSS_DISPC_GENERIC + 1)
+
+#define OMAP2_OUTPUT_LCD 4
+#define OMAP2_OUTPUT_TV 5
+
+/* Dithering enable/disable */
+#define DITHERING_ON 28
+#define DITHERING_OFF 29
+
+/* TVOUT Definitions */
+enum omap2_tvstandard {
+ PAL_BDGHI = 0,
+ PAL_NC,
+ PAL_N,
+ PAL_M,
+ PAL_60,
+ NTSC_M,
+ NTSC_J,
+ NTSC_443,
+};
+
+/* TV ref ON/OFF */
+#define TVREF_ON 30
+#define TVREF_OFF 31
+
+/* LCD data lines configuration */
+#define LCD_DATA_LINE_12BIT 32
+#define LCD_DATA_LINE_16BIT 33
+#define LCD_DATA_LINE_18BIT 34
+#define LCD_DATA_LINE_24BIT 35
+
+/* transparent color key types */
+#define OMAP2_GFX_DESTINATION 100
+#define OMAP2_VIDEO_SOURCE 101
+
+/* SDRAM page size parameters used for VRFB settings */
+#define PAGE_WIDTH_EXP 5 /* page width = 1 << PAGE_WIDTH_EXP */
+#define PAGE_HEIGHT_EXP 5 /* page height = 1 << PAGE_HEIGHT_EXP */
+
+/* 2048 x 2048 is max res supported by OMAP24xx display controller */
+#define MAX_PIXELS_PER_LINE 2048
+#define MAX_LINES 2048
+
+#define TV_OFF 0
+#define TV_ON 1
+#define LCD_OFF 0
+#define LCD_ON 1
+
+/* States needed for TV-LCD on the fly */
+#define TVLCD_STOP 1
+#define TVLCD_CONTINUE 2
+
+extern short int current_colorconv_values[2][3][3];
+
+/* input layer APIs */
+extern int omap2_disp_request_layer (int ltype);
+extern void omap2_disp_release_layer (int ltype);
+extern void omap2_disp_disable_layer (int ltype);
+extern void omap2_disp_enable_layer (int ltype);
+extern void omap2_disp_config_vlayer (int ltype, struct v4l2_pix_format *pix,
+ struct v4l2_rect *crop,
+ struct v4l2_window *win,
+ int rotation_deg, int mirroring);
+extern int omap2_disp_reg_sync_bit(int output_dev);
+extern void omap2_disp_config_gfxlayer (u32 size_x, u32 size_y,
+ int color_depth);
+extern void omap2_disp_start_vlayer (int ltype, struct v4l2_pix_format *pix,
+ struct v4l2_rect *crop, struct v4l2_window *win,
+ unsigned long fb_base_phys,
+ int rotation_deg, int mirroring);
+extern void omap2_disp_start_gfxlayer (void);
+
+/* output device APIs */
+extern void omap2_disp_get_panel_size (int output_dev, int *witdth,
+ int *height);
+extern void omap2_disp_set_panel_size (int output_dev, int witdth,
+ int height);
+extern void omap2_disp_disable_output_dev (int output_dev);
+extern void omap2_disp_enable_output_dev (int output_dev);
+extern void omap2_disp_config_lcd (u32 clkdiv, u32 hbp, u32 hfp, u32 hsw,
+ u32 vbp, u32 vfp, u32 vsw);
+extern void omap2_disp_lcdcfg_polfreq(u32 hsync_high, u32 vsync_high,
+ u32 acb,u32 ipc, u32 onoff);
+extern void omap2_disp_set_pcd (u32 pcd);
+extern void omap2_disp_set_dssfclk (void);
+extern void omap2_disp_set_tvstandard (int tvstandard);
+extern int omap2_disp_get_tvstandard (void);
+extern void omap2_disp_get_tvlcd(struct tvlcd_status_t *status);
+extern void omap2_disp_set_tvlcd(int status);
+extern void omap2_disp_set_dithering (int dither_state);
+#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
+extern void omap2_disp_set_tvref (int tvref_state);
+#endif
+extern int omap2_disp_get_dithering (void);
+
+extern void omap2_disp_set_lcddatalines (int no_of_lines);
+extern int omap2_disp_get_lcddatalines (void);
+
+/* connection of input layers to output devices */
+extern int omap2_disp_get_output_dev (int ltype);
+extern void omap2_disp_set_output_dev (int ltype, int output_dev);
+extern void omap2_disp_set_dma_params (int ltype, int output_dev,
+ u32 ba0, u32 ba1, u32 row_inc,
+ u32 pix_inc);
+
+/* DSS power management */
+extern void omap2_disp_get_dss (void);
+extern void omap2_disp_put_dss (void);
+
+/* Clocks mgt */
+extern void omap2_disp_get_all_clks(void);
+extern void omap2_disp_put_all_clks(void);
+
+/* Color conversion */
+void omap2_disp_set_default_colorconv (int ltype,
+ struct v4l2_pix_format *pix);
+void omap2_disp_set_colorconv (int ltype, struct v4l2_pix_format *pix);
+
+/* background color */
+extern void omap2_disp_set_bg_color (int output_dev, int color);
+extern void omap2_disp_get_bg_color (int output_dev, int *color);
+
+/* transparent color key */
+extern void omap2_disp_set_colorkey (int output_dev, int key_type,
+ int key_val);
+extern void omap2_disp_get_colorkey (int output_dev, int *key_type,
+ int *key_val);
+extern void omap2_disp_enable_colorkey (int output_dev);
+extern void omap2_disp_disable_colorkey (int output_dev);
+
+/* alpha blending */
+int omap2_disp_get_alphablend(int output_dev);
+void omap2_disp_set_alphablend(int output_dev,int value);
+unsigned char omap2_disp_get_global_alphablend_value(int ltype);
+void omap2_disp_set_global_alphablend_value(int ltype,int value);
+
+/* other helpers */
+extern void omap2_disp_set_gfx_palette (u32 palette_ba);
+extern void omap2_disp_pixels_per_clock (unsigned int *nom,
+ unsigned int *den);
+
+/* rotation APIs */
+extern int omap2_disp_set_vrfb (int context, u32 phy_addr,
+ u32 width, u32 height, u32 bytes_per_pixel);
+
+/* display controller register synchronization */
+void omap2_disp_reg_sync (int output_dev);
+extern int omap2_disp_reg_sync_done (int output_dev);
+
+/* disable LCD and TV outputs and sync with next frame */
+extern void omap2_disp_disable (unsigned long timeout_ticks);
+
+/* interrupt handling */
+typedef void (*omap2_disp_isr_t) (void *arg, struct pt_regs * regs);
+extern int omap2_disp_register_isr (omap2_disp_isr_t isr, void *arg,
+ unsigned int mask);
+extern int omap2_disp_unregister_isr (omap2_disp_isr_t isr);
+extern int omap2_disp_irqenable(omap2_disp_isr_t isr,unsigned int mask);
+extern int omap2_disp_irqdisable(omap2_disp_isr_t isr,unsigned int mask);
+extern void omap2_disp_save_initstate (int layer);
+extern void omap2_disp_restore_initstate (int layer);
+
+/* LPR */
+int omap2_disp_lpr_enable(void);
+int omap2_disp_lpr_disable(void);
+int omap2_disp_get_gfx_fifo_low_threshold(void);
+void omap2_disp_set_gfx_fifo_low_threshold(int thrs);
+int omap2_disp_get_gfx_fifo_high_threshold(void);
+void omap2_disp_set_gfx_fifo_high_threshold(int thrs);
+
+
+/*------------------ end of exposed values and APIs
-------------------------*/
+
+#endif /* __ASM_ARCH_OMAP2_DISP_H */
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 0b13557..2809f69 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -140,8 +140,11 @@
#define OMAP34XX_GPMC_SIZE SZ_1M
#define OMAP343X_SMS_PHYS OMAP343X_SMS_BASE /* 0x6C000000 */
+#define SMS_PHYS OMAP343X_SMS_PHYS
#define OMAP343X_SMS_VIRT 0xFC000000
+#define SMS_VIRT OMAP343X_SMS_VIRT
#define OMAP343X_SMS_SIZE SZ_1M
+#define SMS_SIZE OMAP343X_SMS_SIZE
#define OMAP343X_SDRC_PHYS OMAP343X_SDRC_BASE /* 0x6D000000 */
#define OMAP343X_SDRC_VIRT 0xFD000000
diff --git a/include/asm-arm/arch-omap/power_companion.h
b/include/asm-arm/arch-omap/power_companion.h
new file mode 100644
index 0000000..da77f9c
--- /dev/null
+++ b/include/asm-arm/arch-omap/power_companion.h
@@ -0,0 +1,151 @@
+/*
+ * linux/include/asm-arm/arch-omap2/power_companion.h
+ *
+ * Power Companion Chip defines.
+ *
+ * Copyright (C) 2006 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef __ASM_ARM_ARCH_OMAP2_POWER_COMPANION_H
+#define __ASM_ARM_ARCH_OMAP2_POWER_COMPANION_H
+
+#include <asm/arch/twl4030.h>
+#include <asm/arch/bits.h>
+
+#define PM_MASTER TWL4030_MODULE_PM_MASTER
+#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
+#define PM_INT TWL4030_MODULE_INT
+
+#define t2_out(c, v, r) twl4030_i2c_write_u8(c, v, r)
+#define t2_in(c, v, r) twl4030_i2c_read_u8(c, v, r)
+
+
+int power_companion_init(void);
+int enable_vmode_companion_voltage_scaling(int vdd, int floor, int roof,
+ int mode);
+int disable_companion_voltage_scaling(void);
+int write_bits_companion_reg(u8 mod_no, u8 value, u8 reg);
+int set_bits_companion_reg(u8 mod_no, u8 value, u8 reg);
+int clear_bits_companion_reg(u8 mod_no, u8 value, u8 reg);
+int set_voltage_level(u8 vdd, u8 vsel);
+
+#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
+#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
+#define PHY_TO_OFF_PM_INT(p) (p - 0x2e)
+
+/* resource - vaux1 */
+#define ENABLE_VAUX1_DEDICATED 0x03
+#define ENABLE_VAUX1_DEV_GRP 0x20
+int twl4030_vaux1_ldo_use(void);
+int twl4030_vaux1_ldo_unuse(void);
+
+/* resource - vaux2 */
+#define ENABLE_VAUX2_DEDICATED 0x09
+#define ENABLE_VAUX2_DEV_GRP 0x20
+int twl4030_vaux2_ldo_use(void);
+int twl4030_vaux2_ldo_unuse(void);
+
+/* resource - vaux3 */
+#define ENABLE_VAUX3_DEDICATED 0x03
+#define ENABLE_VAUX3_DEV_GRP 0x20
+int twl4030_vaux3_ldo_use(void);
+int twl4030_vaux3_ldo_unuse(void);
+
+/* resource - hfclk */
+#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
+
+/* boot config */
+#define R_CFG_BOOT PHY_TO_OFF_PM_MASTER(0x3b)
+#define HFCLK_FREQ_19p2_MHZ (1 << 0)
+#define HFCLK_FREQ_26_MHZ (2 << 0)
+#define HFCLK_FREQ_38p4_MHZ (3 << 0)
+#define HIGH_PERF_SQ (1 << 3)
+
+/* access control */
+#define R_PROTECT_KEY PHY_TO_OFF_PM_MASTER(0x44)
+#define KEY_UNLOCK1 0xce
+#define KEY_UNLOCK2 0xec
+#define KEY_LOCK 0x00
+
+/* Vmode control */
+#define R_DCDC_GLOBAL_CFG PHY_TO_OFF_PM_RECEIVER(0x61)
+
+#define R_VDD1_VSEL PHY_TO_OFF_PM_RECEIVER(0xb9)
+#define R_VDD1_VMODE_CFG PHY_TO_OFF_PM_RECEIVER(0xba)
+#define R_VDD1_VFLOOR PHY_TO_OFF_PM_RECEIVER(0xbb)
+#define R_VDD1_VROOF PHY_TO_OFF_PM_RECEIVER(0xbc)
+#define R_VDD1_STEP PHY_TO_OFF_PM_RECEIVER(0xbd)
+
+#define R_VDD2_VSEL PHY_TO_OFF_PM_RECEIVER(0xc7)
+#define R_VDD2_VMODE_CFG PHY_TO_OFF_PM_RECEIVER(0xc8)
+#define R_VDD2_VFLOOR PHY_TO_OFF_PM_RECEIVER(0xc9)
+#define R_VDD2_VROOF PHY_TO_OFF_PM_RECEIVER(0xca)
+#define R_VDD2_STEP PHY_TO_OFF_PM_RECEIVER(0xcb)
+
+/* R_DCDC_GLOBAL_CFG register, SMARTREFLEX_ENABLE valuws */
+#define DCDC_GLOBAL_CFG_ENABLE_SRFLX 0x08
+
+/* R_VDD1_VMODE_CFG register, ENABLE_VMODE values */
+#define VDD1_VMODE_CFG_ENABLE_VMODE 0x01
+
+/* R_VDD1_STEP register, STEP_REG values */
+#define VDD1_STEP_STEP_REG_0 0x00
+
+/* R_VDD2_VMODE_CFG register, ENABLE_VMODE values */
+#define VDD2_VMODE_CFG_ENABLE_VMODE 0x01
+
+/* R_VDD2_STEP register, STEP_REG values */
+#define VDD2_STEP_STEP_REG_0 0x00
+
+#define EN_JMP 0x0
+#define DIS_SCALE 0x0
+#define EN_SCALE 0x1
+
+#define V_1p3 0x38
+#define V_1p2 0x30
+#define V_1p15 0x2C
+#define V_1p05 0x24
+#define V_1p0 0x20
+
+/* sequence script */
+#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
+#define R_SEQ_ADD_SA12 PHY_TO_OFF_PM_MASTER(0x56)
+#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
+#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
+#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
+
+/* PM events */
+#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
+#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
+#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
+#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
+#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
+#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
+#define LVL_WAKEUP BIT3
+#define STARTON_CHG BIT1
+
+#define R_PWR_ISR1 PHY_TO_OFF_PM_INT(0x2e)
+#define R_PWR_IMR1 PHY_TO_OFF_PM_INT(0x2f)
+#define R_PWR_ISR2 PHY_TO_OFF_PM_INT(0x30)
+#define R_PWR_IMR2 PHY_TO_OFF_PM_INT(0x31)
+#define R_PWR_EDR1 PHY_TO_OFF_PM_INT(0x33)
+#define R_PWR_EDR2 PHY_TO_OFF_PM_INT(0x34)
+#define R_PWR_SIH_CTRL PHY_TO_OFF_PM_INT(0x35)
+#define SIH_COR BIT2
+#define SIH_EXCLEN BIT0
+
+/* R_PWR_ISR1,2 R_PWR_IMR1,2 bits */
+#define RTC_IT BIT3
+
+/* R_PWR_EDR1 bits */
+#define RTC_IT_RISING BIT7
+
+#endif /* POWER_COMPANION */
diff --git a/include/asm-arm/arch-omap/prcm.h
b/include/asm-arm/arch-omap/prcm.h
index b707af7..941fc20 100644
--- a/include/asm-arm/arch-omap/prcm.h
+++ b/include/asm-arm/arch-omap/prcm.h
@@ -1,9 +1,9 @@
/*
* linux/include/asm-arm/arch-omap/prcm.h
*
- * Access definations for use in OMAP24XX clock and power management
+ * Access definitions for use in OMAP34XX clock and power management
*
- * Copyright (C) 2005 Texas Instruments, Inc.
+ * Copyright (C) 2007 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -20,15 +20,1202 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef __ASM_ARM_ARCH_OMAP_PRCM_H
-#define __ASM_ARM_ARCH_OMAP_PRCM_H
+#ifndef __ASM_ARM_ARCH_PRCM_H
+#define __ASM_ARM_ARCH_PRCM_H
u32 omap_prcm_get_reset_sources(void);
-void omap_prcm_arch_reset(char mode);
+/* Return Values of PRCM Lib API's */
+#define PRCM_PASS 0
+#define PRCM_FAIL 1
+
+/* Definitions for enable/ disable */
+#define PRCM_ENABLE 1
+#define PRCM_DISABLE 0
+
+#define PRCM_TRUE 1
+#define PRCM_FALSE 0
+
+/* Check accessibility or dont check accessibility*/
+#define PRCM_ACCESS_CHK 1
+#define PRCM_NO_ACCESS_CHK 0
+
+/* IDLE METHOD */
+#define PRCM_AUTO 1
+#define PRCM_FORCE 2
+#define PRCM_MANUAL 3
+
+/* POWER DOMAIN STATES */
+#define PRCM_OFF 0x0
+#define PRCM_RET 0x1
+#define PRCM_INACTIVE 0x2
+#define PRCM_ON 0x3
+
+/* Dpll resources */
+#define DPLL_NO_AUTOIDLE 0x0
+#define DPLL_AUTOIDLE 0x1
+#define DPLL_AUTOIDLE_BYPASS 0x5
+
+/* memory and logic states */
+#define MEMORY_OFF 0x0
+#define MEMORY_RET 0x1
+#define MEMORY_ON 0x3
+#define MEMORY_MAXLEVEL_DOMAINRET 0x2
+#define MEMORY_MAXLEVEL_DOMAINON 0x4
+
+#define LOGIC_OFF 0x0
+#define LOGIC_RET 0x1
+#define LOGIC_MAXLEVEL 0x2
+
+
+/* CLOCK STATE TRANSITIONS */
+#define PRCM_NO_AUTO 0x0
+#define PRCM_SWSUP_SLEEP 0x1
+#define PRCM_SWSUP_WKUP 0x2
+#define PRCM_HWSUP_AUTO 0x3
+
+#define PRCM_FORCE_IDLE 0x0
+#define PRCM_NO_IDLE 0x1
+#define PRCM_SMART_IDLE 0x2
+#define PRCM_SIDLEMODE_DONTCARE 0x3
+
+#define PRCM_FORCE_STANDBY 0x0
+#define PRCM_NO_STANDBY 0x1
+#define PRCM_SMART_STANDBY 0x2
+#define PRCM_MIDLEMODE_DONTCARE 0x3
+
+/* Masks for standby, idle and auto idle modes */
+#define PRCM_AUTO_IDLE_MASK 0x1
+#define PRCM_IDLE_MASK 0x18
+#define PRCM_STANDBY_MASK 0x3000
+
+/* Offsets for standby, idle and auto idle modes */
+#define PRCM_AUTO_IDLE_OFF 0x0
+#define PRCM_IDLE_OFF 0x3
+#define PRCM_STANDBY_OFF 0xC
+
+/* Mask for setting wakeup dependency */
+#define PRCM_WKDEP_EN_CORE 0x1
+#define PRCM_WKDEP_EN_MPU 0x2
+#define PRCM_WKDEP_EN_IVA2 0x4
+#define PRCM_WKDEP_EN_WKUP 0x10
+#define PRCM_WKDEP_EN_DSS 0x20
+#define PRCM_WKDEP_EN_PER 0x80
+
+/* Mask for setting sleep dependency */
+#define PRCM_SLEEPDEP_EN_CORE 0x1
+#define PRCM_SLEEPDEP_EN_MPU 0x2
+#define PRCM_SLEEPDEP_EN_IVA2 0x4
+
+/* Mask for H/W supervised transitions L3, L4 and D2D CLKS */
+#define CLK_D2D_HW_SUP_ENABLE 0x30
+#define CLK_L4_HW_SUP_ENABLE 0xC
+#define CLK_L3_HW_SUP_ENABLE 0x3
+
+/* VDDs*/
+#define PRCM_VDD1 1
+#define PRCM_VDD2 2
+#define PRCM_MAX_SYSC_REGS 30
+
+
+/* OMAP Revisions */
+#define AT_3430 1 /*3430 ES 1.0 */
+#define AT_3430_ES2 2 /*3430 ES 2.0 */
+
+/* Domains */
+#define DOM_IVA2 1
+#define DOM_MPU 2
+#define DOM_CORE1 3
+#define DOM_CORE2 4
+#ifdef CONFIG_OMAP3430_ES2
+#define DOM_SGX 5
+#else
+#define DOM_GFX 5
+#endif
+#define DOM_WKUP 6
+#define DOM_DSS 7
+#define DOM_CAM 8
+#define DOM_PER 9
+#define DOM_EMU 10
+#define DOM_NEON 11
+#ifdef CONFIG_OMAP3430_ES2
+#define DOM_CORE3 12
+#define DOM_USBHOST 13
+#define PRCM_NUM_DOMAINS 13
+#else
+#define PRCM_NUM_DOMAINS 11
+#endif
+
+/* DPLL's */
+#define DPLL1_MPU 1
+#define DPLL2_IVA2 2
+#define DPLL3_CORE 3
+#define DPLL4_PER 4
+#ifdef CONFIG_OMAP3430_ES2
+#define DPLL5_PER2 5
+#define NO_OF_DPLL 5
+#else
+#define NO_OF_DPLL 4
+#endif
+
+/* PUT_DPLL_IN_BYPASS PARAMETERS */
+#define LOW_POWER_STOP 1
+#define LOW_POWER_BYPASS 5
+#define FAST_RELOCK_BYPASS 6
+
+/* DPLL dividers */
+#define DPLL_M2 0x0
+#define DPLL_M2X2 0x1
+#define DPLL_M3X2 0x2
+#define DPLL_M4X2 0x3
+#define DPLL_M5X2 0x4
+#define DPLL_M6X2 0x5
+#define NO_DPLL_DIV 0x6
+
+/* Device Type */
+#define INITIATOR 1
+#define TARGET 2
+#define INIT_TAR 3
+
+/* Clock Type */
+#define FCLK 1
+#define ICLK 2
+
+/* Initiator masks for all domains */
+#define IVA2_IMASK 0x1
+#define MPU_IMASK 0x1
+#define CORE2_IMASK 0x0
+#ifdef CONFIG_OMAP3430_ES2
+#define CORE1_IMASK 0x15
+#define CORE3_IMASK 0x0
+#define SGX_IMASK 0x1
+#define USBHOST_IMASK 0x1
+#else
+#define CORE1_IMASK 0x3D
+#define GFX_IMASK 0x1
+#endif
+#define WKUP_IMASK 0x0
+#define DSS_IMASK 0x1
+#define CAM_IMASK 0x1
+#define PER_IMASK 0x0
+#define NEON_IMASK 0x1
+
+/* Type of device IDs - Note that a particular device ID
+ can be of multiple types*/
+#define ID_DEV 0x0 /*Leaf node eg:uart */
+#define ID_DPLL_OP 0x1 /*Dpll output */
+#define ID_CLK_DIV 0x2 /*Clock has a divider */
+#define ID_CLK_SRC 0x4 /*Source of the clock can be selected */
+
+#define ID_CLK_PARENT 0xE1 /*Parent of some other clock */
+#define ID_OPP 0xE2 /*OPP*/
+#define ID_MPU_DOM_STATE 0xE4 /*Mpu power domain state*/
+#define ID_CORE_DOM_STATE 0xE8 /*Core power domain state*/
+#define ID_SYSCONF 0xF0
+
+#define ID_CONSTRAINT_CLK 0xF1 /* a clock rampup constraint */
+#define ID_CONSTRAINT_OPP 0xF2 /* OPP constraint */
+#define ID_CONSTRAINT_FREQ 0xF3 /* Frequnecy constraint */
+#define ID_MEMORY_RES 0xF4 /* Memory resource */
+#define ID_LOGIC_RES 0xF5 /* Logic resource */
+#define ID_DPLL_RES 0xF6 /*Dpll resource */
+
+/* DEVICE ID: bits 0-4 for Device bit position */
+#define DEV_BIT_POS_SHIFT 0
+#define DEV_BIT_POS_MASK 0x1F
+/* DEVICE ID: bits 5-8 for domainid */
+#define DOMAIN_ID_SHIFT 5
+#define DOMAIN_ID_MASK 0xF
+/* DEVICE ID: bits 9-10 for device type */
+#define DEV_TYPE_SHIFT 9
+#define DEV_TYPE_MASK 0x3
+/* DEVICE ID: bits 11-13 for clk src*/
+#define CLK_SRC_BIT_POS_SHIFT 11
+#define CLK_SRC_BIT_POS_MASK 0x7
+/* CLK ID: bits 14-18 for the clk number */
+#define CLK_NO_POS 14
+#define CLK_NO_MASK 0x1F
+/* DPLL ID: bits 19-21 for the DPLL number */
+#define DPLL_NO_POS 19
+#define DPLL_NO_MASK 0x7
+/* DPLL ID: bits 22-24 for Divider */
+#define DPLL_DIV_POS 22
+#define DPLL_DIV_MASK 0x7
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 25-27 for ID type */
+#define ID_TYPE_SHIFT 25
+#define ID_TYPE_MASK 0x7
+/* DEVICE ID/DPLL ID/CLOCK ID: bits 28-31 for OMAP type */
+#define OMAP_TYPE_SHIFT 28
+#define OMAP_TYPE_MASK 0xF
+
+/* Other IDs: bits 20-27 for ID type */
+/* These IDs have bits 25,26,27 as 1 */
+#define OTHER_ID_TYPE_SHIFT 20
+#define OTHER_ID_TYPE_MASK 0xFF
+
+/* OPP ID: bits: 0-4 for OPP number */
+#define OPP_NO_POS 0
+#define OPP_NO_MASK 0x1F
+/* OPP ID: bits: 5-6 for VDD */
+#define VDD_NO_POS 5
+#define VDD_NO_MASK 0x3
+/* COMMMON bits in DEVICE ID/DPLL ID/CLOCK ID */
+/* Macros */
+#define ID_DEV_BIT_POS(X) ((X & DEV_BIT_POS_MASK)<< DEV_BIT_POS_SHIFT)
+#define ID_CLK_SRC_BIT_POS(X) ((X & CLK_SRC_BIT_POS_MASK)<<
CLK_SRC_BIT_POS_SHIFT)
+#define ID_DOMAIN(X) ((X & DOMAIN_ID_MASK) << DOMAIN_ID_SHIFT)
+#define ID_DEV_TYPE(X) ((X & DEV_TYPE_MASK) << DEV_TYPE_SHIFT)
+#define ID_DPLL_NO(X) ((X & DPLL_NO_MASK) << DPLL_NO_POS)
+#define ID_DPLL_DIV(X) ((X & DPLL_DIV_MASK) << DPLL_DIV_POS)
+#define ID_CLK_NO(X) ((X & CLK_NO_MASK) << CLK_NO_POS)
+#define ID_TYPE(X) ((X & ID_TYPE_MASK) << ID_TYPE_SHIFT)
+#define OTHER_ID_TYPE(X) ((X & OTHER_ID_TYPE_MASK) << OTHER_ID_TYPE_SHIFT)
+#define ID_ES(X) ((X & ES_TYPE_MASK) << ES_TYPE_SHIFT)
+#define ID_OMAP(X) ((X & OMAP_TYPE_MASK) << OMAP_TYPE_SHIFT)
+#define ID_OPP_NO(X) ((X & OPP_NO_MASK) << OPP_NO_POS)
+#define ID_VDD(X) ((X & VDD_NO_MASK) << VDD_NO_POS)
+#define DEV_BIT_POS(X) ((X >> DEV_BIT_POS_SHIFT) & DEV_BIT_POS_MASK)
+#define CLK_SRC_BIT_POS(X) ((X >> CLK_SRC_BIT_POS_SHIFT) &
CLK_SRC_BIT_POS_MASK)
+#define DOMAIN_ID(X) ((X >> DOMAIN_ID_SHIFT) & DOMAIN_ID_MASK)
+#define DEV_TYPE(X) ((X >> DEV_TYPE_SHIFT) & DEV_TYPE_MASK)
+#define OMAP(X) ((X >> OMAP_TYPE_SHIFT) & OMAP_TYPE_MASK)
+#define get_id_type(X) ((X >> ID_TYPE_SHIFT) & ID_TYPE_MASK)
+#define get_other_id_type(X) ((X >> OTHER_ID_TYPE_SHIFT) &
OTHER_ID_TYPE_MASK)
+#define get_opp_no(X) ((X >> OPP_NO_POS) & OPP_NO_MASK)
+#define get_vdd(X) ((X >> VDD_NO_POS) & VDD_NO_MASK)
+#define get_addr(domainId,regId) (dom_reg[domainId-1].regdef[regId].reg_addr)
+#define get_val_bits(domainId,regId)
(dom_reg[domainId-1].regdef[regId].valid_bits)
+#define get_addr_pll(dpll,regId) (dpll_reg[dpll-1].regdef[regId].reg_addr)
+#define get_val_bits_pll(dpll,regId)
(dpll_reg[dpll-1].regdef[regId].valid_bits)
+#define get_idlest_lock_bit(dpll_id) ((dpll_id==DPLL4_PER)?0x2:0x1)
+#define get_dpll_enbitmask(dpll_id)
((dpll_id==DPLL4_PER)?DPLL4_ENBIT_MASK:DPLL_ENBIT_MASK)
+/* DEVICE ID's */
+/* Devices in Core1 registers */
+#define PRCM_SSI (ID_OMAP(AT_3430) | ID_TYPE( (ID_DEV | ID_CLK_DIV)) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x0) | ID_CLK_NO(0x7))
+#define PRCM_SDRC (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1))
+#define PRCM_SDMA (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x2))
+#define PRCM_D2D (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x3))
+#define PRCM_HSOTG (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x4))
+
+#ifndef CONFIG_OMAP3430_ES2
+#define PRCM_FSHOST (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_DIV)) |
ID_DEV_TYPE(INITIATOR) \
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x5) | ID_CLK_NO(0x4) )
+#endif
+
+#define PRCM_OMAP_CTRL (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x6))
+#define PRCM_MBOXES (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x7))
+#define PRCM_FAC (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x8))
+#define PRCM_MCBSP1 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
+ ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x9))
+#define PRCM_MCBSP5 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
+ ID_CLK_SRC_BIT_POS(0x4) | ID_DEV_BIT_POS(0xA))
+#define PRCM_GPT10 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
+ ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0xB))
+#define PRCM_GPT11 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_CORE1) | \
+ ID_CLK_SRC_BIT_POS(0x7) | ID_DEV_BIT_POS(0xC))
+#define PRCM_UART1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xD))
+#define PRCM_UART2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xE))
+#define PRCM_I2C1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0xF))
+#define PRCM_I2C2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x10))
+#define PRCM_I2C3 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x11))
+#define PRCM_MCSPI1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x12))
+#define PRCM_MCSPI2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x13))
+#define PRCM_MCSPI3 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x14))
+#define PRCM_MCSPI4 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x15))
+#define PRCM_HDQ (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x16))
+#define PRCM_MSPRO (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x17))
+#define PRCM_MMC1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x18))
+#define PRCM_MMC2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x19))
+#define PRCM_DES2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1A))
+#define PRCM_SHA12 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1B))
+#define PRCM_AES2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1C))
+#define PRCM_ICR (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1D))
+#define PRCM_MMC3 (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x1E))
+#define PRCM_SMS (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(TARGET) | \
+ ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x18))
+#define PRCM_GPMC (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(TARGET) | \
+ ID_DOMAIN(DOM_CORE1) | ID_DEV_BIT_POS(0x19))
+#define PRCM_MPU_INTC (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(TARGET) | \
+ ID_DOMAIN(DOM_CORE1) |
ID_DEV_BIT_POS(0x1A))
+#define PRCM_CORE1_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_CORE1))
+/* Devices in Core2 registers */
+#define PRCM_DES1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x0))
+#define PRCM_SHA11 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x1))
+#define PRCM_RNG (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x2))
+#define PRCM_AES1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x3))
+#define PRCM_PKA (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE2) | ID_DEV_BIT_POS(0x4))
+
+/* Devices in Core3 registers */
+#define PRCM_CPEFUSE (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x0))
+#define PRCM_TS (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x1))
+#define PRCM_USBTLL (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_CORE3) | ID_DEV_BIT_POS(0x2))
+#ifdef CONFIG_OMAP3430_ES2
+/* Devices in SGX registers */
+#define PRCM_SGX_ICLK (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |\
+ ID_DEV_TYPE(INITIATOR) | ID_DOMAIN(DOM_SGX)\
+ | ID_DEV_BIT_POS(0x0))
+#define PRCM_SGX_FCLK (ID_OMAP(AT_3430_ES2) |\
+ ID_TYPE((ID_DEV | ID_CLK_DIV | ID_CLK_SRC))\
+ | ID_DOMAIN(DOM_SGX) | ID_DEV_TYPE(TARGET) |\
+ ID_CLK_NO(0x6) | ID_DEV_BIT_POS(0x1))
+#define PRCM_3D_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_SGX))
+#else
+#define PRCM_GFX (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_GFX) | ID_DEV_BIT_POS(0x0))
+#define PRCM_2D (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_GFX) | ID_DEV_BIT_POS(0x1))
+#define PRCM_3D (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_GFX) | ID_DEV_BIT_POS(0x2))
+#define PRCM_3D_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_GFX))
+#endif
+
+/* Devices in WKUP registers */
+#define PRCM_GPT1 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_WKUP) | \
+ ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x0))
+#define PRCM_GPT12 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x1))
+#define PRCM_32KSYNC (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x2))
+#define PRCM_GPIO1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x3))
+#define PRCM_WDT1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x4))
+#define PRCM_WDT2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x5))
+#define PRCM_SR1 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x6))
+#define PRCM_SR2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ | ID_DOMAIN(DOM_WKUP) | ID_DEV_BIT_POS(0x7))
+#define PRCM_USIM (ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_CLK_DIV |\
+ ID_CLK_SRC)) | ID_DEV_TYPE(TARGET) |\
+ ID_DOMAIN(DOM_WKUP)\
+ | ID_DEV_BIT_POS(0x9) | ID_CLK_NO(0xA))
+
+/* Devices in IVA registers */
+#define PRCM_IVA2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_IVA2) | ID_DEV_BIT_POS(0x0))
+#define PRCM_IVA2_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_IVA2))
+/* Devices in DSS registers */
+#define PRCM_DSS (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_DPLL_OP)) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x0) | \
+ ID_DPLL_DIV(DPLL_M4X2) | ID_DPLL_NO(DPLL4_PER) )
+#define PRCM_DSS2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x1))
+#define PRCM_TVOUT (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC)) | \
+ ID_DEV_TYPE(TARGET) | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x2))
+#define PRCM_DISPC (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INIT_TAR) \
+ | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x1))
+#define PRCM_RFBI (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INITIATOR) \
+ | ID_DOMAIN(DOM_DSS) | ID_DEV_BIT_POS(0x2))
+
+#define PRCM_DSS_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_DSS))
+
+/* Devices in CAM Domain */
+#define PRCM_CAM (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_DPLL_OP)) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x0) |\
+ ID_DPLL_DIV(DPLL_M5X2) | ID_DPLL_NO(DPLL4_PER))
+
+#ifdef CONFIG_OMAP3430_ES2
+#define PRCM_CSI2 (ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_DPLL_OP)) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x1))
+#endif
+
+#define PRCM_CSIA (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INIT_TAR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x1))
+#define PRCM_CSIB (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INIT_TAR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x2))
+#define PRCM_MMU (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INIT_TAR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x3))
+#define PRCM_ISP_CTRL (ID_OMAP(AT_3430) | OTHER_ID_TYPE(ID_SYSCONF) |
ID_DEV_TYPE(INIT_TAR)\
+ | ID_DOMAIN(DOM_CAM) | ID_DEV_BIT_POS(0x4))
+#define PRCM_CAM_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_CAM))
+
+/* Devices in PER Domain */
+#define PRCM_MCBSP2 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0x0))
+#define PRCM_MCBSP3 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x1))
+#define PRCM_MCBSP4 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x2))
+#define PRCM_GPT2 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x0) | ID_DEV_BIT_POS(0x3))
+#define PRCM_GPT3 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x1) | ID_DEV_BIT_POS(0x4))
+#define PRCM_GPT4 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x2) | ID_DEV_BIT_POS(0x5))
+#define PRCM_GPT5 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x3) | ID_DEV_BIT_POS(0x6))
+#define PRCM_GPT6 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x4) | ID_DEV_BIT_POS(0x7))
+#define PRCM_GPT7 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x5) | ID_DEV_BIT_POS(0x8))
+#define PRCM_GPT8 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x6) | ID_DEV_BIT_POS(0x9))
+#define PRCM_GPT9 (ID_OMAP(AT_3430) | ID_TYPE((ID_DEV | ID_CLK_SRC))\
+ | ID_DEV_TYPE(TARGET) |ID_DOMAIN(DOM_PER) | \
+ ID_CLK_SRC_BIT_POS(0x7) | ID_DEV_BIT_POS(0xA))
+#define PRCM_UART3 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xB))
+#define PRCM_WDT3 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xC))
+#define PRCM_GPIO2 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xD))
+#define PRCM_GPIO3 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xE))
+#define PRCM_GPIO4 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0xF))
+#define PRCM_GPIO5 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0x10))
+#define PRCM_GPIO6 (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) | ID_DEV_TYPE(TARGET)\
+ |ID_DOMAIN(DOM_PER) | ID_DEV_BIT_POS(0x11))
+#define PRCM_PER_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_PER))
+
+/* Devices in NEON Domain */
+#define PRCM_NEON (ID_OMAP(AT_3430) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_NEON) | ID_DEV_BIT_POS(0x0))
+#define PRCM_NEON_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_NEON))
+
+#ifdef CONFIG_OMAP3430_ES2
+/* Devices in USBHOST Domain */
+#define PRCM_USBHOST1 (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DEV) |
ID_DEV_TYPE(INITIATOR)\
+ | ID_DOMAIN(DOM_USBHOST) | ID_DEV_BIT_POS(0x0))
+#define PRCM_USBHOST2 (ID_OMAP(AT_3430_ES2) | ID_TYPE((ID_DEV | ID_DPLL_OP))\
+ | ID_DEV_TYPE(INITIATOR) | ID_DOMAIN(DOM_USBHOST)\
+ | ID_DEV_BIT_POS(0x1)| ID_DPLL_DIV(DPLL_M2)\
+ | ID_DPLL_NO(DPLL5_PER2))
+#define PRCM_USBHOST_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_CLK) | \
+ ID_DOMAIN(DOM_USBHOST))
+#endif
+
+/* DPLL ID's */
+#define PRCM_DPLL1_M2X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL1_MPU))
+#define PRCM_DPLL2_M2X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL2_IVA2))
+#define PRCM_DPLL3_M2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2) | ID_DPLL_NO(DPLL3_CORE))
+#define PRCM_DPLL3_M2X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL3_CORE))
+#define PRCM_DPLL3_M3X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M3X2) | ID_DPLL_NO(DPLL3_CORE))
+#define PRCM_DPLL4_M2X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2X2) | ID_DPLL_NO(DPLL4_PER))
+#define PRCM_DPLL4_M3X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M3X2) | ID_DPLL_NO(DPLL4_PER))
+#define PRCM_DPLL4_M6X2_CLK (ID_OMAP(AT_3430) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M6X2) | ID_DPLL_NO(DPLL4_PER))
+#define PRCM_DPLL5_M2_CLK (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_DPLL_OP)\
+ | ID_DPLL_DIV(DPLL_M2) | ID_DPLL_NO(DPLL5_PER2))
+
+/* CLK ID's */
+#define PRCM_L3_ICLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
+ ID_CLK_NO(0x1))
+#define PRCM_L4_ICLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
+ ID_CLK_NO(0x2))
+#define PRCM_RM_ICLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV) |\
+ ID_CLK_NO(0x3))
+#define PRCM_SYS_CLKOUT2 (ID_OMAP(AT_3430) | ID_TYPE((ID_CLK_DIV |
ID_CLK_SRC))\
+ | ID_CLK_NO(0x5))
+#ifndef CONFIG_OMAP3430_ES2
+#define PRCM_GFX_L3_FCLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
+ | ID_CLK_NO(0x6))
+#endif
+
+#define PRCM_DPLL1_FCLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
+ | ID_CLK_NO(0x8))
+#define PRCM_DPLL2_FCLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
+ | ID_CLK_NO(0x9))
+#define PRCM_96M_CLK (ID_OMAP(AT_3430_ES2) | ID_TYPE(ID_CLK_SRC)\
+ | ID_CLK_SRC_BIT_POS(0x6))
+#define PRCM_NO_OF_CLKS 0xA
+/* func_48m_fclk and func_12m_fclk have dividers */
+/*but they are fixed dividers.*/
+/*So these are not included in the array */
+#define PRCM_48M_FCLK (ID_OMAP(AT_3430) | ID_TYPE((ID_CLK_DIV\
+ | ID_CLK_SRC)) | ID_CLK_NO(0xB))
+#define PRCM_12M_FCLK (ID_OMAP(AT_3430) | ID_TYPE(ID_CLK_DIV)\
+ | ID_CLK_NO(0xE))
+/* Clock IDs for parent clocks */
+#define PRCM_SYS_ALT_CLK (OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
+ | ID_CLK_NO(0xF))
+#define PRCM_SYS_CLK (OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
+ | ID_CLK_NO(0x10))
+#define PRCM_SYS_32K_CLK (OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
+ | ID_CLK_NO(0x11))
+#define PRCM_EXT_MCBSP_CLK (OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
+ | ID_CLK_NO(0x12))
+#define PRCM_SYS_CLKOUT1 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_CLK_PARENT)\
+ | ID_CLK_NO(0x13))
+/* VDD1 OPPs */
+#define PRCM_VDD1_OPP1 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD1)\
+ | ID_OPP_NO(0x1))
+#define PRCM_VDD1_OPP2 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD1)\
+ | ID_OPP_NO(0x2))
+#define PRCM_VDD1_OPP3 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD1)\
+ | ID_OPP_NO(0x3))
+#define PRCM_VDD1_OPP4 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD1)\
+ | ID_OPP_NO(0x4))
+#ifdef CONFIG_OMAP3430_ES2
+#define PRCM_VDD1_OPP5 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD1)\
+ | ID_OPP_NO(0x5))
+#define PRCM_NO_VDD1_OPPS 5
+#else
+#define PRCM_NO_VDD1_OPPS 4
+#endif
+
+/* VDD2 OPPs */
+#define PRCM_VDD2_OPP1 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD2)\
+ | ID_OPP_NO(0x1))
+#define PRCM_VDD2_OPP2 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD2)\
+ | ID_OPP_NO(0x2))
+#ifdef CONFIG_OMAP3430_ES2
+#define PRCM_VDD2_OPP3 (OMAP(AT_3430)| OTHER_ID_TYPE(ID_OPP) |
ID_VDD(PRCM_VDD2)\
+ | ID_OPP_NO(0x3))
+#define PRCM_NO_VDD2_OPPS 3
+#else
+#define PRCM_NO_VDD2_OPPS 2
+#endif
+
+/* OPP and Frequency Constraints */
+#define PRCM_VDD1_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_OPP) | 0x1)
+#define PRCM_VDD2_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_OPP) | 0x2)
+#define PRCM_ARMFREQ_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_FREQ) | 0x3)
+#define PRCM_DSPFREQ_CONSTRAINT (ID_OMAP(AT_3430) | \
+ OTHER_ID_TYPE(ID_CONSTRAINT_FREQ) | 0x4)
+
+/* Mpu power domain states */
+#define PRCM_MPU_ACTIVE (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x0)
+#define PRCM_MPU_INACTIVE (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x1)
+#define PRCM_MPU_CSWR_L2RET (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x3)
+#define PRCM_MPU_CSWR_L2OFF (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x7)
+#define PRCM_MPU_OSWR_L2RET (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0xF)
+#define PRCM_MPU_OSWR_L2OFF (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x1F)
+#define PRCM_MPU_OFF (OTHER_ID_TYPE(ID_MPU_DOM_STATE) | 0x3F)
+
+/* Core power domain states */
+#define PRCM_CORE_ACTIVE (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x0)
+#define PRCM_CORE_INACTIVE (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1)
+#define PRCM_CORE_CSWR_MEMRET (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3)
+#define PRCM_CORE_CSWR_MEM1OFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x7)
+#define PRCM_CORE_CSWR_MEM2OFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0xF)
+#define PRCM_CORE_CSWR_MEMOFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1F)
+#define PRCM_CORE_OSWR_MEMRET (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3F)
+#define PRCM_CORE_OSWR_MEM1OFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x7F)
+#define PRCM_CORE_OSWR_MEM2OFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0xFF)
+#define PRCM_CORE_OSWR_MEMOFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x1FF)
+#define PRCM_CORE_OFF (OTHER_ID_TYPE(ID_CORE_DOM_STATE) | 0x3FF)
+
+/* Memory and Logic resources */
+#define PRCM_MPU_L2CACHEON (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_MPU) | 0x1)
+#define PRCM_MPU_L2CACHERET (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_MPU) | 0x2)
+#define PRCM_MPU_LOGICL1CACHERET (OTHER_ID_TYPE(ID_LOGIC_RES) | \
+ ID_DOMAIN(DOM_MPU) | 0x3)
+
+#define PRCM_CORE_MEM2ON (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x1)
+#define PRCM_CORE_MEM1ON (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x2)
+#define PRCM_CORE_MEM2RET (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x3)
+#define PRCM_CORE_MEM1RET (OTHER_ID_TYPE(ID_MEMORY_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x4)
+#define PRCM_CORE_LOGICRET (OTHER_ID_TYPE(ID_LOGIC_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x5)
+#define PRCM_CORE_MEMORYCHANGE (OTHER_ID_TYPE(ID_LOGIC_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x6)
+#define PRCM_CORE_POWERSTATE (OTHER_ID_TYPE(ID_LOGIC_RES) | \
+ ID_DOMAIN(DOM_CORE1) | 0x7)
+
+#define PRCM_PER_LOGICRET (OTHER_ID_TYPE(ID_LOGIC_RES) | \
+ ID_DOMAIN(DOM_PER) | 0x1)
+
+/* VDD1 and VDD2 sleep states */
+#define PRCM_VDD_ACTIVE 1
+#define PRCM_VDD_RET 2
+#define PRCM_VDD_OFF 3
+
+#define PRCM_WAKEUP_T2_KEYPAD 0x1
+#define PRCM_WAKEUP_TOUCHSCREEN 0x2
+#define PRCM_WAKEUP_UART1 0x4
+
+/* PRM_VC_SMPS_SA */
+#define PRM_VC_SMPS_SA1_SHIFT 16
+#define PRM_VC_SMPS_SA1_MASK (0x7F << 16)
+#define PRM_VC_SMPS_SA0_SHIFT 0
+#define PRM_VC_SMPS_SA0_MASK (0x7F << 16)
+
+/* PRM_VC_SMPS_VOL_RA */
+#define PRM_VC_SMPS_VOLRA1_SHIFT 16
+#define PRM_VC_SMPS_VOLRA1_MASK (0xFF << 16)
+#define PRM_VC_SMPS_VOLRA0_SHIFT 0
+#define PRM_VC_SMPS_VOLRA0_MASK (0xFF << 0)
+
+/* PRM_VC_SMPS_CMD_RA */
+#define PRM_VC_SMPS_CMDRA1_SHIFT 16
+#define PRM_VC_SMPS_CMDRA1_MASK (0xFF << 16)
+#define PRM_VC_SMPS_CMDRA0_SHIFT 0
+#define PRM_VC_SMPS_CMDRA0_MASK (0xFF << 0)
+
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define PRM_VC_CMD_VAL0_ON 0x30
+#define PRM_VC_CMD_VAL0_ONLP 0x18
+#define PRM_VC_CMD_VAL0_RET 0x18
+#define PRM_VC_CMD_VAL0_OFF 0x18
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+#define PRM_VC_CMD_VAL1_ON 0x2C
+#define PRM_VC_CMD_VAL1_ONLP 0x18
+#define PRM_VC_CMD_VAL1_RET 0x18
+#define PRM_VC_CMD_VAL1_OFF 0x18
+
+#define PRM_VC_CMD_ON_SHIFT 24
+#define PRM_VC_CMD_ON_MASK (0xFF << 24)
+#define PRM_VC_CMD_ONLP_SHIFT 16
+#define PRM_VC_CMD_ONLP_MASK (0xFF << 16)
+#define PRM_VC_CMD_RET_SHIFT 8
+#define PRM_VC_CMD_RET_MASK (0xFF << 8)
+#define PRM_VC_CMD_OFF_SHIFT 0
+#define PRM_VC_CMD_OFF_MASK (0xFF << 0)
+
+/* PRM_VC_BYPASS_VAL */
+#define PRM_VC_BYPASS_VALID (0x1 << 24)
+#define PRM_VC_BYPASS_DATA_SHIFT 16
+#define PRM_VC_BYPASS_DATA_MASK (0xFF << 16)
+#define PRM_VC_BYPASS_REGADDR_SHIFT 8
+#define PRM_VC_BYPASS_REGADDR_MASK (0xFF << 8)
+#define PRM_VC_BYPASS_SLAVEADDR_SHIFT 0
+#define PRM_VC_BYPASS_SLAVEADDR_MASK (0x7F << 0)
+
+/* PRM_VC_CH_CONF */
+#define PRM_VC_CH_CONF_CMD1 (0x1 << 20)
+#define PRM_VC_CH_CONF_RAV1 (0x1 << 17)
+
+/* PRM_VC_I2C_CFG */
+#define PRM_VC_I2C_CFG_MCODE 0x0
+#define PRM_VC_I2C_CFG_HSEN (0x1 << 3)
+#define PRM_VC_I2C_CFG_SREN (0x1 << 4)
+#define PRM_VC_I2C_CFG_HSMASTER (0x1 << 5)
+
+/* PRM_VOLTCTRL */
+#define PRM_VOLTCTRL_AUTO_SLEEP 0x1
+#define PRM_VOLTCTRL_AUTO_RET 0x2
+#define PRM_VOLTCTRL_AUTO_OFF 0x4
+#define PRM_VOLTCTRL_SEL_OFF 0x8
+#define PRM_VOLTCTRL_SEL_VMODE 0x10
+
+/* Constants to define setup durations */
+#define PRM_CLKSETUP_DURATION 0xFF
+#define PRM_VOLTSETUP_TIME2 0xFFF
+#define PRM_VOLTSETUP_TIME1 0xFFF
+#define PRM_VOLTOFFSET_DURATION 0xFF
+#define PRM_VOLTSETUP2_DURATION 0xFF
+
+/* PRM_VOLTSETUP1 */
+#define PRM_VOLTSETUP_TIME2_OFFSET 16
+#define PRM_VOLTSETUP_TIME1_OFFSET 0
+
+/* PRM_POLCTRL */
+#define PRM_POL_SYSOFFMODE 0x8
+
+/* PRM_IRQENABLE_MPU */
+#define PRM_VC_TIMEOUTERR_EN (0x1 << 24)
+#define PRM_VC_RAERR_EN (0x1 << 23)
+#define PRM_VC_SAERR_EN (0x1 << 22)
+
+/* PRM_IRQSTATUS_MPU */
+#define PRM_VC_TIMEOUTERR_ST (0x1 << 24)
+#define PRM_VC_RAERR_ST (0x1 << 23)
+#define PRM_VC_SAERR_ST (0x1 << 22)
+
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR 0x12
+#define R_VDD1_SR_CONTROL 0x00
+#define R_VDD2_SR_CONTROL 0x01
+#define T2_SMPS_UPDATE_DELAY 360 /* In uSec */
+
+/* GPTimer wait delay */
+#define GPTIMER_WAIT_DELAY 50 /* In usec */
+
+#define PRCM_SAVE(x) prcm_sleep_save[PRCM_SLEEP_SAVE_##x] = x
+#define PRCM_RESTORE(x) x = prcm_sleep_save[PRCM_SLEEP_SAVE_##x]
+#define PRCM_SHOW(x) prcm_sleep_save[PRCM_SLEEP_SAVE_##x]
+
+enum prcm_save_state {
+ PRCM_SLEEP_SAVE_START = 0,
+ PRCM_SLEEP_SAVE_INTC_MIR_0,
+ PRCM_SLEEP_SAVE_INTC_MIR_1,
+ PRCM_SLEEP_SAVE_INTC_MIR_2,
+ PRCM_SLEEP_SAVE_CONTROL_PADCONF_SYS_NIRQ,
+ PRCM_SLEEP_SAVE_GPIO1_IRQENABLE1,
+ PRCM_SLEEP_SAVE_GPIO1_WAKEUPENABLE,
+ PRCM_SLEEP_SAVE_GPIO1_FALLINGDETECT,
+
+ PRCM_SLEEP_SAVE_CM_CLKSEL2_PLL_IVA2,
+ PRCM_SLEEP_SAVE_CM_SYSCONFIG,
+
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_CLKSEL_SGX,
+#else
+ PRCM_SLEEP_SAVE_CM_CLKSEL_GFX,
+#endif
+ PRCM_SLEEP_SAVE_CM_CLKSEL_WKUP,
+
+ PRCM_SLEEP_SAVE_CM_CLKSEL_DSS,
+
+ PRCM_SLEEP_SAVE_CM_CLKSEL_CAM,
+ PRCM_SLEEP_SAVE_CM_CLKSEL_PER,
+
+ PRCM_SLEEP_SAVE_CM_CLKSEL1_EMU,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_EMU,
+
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE2_PLL,
+ PRCM_SLEEP_SAVE_CM_CLKSEL5_PLL,
+#endif
+ PRCM_SLEEP_SAVE_CM_POLCTRL,
+
+ PRCM_SLEEP_SAVE_CM_FCLKEN_IVA2,
+ PRCM_SLEEP_SAVE_CM_FCLKEN1_CORE,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_FCLKEN3_CORE,
+ PRCM_SLEEP_SAVE_CM_FCLKEN_SGX,
+#else
+ PRCM_SLEEP_SAVE_CM_FCLKEN_GFX,
+#endif
+ PRCM_SLEEP_SAVE_CM_FCLKEN_WKUP,
+ PRCM_SLEEP_SAVE_CM_FCLKEN_DSS,
+ PRCM_SLEEP_SAVE_CM_FCLKEN_CAM,
+ PRCM_SLEEP_SAVE_CM_FCLKEN_PER,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_FCLKEN_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_CM_ICLKEN1_CORE,
+ PRCM_SLEEP_SAVE_CM_ICLKEN2_CORE,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_ICLKEN3_CORE,
+ PRCM_SLEEP_SAVE_CM_ICLKEN_SGX,
+#else
+ PRCM_SLEEP_SAVE_CM_ICLKEN_GFX,
+#endif
+ PRCM_SLEEP_SAVE_CM_ICLKEN_WKUP,
+ PRCM_SLEEP_SAVE_CM_ICLKEN_DSS,
+ PRCM_SLEEP_SAVE_CM_ICLKEN_CAM,
+ PRCM_SLEEP_SAVE_CM_ICLKEN_PER,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_ICLKEN_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL_IVA2,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL_MPU,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_PLL,
+
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_IVA2,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_MPU,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_CORE,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_SGX,
+#else
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_GFX,
#endif
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_DSS,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_CAM,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_PER,
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_NEON,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_CLKSTCTRL_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE1_CORE,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE2_CORE,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE3_CORE,
+#endif
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_WKUP,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_DSS,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_CAM,
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_PER,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_AUTOIDLE_USBHOST,
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_SGX,
+#else
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_GFX,
+#endif
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_DSS,
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_CAM,
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_PER,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_CM_SLEEPDEP_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_CM_CLKOUT_CTRL,
+ PRCM_SLEEP_SAVE_PRM_CLKOUT_CTRL,
+
+ PRCM_SLEEP_SAVE_PM_WKDEP_IVA2,
+ PRCM_SLEEP_SAVE_PM_WKDEP_MPU,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_PM_WKDEP_SGX,
+#else
+ PRCM_SLEEP_SAVE_PM_WKDEP_GFX,
+#endif
+ PRCM_SLEEP_SAVE_PM_WKDEP_DSS,
+ PRCM_SLEEP_SAVE_PM_WKDEP_CAM,
+ PRCM_SLEEP_SAVE_PM_WKDEP_PER,
+ PRCM_SLEEP_SAVE_PM_WKDEP_NEON,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_PM_WKDEP_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_PM_MPUGRPSEL1_CORE,
+ PRCM_SLEEP_SAVE_PM_IVA2GRPSEL1_CORE,
+ PRCM_SLEEP_SAVE_PM_IVA2GRPSEL3_CORE,
+ PRCM_SLEEP_SAVE_PM_MPUGRPSEL3_CORE,
+ PRCM_SLEEP_SAVE_PM_MPUGRPSEL_WKUP,
+ PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_WKUP,
+ PRCM_SLEEP_SAVE_PM_MPUGRPSEL_PER,
+ PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_PER,
+#ifdef CONFIG_OMAP3430_ES2
+ PRCM_SLEEP_SAVE_PM_MPUGRPSEL_USBHOST,
+ PRCM_SLEEP_SAVE_PM_IVA2GRPSEL_USBHOST,
+#endif
+ PRCM_SLEEP_SAVE_PM_WKEN_WKUP,
+
+ PRCM_SLEEP_SAVE_SIZE
+};
+extern void omap_sram_idle(void);
+extern void omap3_configure_core_dpll(u32 tar_m, u32 tar_n, u32 tar_freqsel,
+ u32 tar_m2);
+/* Structure to save interrupt controller context */
+struct int_controller_context {
+ u32 sysconfig;
+ u32 protection;
+ u32 idle;
+ u32 threshold;
+ u32 ilr[96];
+ u32 mir_0;
+ u32 mir_1;
+ u32 mir_2;
+};
+
+/* Structure to save control module context */
+struct control_module_context {
+ u32 sysconfig;
+ u32 devconf0;
+ u32 mem_dftrw0;
+ u32 mem_dftrw1;
+ u32 msuspendmux_0;
+ u32 msuspendmux_1;
+ u32 msuspendmux_2;
+ u32 msuspendmux_3;
+ u32 msuspendmux_4;
+ u32 msuspendmux_5;
+ u32 sec_ctrl;
+ u32 devconf1;
+ u32 csirxfe;
+ u32 iva2_bootaddr;
+ u32 iva2_bootmod;
+ u32 debobs_0;
+ u32 debobs_1;
+ u32 debobs_2;
+ u32 debobs_3;
+ u32 debobs_4;
+ u32 debobs_5;
+ u32 debobs_6;
+ u32 debobs_7;
+ u32 debobs_8;
+ u32 prog_io0;
+ u32 prog_io1;
+ u32 dss_dpll_spreading;
+ u32 core_dpll_spreading;
+ u32 per_dpll_spreading;
+ u32 usbhost_dpll_spreading;
+ u32 pbias_lite;
+ u32 temp_sensor;
+ u32 sramldo4;
+ u32 sramldo5;
+ u32 csi;
+};
+
+/* Structure to save gpmc cs context */
+struct gpmc_cs_context {
+ int cs_valid;
+ u32 config1;
+ u32 config2;
+ u32 config3;
+ u32 config4;
+ u32 config5;
+ u32 config6;
+ u32 config7;
+};
+
+/* Structure to save gpmc context */
+struct gpmc_context {
+ u32 sysconfig;
+ u32 irqenable;
+ u32 timeout_ctrl;
+ u32 config;
+ u32 prefetch_config1;
+ u32 prefetch_config2;
+ u32 prefetch_control;
+ struct gpmc_cs_context cs0_context;
+ struct gpmc_cs_context cs1_context;
+ struct gpmc_cs_context cs2_context;
+ struct gpmc_cs_context cs3_context;
+ struct gpmc_cs_context cs4_context;
+ struct gpmc_cs_context cs5_context;
+ struct gpmc_cs_context cs6_context;
+ struct gpmc_cs_context cs7_context;
+};
+
+/* Register Types */
+enum regtype {
+ REG_FCLKEN,
+ REG_ICLKEN,
+ REG_IDLEST,
+ REG_AUTOIDLE,
+ REG_WKEN,
+ REG_WKST,
+ REG_CLKSTCTRL,
+ REG_CLKSTST,
+ REG_PWSTCTRL,
+ REG_PWSTST,
+ REG_PREPWSTST,
+ REG_CLK_SRC,
+ REG_RSTST,
+ PRCM_REG_TYPES,
+};
+
+enum dpll_regtype {
+ REG_CLKEN_PLL,
+ REG_AUTOIDLE_PLL,
+ REG_CLKSEL1_PLL,
+ REG_IDLEST_PLL,
+ REG_M2_DIV_PLL,
+ REG_M2X2_DIV_PLL,
+ REG_M3_DIV_PLL,
+ REG_M4_DIV_PLL,
+ REG_M5_DIV_PLL,
+ REG_M6_DIV_PLL,
+ PRCM_DPLL_REG_TYPES,
+};
+
+struct dpll_param {
+ u32 dpll_m;
+ u32 dpll_n;
+ u32 dpll_freqsel;
+ u32 dpll_m2;
+};
+
+struct system_power_state {
+ u32 iva2_state;
+ u32 gfx_state;
+ u32 dss_state;
+ u32 cam_state;
+ u32 per_state;
+ u32 neon_state;
+#ifdef CONFIG_OMAP3430_ES2
+ u32 usbhost_state;
+#endif
+ u32 mpu_state;
+ u32 core_state;
+};
+/* Offset of MX registers in the pll_register array*/
+#define MX_ARRAY_OFFSET REG_M2_DIV_PLL
+/* Structure to store the attributes of register */
+struct reg_def {
+ u32 valid_bits;
+ volatile u32 *reg_addr;
+};
+
+struct sysconf_reg {
+ u32 device_id;
+ volatile u32 *reg_addr;
+ };
+/* Structure to store attributes of registers in a domain */
+struct domain_registers {
+ struct reg_def regdef[PRCM_REG_TYPES];
+};
+
+/* Structure to store DPLL information */
+struct dpll_registers {
+ struct reg_def regdef[PRCM_DPLL_REG_TYPES];
+};
+
+/* Structure for mpu, core and VDD states */
+/* This structure will be used in OS Idle code */
+struct mpu_core_vdd_state {
+ u32 mpu_state;
+ u32 core_state;
+ u32 vdd_state;
+};
+
+/* SDRC/GPMC params for DVFS */
+
+struct sdrc_config {
+ u32 sdrc_rfr_ctrl;
+ u32 sdrc_actim_ctrla;
+ u32 sdrc_actim_ctrlb;
+};
+
+struct gpmc_config {
+ u32 gpmc_config2;
+ u32 gpmc_config3;
+ u32 gpmc_config4;
+ u32 gpmc_config5;
+ u32 gpmc_config6;
+};
+
+#define no_sdrc_cs 2
+#define no_gpmc_cs 4
+
+struct dvfs_config {
+ struct sdrc_config sdrc_cfg[no_sdrc_cs];
+ struct gpmc_config gpmc_cfg[no_gpmc_cs];
+};
+
+extern int prcm_clock_control(u32 deviceid, u8 clk_type, u8 control,
+ u8 checkaccessibility);
+extern int prcm_is_device_accessible(u32 deviceid, u8 * result);
+extern int prcm_interface_clock_autoidle(u32 deviceid, u8 control);
+extern int prcm_wakeup_event_control(u32 deviceid, u8 control);
+
+/* DPLL control APIs */
+extern int prcm_enable_dpll(u32 dpll);
+extern int prcm_configure_dpll(u32 dpll, u32 mult, u8 div, u8 freq_sel);
+extern int prcm_put_dpll_in_bypass(u32 dpll, u32 bypass_mode);
+extern int prcm_dpll_clock_auto_control(u32 dpll, u32 setting);
+extern int prcm_get_dpll_mn_output(u32 dpll, u32 * mn_output);
+extern int prcm_get_dpll_rate(u32 dpll, u32 * rate);
+extern int prcm_configure_dpll_divider(u32 dpll, u32 setting);
+
+/* Other APIs*/
+extern int prcm_get_power_domain_state(u32 domainid, u8 * result);
+extern int prcm_get_pre_power_domain_state(u32 domainid, u8 * result);
+extern int prcm_is_clock_domain_active(u32 domainid, u8 * result);
+extern int prcm_set_clock_domain_state(u32 domainid, u8 new_state,
+ u8 check_state);
+extern int prcm_set_power_domain_state(u32 domainid, u8 new_state, u8 mode);
+extern int prcm_get_devices_not_idle(u32 domainid, u32 * result);
+extern int prcm_get_initiators_not_standby(u32 domainid, u32 * result);
+extern int prcm_get_domain_interface_clocks(u32 domainid, u32 * result);
+extern int prcm_get_domain_functional_clocks(u32 domainid, u32 * result);
+extern int prcm_set_domain_interface_clocks(u32 domainid, u32 setmask);
+extern int prcm_set_domain_functional_clocks(u32 domainid, u32 setmask);
+extern int prcm_get_crystal_rate(void);
+extern int prcm_get_system_clock_speed(void);
+extern int prcm_select_system_clock_divider(u32 setting);
+extern int prcm_control_external_output_clock1(u32 control);
+extern int prcm_control_external_output_clock2(u32 control);
+extern int prcm_select_external_output_clock2_divider(u32 setting);
+extern int prcm_select_external_output_clock2_source(u32 setting);
+extern int prcm_clksel_get_divider(u32 clk, u32 * div);
+extern int prcm_clksel_set_divider(u32 clk, u32 div);
+extern int prcm_get_processor_speed(u32 domainid, u32 * processor_speed);
+extern int prcm_clksel_round_rate(u32 clk, u32 parent_rate, u32 target_rate,
+ u32 * newdiv);
+extern int prcm_clk_set_source(u32 clk_id, u32 parent_id);
+extern int prcm_clk_get_source(u32 clk_id, u32 * parent_id);
+extern int prcm_set_power_configuration(u32 domainid, u8 idlemode,
+ u8 standbymode, u8 autoidleenable);
+extern int prcm_set_wkup_dependency(u32 domainid, u32 wkup_dep);
+extern int prcm_set_sleep_dependency(u32 domainid, u32 sleep_dep);
+extern int prcm_clear_wkup_dependency(u32 domainid, u32 wkup_dep);
+extern int prcm_clear_sleep_dependency(u32 domainid, u32 sleep_dep);
+extern int prcm_set_mpu_domain_state(u32 mpu_dom_state);
+extern int prcm_set_core_domain_state(u32 core_dom_state);
+extern void prcm_printreg(u32 domainid);
+
+extern int prcm_init(void);
+extern int prcm_set_domain_power_configuration(u32 domainid, u8 idlemode,
+ u8 standbymode, u8 autoidleenable);
+extern int prcm_set_device_power_configuration(u32 deviceid, u8 idlemode,
+ u8 standbymode, u8 autoidleenable);
+extern int get_dpll_m_n(u32 dpll_id, u32 * mult, u32 * div);
+/* Level 2 PRCM APIs */
+extern int prcm_do_frequency_scaling(u32 target_opp, u32 current_opp);
+extern int prcm_do_voltage_scaling(u32 target_opp, u32 current_opp);
+extern int prcm_force_power_domain_state(u32 domain, u8 state);
+extern int prcm_set_chip_power_mode(struct system_power_state *target_state,
+ u32 wakeup_source);
+extern void omap_dma_global_context_restore(void);
+extern void omap_dma_global_context_save(void);
+extern int prcm_lock_iva_dpll(u32 target_opp);
+extern void omap_udelay(u32 delay);
+extern void prcm_save_core_context(u32 target_core_state);
+
+void clear_domain_reset_status(void);
+u32 omap_prcm_get_reset_sources(void);
+
+extern int sr_voltagescale_vcbypass(u32 target_opp, u8 vsel);
+#endif
diff --git a/include/asm-arm/arch-omap/system.h
b/include/asm-arm/arch-omap/system.h
index 4faeb9f..07cea26 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -15,6 +15,8 @@
#define voiceblue_reset() do {} while (0)
#endif
+extern void omap_prcm_arch_reset(char mode);
+
static inline void arch_idle(void)
{
cpu_do_idle();
diff --git a/include/asm-arm/arch-omap/twl4030.h
b/include/asm-arm/arch-omap/twl4030.h
new file mode 100644
index 0000000..0bdde3e
--- /dev/null
+++ b/include/asm-arm/arch-omap/twl4030.h
@@ -0,0 +1,122 @@
+/*
+ * twl4030.h - header for TWL4030 PM and audio CODEC device
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * Based on tlv320aic23.c:
+ * Copyright (c) by Kai Svahn <kai....@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __TWL4030_H_
+#define __TWL4030_H_
+
+/* USB ID */
+#define TWL4030_MODULE_USB 0x00
+/* AUD ID */
+#define TWL4030_MODULE_AUDIO_VOICE 0x01
+#define TWL4030_MODULE_GPIO 0x02
+#define TWL4030_MODULE_INTBR 0x03
+#define TWL4030_MODULE_PIH 0x04
+#define TWL4030_MODULE_TEST 0x05
+/* AUX ID */
+#define TWL4030_MODULE_KEYPAD 0x06
+#define TWL4030_MODULE_MADC 0x07
+#define TWL4030_MODULE_INTERRUPTS 0x08
+#define TWL4030_MODULE_LED 0x09
+#define TWL4030_MODULE_MAIN_CHARGE 0x0A
+#define TWL4030_MODULE_PRECHARGE 0x0B
+#define TWL4030_MODULE_PWM0 0x0C
+#define TWL4030_MODULE_PWM1 0x0D
+#define TWL4030_MODULE_PWMA 0x0E
+#define TWL4030_MODULE_PWMB 0x0F
+/* POWER ID */
+#define TWL4030_MODULE_BACKUP 0x10
+#define TWL4030_MODULE_INT 0x11
+#define TWL4030_MODULE_PM_MASTER 0x12
+#define TWL4030_MODULE_PM_RECEIVER 0x13
+#define TWL4030_MODULE_RTC 0x14
+#define TWL4030_MODULE_SECURED_REG 0x15
+
+/* IRQ information-need base */
+#include <asm/arch/irqs.h>
+/* TWL4030 interrupts */
+
+#define TWL4030_MODIRQ_GPIO (IH_TWL4030_BASE + 0)
+#define TWL4030_MODIRQ_KEYPAD (IH_TWL4030_BASE + 1)
+#define TWL4030_MODIRQ_BCI (IH_TWL4030_BASE + 2)
+#define TWL4030_MODIRQ_MADC (IH_TWL4030_BASE + 3)
+#define TWL4030_MODIRQ_USB (IH_TWL4030_BASE + 4)
+#define TWL4030_MODIRQ_PWR (IH_TWL4030_BASE + 5)
+/* Rest are unsued currently*/
+
+/* Offsets to Power Registers */
+#define TWL4030_VDAC_DEV_GRP 0x3B
+#define TWL4030_VDAC_DEDICATED 0x3E
+#define TWL4030_VAUX1_DEV_GRP 0x17
+#define TWL4030_VAUX1_DEDICATED 0x1A
+#define TWL4030_VAUX2_DEV_GRP 0x1B
+#define TWL4030_VAUX2_DEDICATED 0x1E
+#define TWL4030_VAUX3_DEV_GRP 0x1F
+#define TWL4030_VAUX3_DEDICATED 0x22
+#define TWL4030_VPLL2_DEV_GRP 0x33
+#define TWL4030_VPLL2_DEDICATED 0x36
+
+/* TWL4030 GPIO interrupt definitions */
+
+#define TWL4030_GPIO_MIN 0
+#define TWL4030_GPIO_MAX 18
+#define TWL4030_GPIO_MAX_CD 2
+#define TWL4030_GPIO_IRQ_NO(n) (IH_TWL4030_GPIO_BASE+n)
+#define TWL4030_GPIO_IS_INPUT 1
+#define TWL4030_GPIO_IS_OUTPUT 0
+#define TWL4030_GPIO_IS_ENABLE 1
+#define TWL4030_GPIO_IS_DISABLE 0
+#define TWL4030_GPIO_PULL_UP 0
+#define TWL4030_GPIO_PULL_DOWN 1
+#define TWL4030_GPIO_PULL_NONE 2
+#define TWL4030_GPIO_EDGE_NONE 0
+#define TWL4030_GPIO_EDGE_RISING 1
+#define TWL4030_GPIO_EDGE_FALLING 2
+
+/* Functions to read and write from TWL4030 */
+
+/*
+ * IMP NOTE:
+ * The base address of the module will be added by the triton driver
+ * It is the caller's responsibility to ensure sane values
+ */
+int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
+int twl4030_i2c_read_u8(u8 mod_no, u8* val, u8 reg);
+
+ /*
+ * i2c_write: IMPORTANT - Allocate value num_bytes+1 and valid data starts
at
+ * Offset 1.
+ */
+int twl4030_i2c_write(u8 mod_no, u8 * value, u8 reg, u8 num_bytes);
+int twl4030_i2c_read(u8 mod_no, u8 * value, u8 reg, u8 num_bytes);
+
+/*
+ * Exported TWL4030 GPIO APIs
+ */
+int twl4030_get_gpio_datain(int gpio);
+int twl4030_request_gpio(int gpio);
+int twl4030_set_gpio_edge_ctrl(int gpio, int edge);
+int twl4030_set_gpio_debounce(int gpio, int enable);
+int twl4030_free_gpio(int gpio);
+
+#endif /* End of __TWL4030_H */
diff --git a/include/asm-arm/arch-omap/venc.h
b/include/asm-arm/arch-omap/venc.h
new file mode 100644
index 0000000..f7f15a7
--- /dev/null
+++ b/include/asm-arm/arch-omap/venc.h
@@ -0,0 +1,583 @@
+/*
+ * include/asm-arm/arch-omap24xx/venc.h
+ *
+ * Copyright (C) 2004-2005 Texas Instruments, Inc.
+ * TV Standard configuration for Video Encoder in OMAP24XX
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ */
+
+
+/* TV Encoder initialization for PAL and NTSC */
+
+/* Typical encoder values for different TV tests */
+#define VENC_HFLTR_CTRL_EN 0x00000000
+#define VENC_X_COLOR_VAL 0x00000000
+
+#define VENC_LINE21_VAL 0x00000000
+#define VENC_LN_SEL_VAL 0x00000015
+#define VENC_HTRIGGER_VTRIGGER_VAL 0x00000000
+
+#define VENC_TVDETGP_INT_START_STOP_X_VAL 0x00140001
+#define VENC_TVDETGP_INT_START_STOP_Y_VAL 0x00010001
+#define VENC_GEN_CTRL_VAL 0x00FF0000
+#define VENC_GEN_CTRL_PAL_VAL 0x00F90000
+
+/* DAC enable and in normal operation */
+#ifdef CONFIG_ARCH_OMAP2420
+#define VENC_DAC_ENABLE 0x00000002
+#endif
+
+#ifdef CONFIG_ARCH_OMAP2430
+#define VENC_DAC_ENABLE 0x0000000A
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3430
+#define VENC_DAC_ENABLE 0x0000000D
+#endif
+
+/*Values that are same for NTSC, PAL-M AND PAL-60 */
+#define F_CONTROL_GEN 0x00000000
+#define SYNC_CONTROL_GEN 0x00001040
+#define VENC_LLEN_GEN 0x00000359
+#define VENC_FLENS_GEN 0x0000020C
+#define VENC_C_PHASE_GEN 0x00000000
+#define VENC_CC_CARR_WSS_CARR_GEN 0x000025ed
+#define VENC_L21_WC_CTL_GEN 0x00170000
+#define VENC_SAVID_EAVID_GEN 0x069300F4
+#define VENC_FLEN_FAL_GEN 0x0016020C
+#define VENC_HS_EXT_START_STOP_X_GEN 0x000F0359
+#define VENC_VS_INT_START_X_GEN 0x01A00000
+#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN 0x020D01AC
+#define VENC_VS_EXT_STOP_Y_GEN 0x00000006
+#define VENC_FID_INT_START_X_FID_INT_START_Y_GEN 0x0001008A
+#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN 0x01AC0106
+#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN 0x01060006
+
+
+/* Values that are same for PAL-BDGHI, PAL-N, PAL-NC */
+
+#define VENC_LLEN_PAL 0x0000035F
+#define VENC_FLENS_PAL 0x00000270
+
+#define VENC_LLEN_PAL_M 0x00000359
+#define VENC_FLENS_PAL_M 0x0000020C
+
+#define VENC_C_PHASE_PAL 0x000000F0 /* BDGHI & N */
+#define VENC_C_PHASE_PAL_NC 0x00000000
+
+#define VENC_CC_CARR_WSS_CARR_PAL 0x000025ED
+
+#define VENC_L21_WC_CTL_PAL 0x00000000
+
+#define VENC_SAVID_EAVID_PAL 0x06A70108
+#define VENC_FLEN_FAL_PAL 0x00170270
+#define VENC_HS_EXT_START_STOP_X_PAL 0x000F035F
+#define VENC_VS_INT_START_X_PAL 0x01A70000
+#define VENC_VS_EXT_STOP_Y_PAL 0x00000005
+
+#define VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL 0x027101AF
+
+#define VENC_GAIN_U_PAL_BDGHI 0x00000130
+
+
+#define VENC_GAIN_U_PAL_N 0x000000FD
+#define VENC_GAIN_U_PAL_NC 0x00000130
+#define VENC_GAIN_U_PAL_M 0x00000140
+#define VENC_GAIN_U_PAL_60 0x00000140
+
+#define VENC_GAIN_V_PAL_BDGHI 0x000001B0
+
+#define VENC_GAIN_V_PAL_N 0x00000165
+#define VENC_GAIN_V_PAL_NC 0x000001B0
+#define VENC_GAIN_V_PAL_M 0x00000190
+#define VENC_GAIN_V_PAL_60 0x00000190
+
+#define VENC_GAIN_Y_PAL_BDGHI 0x000001B0
+#define VENC_GAIN_Y_PAL_N 0x00000177
+#define VENC_GAIN_Y_PAL_NC 0x000001B0
+#define VENC_GAIN_Y_PAL_M 0x000001C0
+#define VENC_GAIN_Y_PAL_60 0x000001C0
+
+#define VENC_BLACK_LEVEL_PAL_BDGHI 0x00000067
+
+#define VENC_BLANK_LEVEL_PAL_BDGHI 0x00000067
+#define VENC_BLACK_LEVEL_PAL_NC 0x00000063
+#define VENC_BLANK_LEVEL_PAL_NC 0x00000063
+
+#define VENC_BLACK_LEVEL_PAL_N 0x00000060
+#define VENC_BLANK_LEVEL_PAL_N 0x00000053
+
+#define VENC_BLACK_LEVEL_PAL_M 0x00000069
+#define VENC_BLANK_LEVEL_PAL_M 0x0000005C
+
+#define VENC_BLACK_LEVEL_PAL_60 0x00000069
+#define VENC_BLANK_LEVEL_PAL_60 0x0000005C
+
+#define VENC_M_CONTROL_PAL 0x00000002
+#define VENC_M_CONTROL_PAL_M 0x00000003
+#define VENC_M_CONTROL_PAL_60 0x00000003
+
+#define VENC_BSTAMP_WSS_DATA_PAL_BDGHI 0x00000043
+
+#define VENC_BSTAMP_WSS_DATA_PAL_N 0x00000038
+#define VENC_BSTAMP_WSS_DATA_PAL_M 0x0000003F
+#define VENC_BSTAMP_WSS_DATA_PAL_NC 0x00000041
+#define VENC_BSTAMP_WSS_DATA_PAL_60 0x0000003F
+
+#define VENC_S_CARR_PAL_M 0x21E6EFE3
+#define VENC_S_CARR_PAL_NC 0x21E6EFE3
+#define VENC_S_CARR_PAL_BDGHI 0x2A098ACB
+#define VENC_S_CARR_PAL_60 0x2A098ACB
+
+
+
+#define VENC_LAL_PHASE_RESET_PAL 0x00040136 /* BDGHI & N */
+#define VENC_LAL_PHASE_RESET_PAL_NC 0x00040135
+#define VENC_LAL_PHASE_RESET_PAL_2 0x00040107 /* PAL-M & PAL-60 */
+
+#define VENC_HS_INT_START_STOP_X_PAL 0x00920358 /* BDGHI & N */
+#define VENC_HS_INT_START_STOP_X_NC 0x00880358
+#define VENC_HS_INT_START_STOP_X_PAL_2 0x007e034e /* PAL-M & PAL-60 */
+
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL 0x000601A7
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2 0x020901a0 /* PAL-M &
PAL-60*/
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_NC 0x026F01A7
+
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL 0x01AF0036
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2 0x01ac0022 /* PAL-M & PAL-60
*/
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_NC 0x01AF002E
+
+#define VENC_AVID_START_STOP_X_PAL 0x03530082 /* BDGHI & N */
+#define VENC_AVID_START_STOP_X_PAL_NC 0x03530083
+#define VENC_AVID_START_STOP_X_PAL_2 0x03530082 /* PAL-M & PAL-60 */
+
+#define VENC_AVID_START_STOP_Y_PAL 0x0270002E
+#define VENC_AVID_START_STOP_Y_PAL_2 0x0270002E /* PAL-M & PAL-60 */
+#define VENC_AVID_START_STOP_Y_PAL_NC 0x026E002E
+
+#define VENC_FID_INT_START_X_FID_INT_START_Y_PAL 0x0005008A
+
+#define VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL 0x002E0138
+
+
+#define VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_PAL 0x01380005
+
+/* NTSC */
+#define VENC_GAIN_U_NTSC_M 0x00000102
+#define VENC_GAIN_U_NTSC_J 0x00000100
+#define VENC_GAIN_U_NTSC_443 0x00000140
+
+#define VENC_GAIN_V_NTSC_M 0x0000016C
+#define VENC_GAIN_V_NTSC_J 0x0000016D
+#define VENC_GAIN_V_NTSC_443 0x00000190
+
+#define VENC_GAIN_Y_NTSC_M 0x0000012F
+#define VENC_GAIN_Y_NTSC_J 0x00000196
+#define VENC_GAIN_Y_NTSC_443 0x000001C0
+
+#define VENC_BLACK_LEVEL_NTSC_443 0x00000069
+#define VENC_BLANK_LEVEL_NTSC_443 0x0000005C
+
+#define VENC_BLACK_LEVEL_NTSC_M 0x00000043
+#define VENC_BLANK_LEVEL_NTSC_M 0x00000038
+
+#define VENC_BLACK_LEVEL_NTSC_J 0x00000053
+#define VENC_BLANK_LEVEL_NTSC_J 0x00000053
+
+#define VENC_M_CONTROL_NTSC 0x00000001
+
+#define VENC_BSTAMP_WSS_DATA_NTSC 0x00000038
+#define VENC_BSTAMP_WSS_DATA_NTSC_443 0x0000003F
+
+#define VENC_S_CARR_NTSC_443 0x2A098ACB
+#define VENC_S_CARR_NTSC 0x21F07C1F
+
+#define VENC_HTRIGGER_VTRIGGER_VAL 0x00000000
+
+#define VENC_FLEN_FAL_NTSC 0x0001020C
+
+#define VENC_LAL_PHASE_RESET_NTSC 0x00060107
+
+#define VENC_HS_INT_START_STOP_X_NTSC 0x007E034E
+
+#define VENC_HS_INT_START_STOP_X_443 0x007e034e
+
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC 0x020901A0
+#define VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC_443 0x020901a0
+
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC 0x01AC0022
+#define VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC_443 0x01ac0022
+
+#define VENC_AVID_START_STOP_X_NTSC 0x032000A0
+#define VENC_AVID_START_STOP_X_NTSC_443 0x03480079
+
+#define VENC_AVID_START_STOP_Y_NTSC 0x02060026
+#define VENC_AVID_START_STOP_Y_NTSC_443 0x02040024
+
+#define VENC_TVDETGP_INT_START_STOP_X_GEN 0x00140001
+#define VENC_TVDETGP_INT_START_STOP_Y_GEN 0x00010001
+
+
+struct tv_standard_config{
+ u32 venc_llen;
+ u32 venc_flens;
+ u32 venc_hfltr_ctrl;
+ u32 venc_cc_carr_wss_carr;
+ u32 venc_c_phase;
+ u32 venc_gain_u;
+ u32 venc_gain_v;
+ u32 venc_gain_y;
+ u32 venc_black_level;
+ u32 venc_blank_level;
+ u32 venc_x_color;
+ u32 venc_m_control;
+ u32 venc_bstamp_wss_data;
+ u32 venc_s_carr;
+ u32 venc_line21;
+ u32 venc_ln_sel;
+ u32 venc_l21_wc_ctl;
+ u32 venc_htrigger_vtrigger;
+ u32 venc_savid_eavid;
+ u32 venc_flen_fal;
+ u32 venc_lal_phase_reset;
+ u32 venc_hs_int_start_stop_x;
+ u32 venc_hs_ext_start_stop_x;
+ u32 venc_vs_int_start_x;
+ u32 venc_vs_int_stop_x_vs_int_start_y;
+ u32 venc_vs_int_stop_y_vs_ext_start_x;
+ u32 venc_vs_ext_stop_x_vs_ext_start_y;
+ u32 venc_vs_ext_stop_y;
+ u32 venc_avid_start_stop_x;
+ u32 venc_avid_start_stop_y;
+ u32 venc_fid_int_start_x_fid_int_start_y;
+ u32 venc_fid_int_offset_y_fid_ext_start_x;
+ u32 venc_fid_ext_start_y_fid_ext_offset_y;
+ u32 venc_tvdetgp_int_start_stop_x;
+ u32 venc_tvdetgp_int_start_stop_y;
+ u32 venc_gen_ctrl;
+ u32 venc_dac_tst;
+};
+
+static struct tv_standard_config pal_bdghi_cfg = {
+ VENC_LLEN_PAL,
+ VENC_FLENS_PAL,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_PAL,
+ VENC_C_PHASE_PAL,
+ VENC_GAIN_U_PAL_BDGHI,
+ VENC_GAIN_V_PAL_BDGHI,
+ VENC_GAIN_Y_PAL_BDGHI,
+ VENC_BLACK_LEVEL_PAL_BDGHI,
+ VENC_BLANK_LEVEL_PAL_BDGHI,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_PAL,
+ VENC_BSTAMP_WSS_DATA_PAL_BDGHI,
+ VENC_S_CARR_PAL_BDGHI,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_PAL,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_PAL,
+ VENC_FLEN_FAL_PAL,
+ VENC_LAL_PHASE_RESET_PAL,
+ VENC_HS_INT_START_STOP_X_PAL,
+ VENC_HS_EXT_START_STOP_X_PAL,
+ VENC_VS_INT_START_X_PAL,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,
+ VENC_VS_EXT_STOP_Y_PAL,
+ VENC_AVID_START_STOP_X_PAL,
+ VENC_AVID_START_STOP_Y_PAL,
+ VENC_FID_INT_START_X_FID_INT_START_Y_PAL,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_PAL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config pal_n_cfg = {
+ VENC_LLEN_PAL,
+ VENC_FLENS_PAL,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_PAL,
+ VENC_C_PHASE_PAL,
+ VENC_GAIN_U_PAL_N,
+ VENC_GAIN_V_PAL_N,
+ VENC_GAIN_Y_PAL_N,
+ VENC_BLACK_LEVEL_PAL_N,
+ VENC_BLANK_LEVEL_PAL_N,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_PAL,
+ VENC_BSTAMP_WSS_DATA_PAL_BDGHI,
+ VENC_S_CARR_PAL_BDGHI,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_PAL,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_PAL,
+ VENC_FLEN_FAL_PAL,
+ VENC_LAL_PHASE_RESET_PAL,
+ VENC_HS_INT_START_STOP_X_PAL,
+ VENC_HS_EXT_START_STOP_X_PAL,
+ VENC_VS_INT_START_X_PAL,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,
+ VENC_VS_EXT_STOP_Y_PAL,
+ VENC_AVID_START_STOP_X_PAL,
+ VENC_AVID_START_STOP_Y_PAL,
+ VENC_FID_INT_START_X_FID_INT_START_Y_PAL,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_PAL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config pal_nc_cfg = {
+ VENC_LLEN_PAL,
+ VENC_FLENS_PAL,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_PAL,
+ VENC_C_PHASE_PAL,
+ VENC_GAIN_U_PAL_NC,
+ VENC_GAIN_V_PAL_NC,
+ VENC_GAIN_Y_PAL_NC,
+ VENC_BLACK_LEVEL_PAL_NC,
+ VENC_BLANK_LEVEL_PAL_NC,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_PAL,
+ VENC_BSTAMP_WSS_DATA_PAL_NC,
+ VENC_S_CARR_PAL_NC,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_PAL,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_PAL,
+ VENC_FLEN_FAL_PAL,
+ VENC_LAL_PHASE_RESET_PAL_NC,
+ VENC_HS_INT_START_STOP_X_NC,
+ VENC_HS_EXT_START_STOP_X_PAL,
+ VENC_VS_INT_START_X_PAL,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_NC,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_NC,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_PAL,
+ VENC_VS_EXT_STOP_Y_PAL,
+ VENC_AVID_START_STOP_X_PAL_NC,
+ VENC_AVID_START_STOP_Y_PAL_NC,
+ VENC_FID_INT_START_X_FID_INT_START_Y_PAL,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_PAL,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_PAL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config pal_m_cfg = {
+ VENC_LLEN_PAL_M,
+ VENC_FLENS_PAL_M,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_GEN,
+ VENC_C_PHASE_GEN,
+ VENC_GAIN_U_PAL_M,
+ VENC_GAIN_V_PAL_M,
+ VENC_GAIN_Y_PAL_M,
+ VENC_BLACK_LEVEL_PAL_M,
+ VENC_BLANK_LEVEL_PAL_M,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_PAL_M,
+ VENC_BSTAMP_WSS_DATA_PAL_M,
+ VENC_S_CARR_PAL_M,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_GEN,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_GEN,
+ VENC_FLEN_FAL_GEN,
+ VENC_LAL_PHASE_RESET_PAL_2,
+ VENC_HS_INT_START_STOP_X_PAL_2,
+ VENC_HS_EXT_START_STOP_X_GEN,
+ VENC_VS_INT_START_X_GEN,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
+ VENC_VS_EXT_STOP_Y_GEN,
+ VENC_AVID_START_STOP_X_PAL_2,
+ VENC_AVID_START_STOP_Y_PAL_2,
+ VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config pal_60_cfg = {
+ VENC_LLEN_GEN,
+ VENC_FLENS_GEN,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_GEN,
+ VENC_C_PHASE_GEN,
+ VENC_GAIN_U_PAL_60,
+ VENC_GAIN_V_PAL_60,
+ VENC_GAIN_Y_PAL_60,
+ VENC_BLACK_LEVEL_PAL_60,
+ VENC_BLANK_LEVEL_PAL_60,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_PAL_60,
+ VENC_BSTAMP_WSS_DATA_PAL_60,
+ VENC_S_CARR_PAL_60,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_GEN,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_GEN,
+ VENC_FLEN_FAL_GEN,
+ VENC_LAL_PHASE_RESET_PAL_2,
+ VENC_HS_INT_START_STOP_X_PAL_2,
+ VENC_HS_EXT_START_STOP_X_GEN,
+ VENC_VS_INT_START_X_GEN,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_PAL_2,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_PAL_2,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
+ VENC_VS_EXT_STOP_Y_GEN,
+ VENC_AVID_START_STOP_X_PAL_2,
+ VENC_AVID_START_STOP_Y_PAL_2,
+ VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config ntsc_m_cfg = {
+ VENC_LLEN_GEN,
+ VENC_FLENS_GEN,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_GEN,
+ VENC_C_PHASE_GEN,
+ VENC_GAIN_U_NTSC_M,
+ VENC_GAIN_V_NTSC_M,
+ VENC_GAIN_Y_NTSC_M,
+ VENC_BLACK_LEVEL_NTSC_M,
+ VENC_BLANK_LEVEL_NTSC_M,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_NTSC,
+ VENC_BSTAMP_WSS_DATA_NTSC,
+ VENC_S_CARR_NTSC,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_GEN,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_GEN,
+ VENC_FLEN_FAL_GEN,
+ VENC_LAL_PHASE_RESET_NTSC,
+ VENC_HS_INT_START_STOP_X_NTSC,
+ VENC_HS_EXT_START_STOP_X_GEN,
+ VENC_VS_INT_START_X_GEN,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
+ VENC_VS_EXT_STOP_Y_GEN,
+ VENC_AVID_START_STOP_X_NTSC,
+ VENC_AVID_START_STOP_Y_NTSC,
+ VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config ntsc_443_cfg = {
+ VENC_LLEN_GEN,
+ VENC_FLENS_GEN,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_GEN,
+ VENC_C_PHASE_GEN,
+ VENC_GAIN_U_NTSC_443,
+ VENC_GAIN_V_NTSC_443,
+ VENC_GAIN_Y_NTSC_443,
+ VENC_BLACK_LEVEL_NTSC_443,
+ VENC_BLANK_LEVEL_NTSC_443,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_NTSC,
+ VENC_BSTAMP_WSS_DATA_NTSC_443,
+ VENC_S_CARR_NTSC_443,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_GEN,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_GEN,
+ VENC_FLEN_FAL_GEN,
+ VENC_LAL_PHASE_RESET_NTSC,
+ VENC_HS_INT_START_STOP_X_443,
+ VENC_HS_EXT_START_STOP_X_GEN,
+ VENC_VS_INT_START_X_GEN,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC_443,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC_443,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
+ VENC_VS_EXT_STOP_Y_GEN,
+ VENC_AVID_START_STOP_X_NTSC_443,
+ VENC_AVID_START_STOP_Y_NTSC_443,
+ VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_VAL,
+ VENC_DAC_ENABLE
+};
+
+static struct tv_standard_config ntsc_j_cfg = {
+ VENC_LLEN_GEN,
+ VENC_FLENS_GEN,
+ VENC_HFLTR_CTRL_EN,
+ VENC_CC_CARR_WSS_CARR_GEN,
+ VENC_C_PHASE_GEN,
+ VENC_GAIN_U_NTSC_J,
+ VENC_GAIN_V_NTSC_J,
+ VENC_GAIN_Y_NTSC_J,
+ VENC_BLACK_LEVEL_NTSC_J,
+ VENC_BLANK_LEVEL_NTSC_J,
+ VENC_X_COLOR_VAL,
+ VENC_M_CONTROL_NTSC,
+ VENC_BSTAMP_WSS_DATA_NTSC,
+ VENC_S_CARR_NTSC,
+ VENC_LINE21_VAL,
+ VENC_LN_SEL_VAL,
+ VENC_L21_WC_CTL_GEN,
+ VENC_HTRIGGER_VTRIGGER_VAL,
+ VENC_SAVID_EAVID_GEN,
+ VENC_FLEN_FAL_GEN,
+ VENC_LAL_PHASE_RESET_NTSC,
+ VENC_HS_INT_START_STOP_X_NTSC,
+ VENC_HS_EXT_START_STOP_X_GEN,
+ VENC_VS_INT_START_X_GEN,
+ VENC_VS_INT_STOP_X_VS_INT_START_Y_NTSC,
+ VENC_VS_INT_STOP_Y_VS_EXT_START_X_NTSC,
+ VENC_VS_EXT_STOP_X_VS_EXT_START_Y_GEN,
+ VENC_VS_EXT_STOP_Y_GEN,
+ VENC_AVID_START_STOP_X_NTSC,
+ VENC_AVID_START_STOP_Y_NTSC,
+ VENC_FID_INT_START_X_FID_INT_START_Y_GEN,
+ VENC_FID_INT_OFFSET_Y_FID_EXT_START_X_GEN,
+ VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y_GEN,
+ VENC_TVDETGP_INT_START_STOP_X_GEN,
+ VENC_TVDETGP_INT_START_STOP_Y_GEN,
+ VENC_GEN_CTRL_VAL,
+ VENC_DAC_ENABLE
+};
Eduardo Valentin
Thanks for this patch. Good work.
I've tried your patch and it works here in my beagle. But with the
same issue of noise.
The behaviour is the same as with original kernel from TI.
However, if you think in submitting this patch to linux-omap I think
we need to work
a bit on it :).
First suggestion is to start splitting it into a series of little
patches by features.
Anyway, I've tried it into 3430 SDP, and with a few changes it worked as well.
Cheers,
> +#ifdef CON...
>
> [Message clipped]
--
Eduardo Bezerra Valentin