Patch[1/4]:This patch adds board directory for BeagleBoard.
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sunil
Apr 2, 2008, 9:24:58 AM4/2/08
to Beagle Board
This patch adds board directory for BeagleBoard.
Signed-off-by:
Sunil Kumar <sunils...@gmail.com>
Shashi Ranjan <shashira...@gmail.com>
Syed Mohammed Khasim <kha...@ti.com>
---
Makefile | 47
beagle_logo_FNL_2.h | 8815 +++++++++++++++++++++++++++++++++++++++++++
+++++++++
clock.c | 350 ++
config.mk | 17
lowlevel_init.S | 361 ++
mem.c | 263 +
nand.c | 455 ++
omap3530beagle.c | 1142 ++++++
sys_info.c | 331 +
syslib.c | 74
u-boot.lds | 63
11 files changed, 11918 insertions(+)
diff -purN orig_u-boot/board/omap3530beagle/beagle_logo_FNL_2.h u-
boot_beagle/board/omap3530beagle/beagle_logo_FNL_2.h
--- orig_u-boot/board/omap3530beagle/beagle_logo_FNL_2.h 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/beagle_logo_FNL_2.h 2008-04-02
16:57:33.000000000 +0530
@@ -0,0 +1,8815 @@
+/* GIMP header image file format (RGB): /home/darrene/beagle/u-boot/
board/omap3530beagle/beagle_logo_FNL_2.h */
+
+static unsigned int beagle_width = 1280;
+static unsigned int beagle_height = 110;
+
+/* Call this macro repeatedly. After each use, the pixel data can
be extracted */
+
+#define HEADER_PIXEL(data,pixel) {\
+ pixel[0] = (((data[0] - 33) << 2) | ((data[1] - 33) >> 4)); \
+ pixel[1] = ((((data[1] - 33) & 0xF) << 4) | ((data[2] - 33) >> 2));
\
+ pixel[2] = ((((data[2] - 33) & 0x3) << 6) | ((data[3] - 33))); \
+ data += 4; \
+}
+static char *header_data =
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````_`T\\R]L*"
+ "DJ/49GFI3F.31%J*4665<(&RGJ[?VN@8````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````S=H*DJ+29WJK3F.415N+5&B9:WVNG*O;V^@9"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````^P@XR=D)BYS,97>H3&\"115N+4VB8;X*RH;+C"
+ "W>P;````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "R]@(CZ#09GFJ3F.315N+36*2:GVMFZO;UN04````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ ">(J[66V=1UV-/U:'25Z.8'.C@9/#J[OLVND9^P@W````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "W^X=_0DY````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "L,#QW.L;^`@X````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "`@\\_`0T]_`P\\_PL[_0DY]@(R[/DIWNP<U.(2U>,3U>,3U.(2V><7Y?(B\\/
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+ "_PL[_`P\\`0T]`P\\_````````````````````````````````````````````````"
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+ "^<5B^<5B^<1@^<):^<-=_-:5__3N`PHM````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
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+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````Y_4D"
+ "KKWN=HBY4F>71%F)05:&/%&!-4Q^,DI\\,$A[+4=[+TA\\,4E],TI^-DM_.DU_05!`"
+ "0U&!0E&!0E&!0U&!/4]_.$Q_-$I_,DI],$E]+D=\\+D=[,DI[.$Y^/%*\"0%6%36&1"
+ "<(&RK;SMZ_DI````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````[OPLM\\;W@)+\"66N<1EF*05:&/%*\"-
DU^"
+ ",$E\\+$=Z+$=[*D9[*T=\\+DE],TM_.TU`/U!`/U%`05)`1U=_1U=_0%!`-TM`,4I^"
+ "+TI]*T=[*T9[+$=Z+D=[-$M].E!`0%6%2E^/8W>GGZ_@X.X>````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "``````````````HQ`/C\\_N?+_=RI^]20^]..^]2/^]..^]21_=RJ__+L`P@J````"
+ "````````````````````````````````````````````````````````````````"
+ "`````````````````````````````````````P@K`//O_=RL^]21^]..^]2/^]2/"
+ "^]2/^].-_-B<_NC.`?`5_`T_`P``````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "`````````````````````````````````````````````````````````````P\\_"
+ "_`P\\_0HYX>`?N<CYD*#197>G1UR,-TU],DAX,TIZ-$M[-4M\\-DQ\\-DQ\\-$M]-
$M]"
+ "-$M]-$M]-$M]-$M]-$I]-$M\\-DQ\\-4Q\\-4M[-$IZ,DAX-
$IZ2U^0:WZNFJK;S]X-"
+ "^08U_`T]`P\\_````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "`````````````````````````````````P\\_`0T]`0T]Y_4EO\\[_E*75;'^O36*2"
+ ".4]_,4AX,TIZ-$I[-4M[-$M\\,TI\\-$I]-$M]-$M]-$M]-$M]-$M]-$M],TI\\,TI\
\"
+ "-4Q\\-4M[-$IZ,DEY-$IZ15N+872DDJ+3R]D)\\O`P_PL[`P\
\_````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "```````````````_``\\]``X[``XZ``TY``TX``TY``TX``XY``XZ``\\\
\```_````"
+ "````````````````````````````````````````````````````````````````"
+ "```````````````````````````````````````_``\\]``XZ``XY``TX``TY``TY"
+ "``TY``TX``XY``X[``\\^````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "`````````@\\^]`4U[/HJX>\\?S]\\.NLGZH[/DC9_/=HFY8W:F5FF93&&215J
+0%>("
+ "/U:'0%:'0%:'/U:&1%J+3&\"156B97G*B;X&QA);&FZS=M,/TT=`0X>`?[_TM_@HZ"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````^@8V[?LKX_$ATN(1"
+ "O<S\\I;;FD*+2?(Z_9WJK66R=4&252%V.05>(/U:&0%:'/U:'/U:'0EB)1UV.4&25"
+ "7&^?;'^O@9/$EZC9K[[OS=T,WNT<[?LK_0DY````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "````````````````````````````````````````````````````````````````"
+ "";
diff -purN orig_u-boot/board/omap3530beagle/clock.c u-boot_beagle/
board/omap3530beagle/clock.c
--- orig_u-boot/board/omap3530beagle/clock.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/clock.c 2008-04-02
16:37:06.000000000 +0530
@@ -0,0 +1,350 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunils...@gmail.com>
+ * Shashi Ranjan <shashira...@gmail.com>
+ *
+ * Derived from Beagle Board and OMAP3 SDP code by
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <environment.h>
+#include <command.h>
+
+/* Used to index into DPLL parameter tables */
+struct dpll_param {
+ unsigned int m;
+ unsigned int n;
+ unsigned int fsel;
+ unsigned int m2;
+};
+
+typedef struct dpll_param dpll_param;
+
+/* Following functions are exported from lowlevel_init.S */
+
+extern dpll_param *get_mpu_dpll_param(void);
+extern dpll_param *get_iva_dpll_param(void);
+extern dpll_param *get_core_dpll_param(void);
+extern dpll_param *get_per_dpll_param(void);
+
+/*************************************************************
+ * get_sys_clk_speed - determine reference oscillator speed
+ * based on known 32kHz clock and gptimer.
+ *************************************************************/
+u32 get_osc_clk_speed(void)
+{
+ u32 start, cstart, cend, cdiff, val;
+
+ val = __raw_readl(PRM_CLKSRC_CTRL);
+
+ /* If SYS_CLK is being divided by 2, remove for now */
+ val = (val & (~BIT7)) | BIT6;
+ __raw_writel(val, PRM_CLKSRC_CTRL);
+
+ /* enable timer2 */
+ val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+ __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
+
+ /* Enable I and F Clocks for GPT1 */
+ val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
+ __raw_writel(val, CM_ICLKEN_WKUP);
+ val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
+ __raw_writel(val, CM_FCLKEN_WKUP);
+
+ __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
+ __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
+ /* enable 32kHz source */
+ /* determine sys_clk via gauging */
+
+ start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
+ while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time
*/
+ cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk
count */
+ while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles
*/
+ cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count
*/
+ cdiff = cend - cstart; /* get elapsed ticks */
+
+ /* based on number of ticks assign speed */
+ if (cdiff > 19000)
+ return (S38_4M);
+ else if (cdiff > 15200)
+ return (S26M);
+ else if (cdiff > 13000)
+ return (S24M);
+ else if (cdiff > 9000)
+ return (S19_2M);
+ else if (cdiff > 7600)
+ return (S13M);
+ else
+ return (S12M);
+}
+
+/
******************************************************************************
+ * get_sys_clkin_sel() - returns the sys_clkin_sel field value based
on
+ * -- input oscillator clock frequency.
+ *
+
*****************************************************************************/
+void get_sys_clkin_sel(u32 osc_clk, u32 * sys_clkin_sel)
+{
+ if (osc_clk == S38_4M)
+ *sys_clkin_sel = 4;
+ else if (osc_clk == S26M)
+ *sys_clkin_sel = 3;
+ else if (osc_clk == S19_2M)
+ *sys_clkin_sel = 2;
+ else if (osc_clk == S13M)
+ *sys_clkin_sel = 1;
+ else if (osc_clk == S12M)
+ *sys_clkin_sel = 0;
+}
+
+/
******************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+
*****************************************************************************/
+void prcm_init(void)
+{
+ void (*f_lock_pll) (u32, u32, u32, u32);
+ int xip_safe, p0, p1, p2, p3;
+ u32 osc_clk = 0, sys_clkin_sel;
+ extern void *_end_vect, *_start;
+ u32 clk_index, sil_index;
+ dpll_param *dpll_param_p;
+
+ f_lock_pll =
+ (void *) ((u32) & _end_vect - (u32) & _start + SRAM_VECT_CODE);
+
+ xip_safe = running_in_sram();
+
+ /* Gauge the input clock speed and find out the sys_clkin_sel
+ * value corresponding to the input clock.
+ */
+ osc_clk = get_osc_clk_speed();
+ get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+
+ sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
+
+ /* If the input clock is greater than 19.2M always divide/2 */
+ if (sys_clkin_sel > 2) {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
+ clk_index = sys_clkin_sel / 2;
+ } else {
+ sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
+ clk_index = sys_clkin_sel;
+ }
+
+ /* The DPLL tables are defined according to sysclk value and
+ * silicon revision. The clk_index value will be used to get
+ * the values for that input sysclk from the DPLL param table
+ * and sil_index will get the values for that SysClk for the
+ * appropriate silicon rev.
+ */
+ sil_index = get_cpu_rev() - 1;
+ /* Unlock MPU DPLL (slows things down, and needed later) */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address of Core DPLL param table */
+ dpll_param_p = (dpll_param *) get_core_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+ if (xip_safe) {
+ /* CORE DPLL */
+ /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
+ /* For OMAP3 ES1.0 Errata 1.50, default value directly doesnt
+ work. write another value and then default value. */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
+ sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
+ sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
+ sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
+ sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
+ sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
+ sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+ } else if (running_in_flash()) {
+ /* if running from flash, jump to small relocated code area in
SRAM. */
+ p0 = __raw_readl(CM_CLKEN_PLL);
+ sr32((u32) & p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ sr32((u32) & p0, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+
+ p1 = __raw_readl(CM_CLKSEL1_PLL);
+ sr32((u32) & p1, 27, 2, dpll_param_p->m2); /* Set M2 */
+ sr32((u32) & p1, 16, 11, dpll_param_p->m); /* Set M */
+ sr32((u32) & p1, 8, 7, dpll_param_p->n); /* Set N */
+ sr32((u32) & p1, 6, 1, 0); /* set source for 96M */
+ p2 = __raw_readl(CM_CLKSEL_CORE);
+ sr32((u32) & p2, 8, 4, CORE_SSI_DIV); /* ssi */
+ sr32((u32) & p2, 4, 2, CORE_FUSB_DIV); /* fsusb */
+ sr32((u32) & p2, 2, 2, CORE_L4_DIV); /* l4 */
+ sr32((u32) & p2, 0, 2, CORE_L3_DIV); /* l3 */
+
+ p3 = CM_IDLEST_CKGEN;
+
+ (*f_lock_pll) (p0, p1, p2, p3);
+ }
+
+ /* PER DPLL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
+ wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to PER DPLL param table */
+ /* Set N */
+ dpll_param_p = (dpll_param *) get_per_dpll_param();
+ /* Moving it to the right sysclk base */
+ dpll_param_p = dpll_param_p + clk_index;
+ /* Errata 1.50 Workaround for OMAP3 ES1.0 only */
+ /* If using default divisors, write default divisor + 1
+ and then the actual divisor value */
+ /* Need to change it to silicon and revisino check */
+ if (1) {
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2 + 1); /* set M6 */
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2 + 1); /* set M5 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2 + 1); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2 + 1); /* set M3 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2 + 1); /* set M2 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ } else {
+ sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
+ sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
+ sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
+ sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
+ sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
+ }
+ sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
+ sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
+ sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+
+ /* Getting the base address to MPU DPLL param table */
+ dpll_param_p = (dpll_param *) get_mpu_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+ /* MPU DPLL (unlocked already) */
+ sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
+ sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
+ sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
+ sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+
+ /* Getting the base address to IVA DPLL param table */
+ dpll_param_p = (dpll_param *) get_iva_dpll_param();
+ /* Moving it to the right sysclk and ES rev base */
+ dpll_param_p = dpll_param_p + 2 * clk_index + sil_index;
+ /* IVA DPLL (set to 12*20=240MHz) */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+ sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
+ sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
+ sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
+ sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
+ sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
+
+ /* Set up GPTimers to sys_clk source only */
+ sr32(CM_CLKSEL_PER, 0, 8, 0xff);
+ sr32(CM_CLKSEL_WKUP, 0, 1, 1);
+
+ sdelay(5000);
+}
+
+/*****************************************************************
+ * Routine: peripheral_enable
+ * Description: Enable the clks & power for perifs (GPT2, UART1,...)
+ ******************************************************************/
+void per_clocks_enable(void)
+{
+ /* Enable GP2 timer. */
+ sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
+ sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
+ sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
+
+#ifdef CFG_NS16550
+ /* Enable UART1 clocks */
+ sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
+ sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
+
+ /* UART 3 Clocks */
+ sr32(CM_FCLKEN_PER, 11, 1, 0x1);
+ sr32(CM_ICLKEN_PER, 11, 1, 0x1);
+#endif
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ /* Turn on all 3 I2C clocks */
+ sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
+ sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
+#endif
+ /* Enable the ICLK for 32K Sync Timer as its used in udelay */
+ sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
+
+#define CLOCKS_ALL_ON 1
+
+#ifdef CLOCKS_ALL_ON
+
+ #define FCK_IVA2_ON 0x00000001
+ #define FCK_CORE1_ON 0x03fffe29
+ #define ICK_CORE1_ON 0x3ffffffb
+ #define ICK_CORE2_ON 0x0000001f
+ #define FCK_WKUP_ON 0x000000e9
+ #define ICK_WKUP_ON 0x0000003f
+ #define FCK_DSS_ON 0x00000005
+ #define ICK_DSS_ON 0x00000001
+ #define FCK_CAM_ON 0x00000001
+ #define ICK_CAM_ON 0x00000001
+ #define FCK_PER_ON 0x0003ffff
+ #define ICK_PER_ON 0x0003ffff
+
+ sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
+ sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
+ sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
+ sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
+ sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
+ sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
+ sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
+ sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
+ sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
+ sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
+ sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
+ sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
+#endif
+ sdelay(1000);
+}
diff -purN orig_u-boot/board/omap3530beagle/config.mk u-boot_beagle/
board/omap3530beagle/config.mk
--- orig_u-boot/board/omap3530beagle/config.mk 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/config.mk 2008-04-02
16:37:56.000000000 +0530
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Begale Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+
diff -purN orig_u-boot/board/omap3530beagle/lowlevel_init.S u-
boot_beagle/board/omap3530beagle/lowlevel_init.S
--- orig_u-boot/board/omap3530beagle/lowlevel_init.S 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/lowlevel_init.S 2008-04-02
16:20:00.000000000 +0530
@@ -0,0 +1,361 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* sdram load addr from config.mk */
+
+#if !defined(CFG_NAND_BOOT) && !defined(CFG_NAND_BOOT)
+/
**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to
execute
+ * R1 = SRAM destination address.
+
*************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+ /* Copy DPLL code into SRAM */
+ adr r0, go_to_speed /* get addr of clock setting
code */
+ mov r2, #384 /* r2 size to copy (div by 32
bytes) */
+ mov r1, r1 /* r1 <- dest address (passed
in) */
+ add r2, r2, r0 /* r2 <- source end address
*/
+next2:
+ ldmia r0!, {r3-r10} /* copy from source address
[r0] */
+ stmia r1!, {r3-r10} /* copy to target address
[r1] */
+ cmp r0, r2 /* until source end address
[r2] */
+ bne next2
+ mov pc, lr /* back to caller */
+
+/*
****************************************************************************
+ * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts
dpll at speed
+ * -executed from SRAM.
+ * R0 = CM_CLKEN_PLL-bypass value
+ * R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ * R2 = CM_CLKSEL_CORE-divider values
+ * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ * Note: If core unlocks/relocks and SDRAM is running fast already
it gets
+ * confused. A reset of the controller gets it back. Taking
away its
+ * L3 when its not in self refresh seems bad for it.
Normally, this code
+ * runs from flash before SDR is init so that should be ok.
+
******************************************************************************/
+.global go_to_speed
+ go_to_speed:
+ stmfd sp!, {r4-r6}
+
+ /* move into fast relock bypass */
+ ldr r4, pll_ctl_add
+ str r0, [r4]
+wait1:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ beq wait1 /* if lock, loop */
+
+ /* set new dpll dividers _after_ in bypass */
+ ldr r5, pll_div_add1
+ str r1, [r5] /* set m, n, m2 */
+ ldr r5, pll_div_add2
+ str r2, [r5] /* set l3/l4/.. dividers*/
+ ldr r5, pll_div_add3 /* wkup */
+ ldr r2, pll_div_val3 /* rsm val */
+ str r2, [r5]
+ ldr r5, pll_div_add4 /* gfx */
+ ldr r2, pll_div_val4
+ str r2, [r5]
+ ldr r5, pll_div_add5 /* emu */
+ ldr r2, pll_div_val5
+ str r2, [r5]
+
+ /* now prepare GPMC (flash) for new dpll speed */
+ /* flash needs to be stable when we jump back to it */
+ ldr r5, flash_cfg3_addr
+ ldr r2, flash_cfg3_val
+ str r2, [r5]
+ ldr r5, flash_cfg4_addr
+ ldr r2, flash_cfg4_val
+ str r2, [r5]
+ ldr r5, flash_cfg5_addr
+ ldr r2, flash_cfg5_val
+ str r2, [r5]
+ ldr r5, flash_cfg1_addr
+ ldr r2, [r5]
+ orr r2, r2, #0x3 /* up gpmc divider */
+ str r2, [r5]
+
+ /* lock DPLL3 and wait a bit */
+ orr r0, r0, #0x7 /* set up for lock mode */
+ str r0, [r4] /* lock */
+ nop /* ARM slow at this point working at
sys_clk */
+ nop
+ nop
+ nop
+wait2:
+ ldr r5, [r3] /* get status */
+ and r5, r5, #0x1 /* isolate core status */
+ cmp r5, #0x1 /* still locked? */
+ bne wait2 /* if lock, loop */
+ nop
+ nop
+ nop
+ nop
+ ldmfd sp!, {r4-r6}
+ mov pc, lr /* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to
happen */
+flash_cfg1_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+ .word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+ .word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+ .word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+ .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+ .word CM_CLKEN_PLL
+pll_div_add1:
+ .word CM_CLKSEL1_PLL
+pll_div_add2:
+ .word CM_CLKSEL_CORE
+pll_div_add3:
+ .word CM_CLKSEL_WKUP
+pll_div_val3:
+ .word (WKUP_RSM << 1)
+pll_div_add4:
+ .word CM_CLKSEL_GFX
+pll_div_val4:
+ .word (GFX_DIV << 0)
+pll_div_add5:
+ .word CM_CLKSEL1_EMU
+pll_div_val5:
+ .word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr sp, SRAM_STACK
+ str ip, [sp] /* stash old link register */
+ mov ip, lr /* save link reg across call */
+ bl s_init /* go setup pll,mux,memory */
+ ldr ip, [sp] /* restore save ip */
+ mov lr, ip /* restore link reg */
+
+ /* back to arch calling code */
+ mov pc, lr
+
+ /* the literal pools origin */
+ .ltorg
+
+REG_CONTROL_STATUS:
+ .word CONTROL_STATUS
+SRAM_STACK:
+ .word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for
nominal
+ * OPP (1.2V). The fields are defined according to dpll_param
struct(clock.c).
+ * The values are defined for all possible sysclk and for ES1 and
ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE,0x07,0x05,0x01
+/* ES2 */
+.word 0x0FA,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D,0x0C,0x03,0x01
+/* ES2 */
+.word 0x1F4,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179,0x12,0x04,0x01
+/* ES2 */
+.word 0x271,0x17,0x03,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D,0x19,0x03,0x01
+/* ES2 */
+.word 0x0FA,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA,0x32,0x03,0x01
+/* ES2 */
+.word 0x271,0x2F,0x03,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+ adr r0, mpu_dpll_param
+ mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D,0x05,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x05,0x07,0x01
+/* 3410 */
+.word 0x085,0x05,0x07,0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA,0x0C,0x03,0x01
+/* ES2 */
+.word 0x168,0x0C,0x03,0x01
+/* 3410 */
+.word 0x10A,0x0C,0x03,0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082,0x09,0x07,0x01
+/* ES2 */
+.word 0x0E1,0x0B,0x06,0x01
+/* 3410 */
+.word 0x14C,0x17,0x03,0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D,0x0C,0x07,0x01
+/* ES2 */
+.word 0x0B4,0x0C,0x07,0x01
+/* 3410 */
+.word 0x085,0x0C,0x07,0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F,0x30,0x03,0x01
+/* ES2 */
+.word 0x0E1,0x17,0x06,0x01
+/* 3410 */
+.word 0x14C,0x2F,0x03,0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+ adr r0, iva_dpll_param
+ mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1,M_12_ES1,FSL_12_ES1,M2_12_ES1
+/* ES2 */
+.word M_12,N_12,FSEL_12,M2_12
+/* 3410 */
+.word M_12,N_12,FSEL_12,M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1,N_13_ES1,FSL_13_ES1,M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1,N_19p2_ES1,FSL_19p2_ES1,M2_19p2_ES1
+/* ES2 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+/* 3410 */
+.word M_19p2,N_19p2,FSEL_19p2,M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1,N_26_ES1,FSL_26_ES1,M2_26_ES1
+/* ES2 */
+.word M_26,N_26,FSEL_26,M2_26
+/* 3410 */
+.word M_26,N_26,FSEL_26,M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1,N_38p4_ES1,FSL_38p4_ES1,M2_38p4_ES1
+/* ES2 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+/* 3410 */
+.word M_38p4,N_38p4,FSEL_38p4,M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+ adr r0, core_dpll_param
+ mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8,0x05,0x07,0x09
+
+/* 13MHz */
+.word 0x1B0,0x0C,0x03,0x09
+
+/* 19.2MHz */
+.word 0xE1,0x09,0x07,0x09
+
+/* 26MHz */
+.word 0xD8,0x0C,0x07,0x09
+
+/* 38.4MHz */
+.word 0xE1,0x13,0x07,0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+ adr r0, per_dpll_param
+ mov pc, lr
+
diff -purN orig_u-boot/board/omap3530beagle/Makefile u-boot_beagle/
board/omap3530beagle/Makefile
--- orig_u-boot/board/omap3530beagle/Makefile 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/Makefile 2008-04-02
11:05:56.000000000 +0530
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := omap3530beagle.o mem.o clock.o syslib.o sys_info.o nand.o
+SOBJS := lowlevel_init.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff -purN orig_u-boot/board/omap3530beagle/mem.c u-boot_beagle/board/
omap3530beagle/mem.c
--- orig_u-boot/board/omap3530beagle/mem.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/mem.c 2008-04-02
16:40:49.000000000 +0530
@@ -0,0 +1,263 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code from:
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <environment.h>
+#include <command.h>
+
+/****** DATA STRUCTURES ************/
+
+/* Only One NAND allowed on board at a time.
+ * The GPMC CS Base for the same
+ */
+unsigned int nand_cs_base = 0;
+unsigned int onenand_cs_base = 0;
+unsigned int boot_flash_base = 0;
+unsigned int boot_flash_off = 0;
+unsigned int boot_flash_sec = 0;
+unsigned int boot_flash_type = 0;
+volatile unsigned int boot_flash_env_addr = 0;
+
+/* help common/env_flash.c */
+#ifdef ENV_IS_VARIABLE
+
+ulong NOR_FLASH_BANKS_LIST[CFG_MAX_FLASH_BANKS];
+int NOR_MAX_FLASH_BANKS = 0; /* max number of flash banks */
+
+uchar(*boot_env_get_char_spec) (int index);
+int (*boot_env_init) (void);
+int (*boot_saveenv) (void);
+void (*boot_env_relocate_spec) (void);
+
+/* 16 bit NAND */
+extern uchar env_get_char_spec(int index);
+extern int env_init(void);
+extern int saveenv(void);
+extern void env_relocate_spec(void);
+extern char *env_name_spec;
+
+u8 is_nand = 0;
+
+#endif /* ENV_IS_VARIABLE */
+
+static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+ M_NAND_GPMC_CONFIG1,
+ M_NAND_GPMC_CONFIG2,
+ M_NAND_GPMC_CONFIG3,
+ M_NAND_GPMC_CONFIG4,
+ M_NAND_GPMC_CONFIG5,
+ M_NAND_GPMC_CONFIG6, 0
+};
+
+
+/
**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to
allow
+ * command line mem=xyz use all memory with out discontinuous
support
+ * compiled in. Could do it at the ATAG, but there really is two
banks...
+ * Called as part of 2nd phase DDR init.
+
**************************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(SDRC_CS0_OSET);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ * mem_ok() - test used to see if timings are correct
+ * for a part. Helps in guessing which part
+ * we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+ u32 val1, val2, addr;
+ u32 pattern = 0x12345678;
+
+ addr = OMAP34XX_SDRC_CS0;
+
+ __raw_writel(0x0, addr + 0x400); /* clear pos A */
+ __raw_writel(pattern, addr); /* pattern to pos B */
+ __raw_writel(0x0, addr + 4); /* remove pattern off the bus */
+ val1 = __raw_readl(addr + 0x400); /* get pos A value */
+ val2 = __raw_readl(addr); /* get val2 */
+
+ if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed
*/
+ return (0);
+ else
+ return (1);
+}
+
+/********************************************************
+ * sdrc_init() - init the sdrc chip selects CS0 and CS1
+ * - early init routines, called from flash or
+ * SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+#define EARLY_INIT 1
+ do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT); /* only init up first bank
here */
+}
+
+/
*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ * -code sets up SDRAM basic SDRC timings for CS0
+ * -optimal settings can be placed here, or redone after i2c
+ * inspection of board info
+ *
+ * - code called ones in C-Stack only context for CS0 and a possible
2nd
+ * time depending on memory configuration from stack+global
context
+
**************************************************************************/
+
+void do_sdrc_init(u32 offset, u32 early)
+{
+
+ /* reset sdrc controller */
+ __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+ wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+ __raw_writel(0, SDRC_SYSCONFIG);
+
+ /* setup sdrc to ball mux */
+ __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+
+ /* SDRC_MCFG0 register */
+ (*(unsigned int *) 0x6D000080) = 0x02584099; //from Micron
+
+ /* SDRC_RFR_CTRL0 register */
+ (*(unsigned int *) 0x6D0000a4) = 0x54601; // for 166M
+
+ /* SDRC_ACTIM_CTRLA0 register */
+ (*(unsigned int *) 0x6D00009c) = 0xa29db4c6; // for 166M
+
+ /* SDRC_ACTIM_CTRLB0 register */
+ (*(unsigned int *) 0x6D0000a0) = 0x12214; // for 166M
+
+ /* Disble Power Down of CKE cuz of 1 CKE on combo part */
+ (*(unsigned int *) 0x6D000070) = 0x00000081;
+
+ /* SDRC_Manual command register */
+ (*(unsigned int *) 0x6D0000a8) = 0x00000000; // NOP command
+ (*(unsigned int *) 0x6D0000a8) = 0x00000001; // Precharge command
+ (*(unsigned int *) 0x6D0000a8) = 0x00000002; // Auto-refresh command
+ (*(unsigned int *) 0x6D0000a8) = 0x00000002; // Auto-refresh command
+
+ /* SDRC MR0 register */
+ (*(int *) 0x6D000084) = 0x00000032; // Burst length =4
+ // CAS latency = 3
+ // Write Burst = Read Burst
+ // Serial Mode
+
+ /* SDRC DLLA control register */
+ (*(unsigned int *) 0x6D000060) = 0x0000A;
+ sdelay(0x20000); // some delay
+}
+
+void enable_gpmc_config(u32 * gpmc_config, u32 gpmc_base, u32 base,
u32 size)
+{
+ __raw_writel(0, GPMC_CONFIG7 + gpmc_base);
+ sdelay(1000);
+ /* Delay for settling */
+ __raw_writel(gpmc_config[0], GPMC_CONFIG1 + gpmc_base);
+ __raw_writel(gpmc_config[1], GPMC_CONFIG2 + gpmc_base);
+ __raw_writel(gpmc_config[2], GPMC_CONFIG3 + gpmc_base);
+ __raw_writel(gpmc_config[3], GPMC_CONFIG4 + gpmc_base);
+ __raw_writel(gpmc_config[4], GPMC_CONFIG5 + gpmc_base);
+ __raw_writel(gpmc_config[5], GPMC_CONFIG6 + gpmc_base);
+ /* Enable the config */
+ __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+ (1 << 6)), GPMC_CONFIG7 + gpmc_base);
+ sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ /* putting a blanket check on GPMC based on ZeBu for now */
+ u32 mux = 0, mwidth;
+ u32 *gpmc_config = NULL;
+ u32 gpmc_base = 0;
+ u32 base = 0;
+ u32 size = 0;
+ u32 f_off = CFG_MONITOR_LEN;
+ u32 f_sec = 0;
+ u32 config = 0;
+
+ mux = BIT9;
+ mwidth = get_gpmc0_width();
+
+ /* global settings */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */
+
+ config = __raw_readl(GPMC_CONFIG);
+ config &= (~0xf00);
+ __raw_writel(config, GPMC_CONFIG);
+
+ /* Disable the GPMC0 config set by ROM code
+ * It conflicts with our MPDB (both at 0x08000000)
+ */
+ __raw_writel(0, GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ sdelay(1000);
+
+ /* CS 0 */
+ gpmc_config = gpmc_m_nand;
+ gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH);
+ base = PISMO1_NAND_BASE;
+ size = PISMO1_NAND_SIZE;
+ enable_gpmc_config(gpmc_config, gpmc_base, base, size);
+
+ f_off = SMNAND_ENV_OFFSET;
+ f_sec = SZ_128K;
+ is_nand = 1;
+ nand_cs_base = gpmc_base;
+
+ /* env setup */
+ boot_flash_base = base;
+ boot_flash_off = f_off;
+ boot_flash_sec = f_sec;
+ boot_flash_env_addr = f_off;
+
+#ifdef ENV_IS_VARIABLE
+ boot_env_get_char_spec = env_get_char_spec;
+ boot_env_init = env_init;
+ boot_saveenv = saveenv;
+ boot_env_relocate_spec = env_relocate_spec;
+#endif
+
+}
diff -purN orig_u-boot/board/omap3530beagle/nand.c u-boot_beagle/board/
omap3530beagle/nand.c
--- orig_u-boot/board/omap3530beagle/nand.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/nand.c 2008-04-02
12:26:39.000000000 +0530
@@ -0,0 +1,455 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <roh...@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <linux/mtd/nand_ecc.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+
+unsigned char cs;
+volatile unsigned long gpmc_cs_base_add;
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL 1
+
+#define ECC_P1_128_E(val) ((val) & 0x000000FF) /* Bit 0 to 7 */
+#define ECC_P512_2048_E(val) (((val) & 0x00000F00)>>8) /* Bit 8 to 11
*/
+#define ECC_P1_128_O(val) (((val) & 0x00FF0000)>>16) /* Bit 16 to
Bit 23 */
+#define ECC_P512_2048_O(val) (((val) & 0x0F000000)>>24) /* Bit 24 to
Bit 27 */
+
+/*
+int nand_unlock(struct mtd_info *mtd, unsigned long off, unsigned
long size)
+{
+ register struct nand_chip *this = mtd->priv;
+ int start_page, end_page;
+
+ start_page = (int) (off >> this->page_shift);
+ end_page = (int) ((off + size) >> this->page_shift);
+
+ printk("\nUnlocking %x - %x. locking rest..\n", off, off + size);
+ this->cmdfunc(mtd, 0x23, -1, start_page);
+ this->cmdfunc(mtd, 0x24, -1, end_page);
+ ndelay (100);
+ return 0;
+}
+*/
+/*
+ * omap_nand_hwcontrol - Set the address pointers corretly for the
+ * following address/data/command operation
+ * @mtd: MTD device structure
+ * @ctrl: Says whether Address or Command or Data is following.
+ */
+
+static void omap_nand_hwcontrol(struct mtd_info *mtd, int ctrl)
+{
+ register struct nand_chip *this = mtd->priv;
+
+/*
+ * Point the IO_ADDR to DATA and ADDRESS registers instead of chip
address
+ */
+ switch (ctrl) {
+ case NAND_CTL_SETCLE:
+ this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+ this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ break;
+ case NAND_CTL_SETALE:
+ this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_ADR;
+ this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ break;
+ case NAND_CTL_CLRCLE:
+ this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ break;
+ case NAND_CTL_CLRALE:
+ this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ break;
+ }
+}
+
+/*
+ * omap_nand_wait - called primarily after a program/erase operation
+ * so that we access NAND again only after the device
+ * is ready again.
+ * @mtd: MTD device structure
+ * @chip: nand_chip structure
+ * @state: State from which wait function is being called i.e write/
erase.
+ */
+static int omap_nand_wait(struct mtd_info *mtd, struct nand_chip
*chip,
+ int state)
+{
+ register struct nand_chip *this = mtd->priv;
+ int status = 0;
+
+ this->IO_ADDR_W = (void *) gpmc_cs_base_add + GPMC_NAND_CMD;
+ this->IO_ADDR_R = (void *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ /* Send the status command and loop until the device is free */
+ while (!(status & 0x40)) {
+ __raw_writeb(NAND_CMD_STATUS & 0xFF, this->IO_ADDR_W);
+ status = __raw_readb(this->IO_ADDR_R);
+ }
+ return status;
+}
+
+/*
+ * omap_nand_dev_ready - Wait for the NAND device to exit busy state
+ * by polling on RDY/BSY signal
+ * @mtd: MTD device structure
+ */
+#if 0
+static int omap_nand_dev_ready(struct mtd_info *mtd)
+{
+ unsigned int wait_status = 0;
+
+ /* busy loop until NAND device is RDY again */
+ while (!(wait_status & (1 << (cs + 8))))
+ wait_status = __raw_readl(GPMC_IRQSTATUS);
+ /* clear the status register for further usage */
+ __raw_writel(1 << (cs + 8), GPMC_IRQSTATUS);
+ return 1;
+}
+#endif
+
+#ifdef CFG_NAND_WIDTH_16
+/**
+ * omap_nand_write_buf16 - [DEFAULT] write buffer to chip
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ *
+ * Default write function for 16bit buswith
+ */
+static void omap_nand_write_buf(struct mtd_info *mtd, const u_char *
buf,
+ int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+ u16 *p = (u16 *) buf;
+ len >>= 1;
+
+ for (i = 0; i < len; i++) {
+ writew(p[i], this->IO_ADDR_W);
+ while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL)) ;
+ }
+}
+
+/**
+ * nand_read_buf16 - [DEFAULT] read chip data into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ *
+ * Default read function for 16bit buswith
+ */
+
+static void omap_nand_read_buf(struct mtd_info *mtd, u_char * buf,
int len)
+{
+ int i;
+ struct nand_chip *this = mtd->priv;
+ u16 *p = (u16 *) buf;
+ len >>= 1;
+
+ for (i = 0; i < len; i++)
+ p[i] = readw(this->IO_ADDR_R);
+}
+
+#else
+/*
+ * omap_nand_write_buf - write buffer to NAND controller
+ * @mtd: MTD device structure
+ * @buf: data buffer
+ * @len: number of bytes to write
+ *
+ */
+
+static void omap_nand_write_buf(struct mtd_info *mtd, const uint8_t *
buf,
+ int len)
+{
+ int i;
+ int j = 0;
+ struct nand_chip *chip = mtd->priv;
+
+ for (i = 0; i < len; i++) {
+ writeb(buf[i], chip->IO_ADDR_W);
+ for (j = 0; j < 10; j++) ;
+ }
+
+}
+
+/*
+ * omap_nand_read_buf - read data from NAND controller into buffer
+ * @mtd: MTD device structure
+ * @buf: buffer to store date
+ * @len: number of bytes to read
+ *
+ */
+
+static void omap_nand_read_buf(struct mtd_info *mtd, uint8_t * buf,
int len)
+{
+ int i;
+ int j = 0;
+ struct nand_chip *chip = mtd->priv;
+
+ for (i = 0; i < len; i++) {
+ buf[i] = readb(chip->IO_ADDR_R);
+ while (GPMC_BUF_EMPTY == (readl(GPMC_STATUS) & GPMC_BUF_FULL)) ;
+ }
+}
+#endif
+
+/*
+ * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
GPMC controller
+ * @mtd: MTD device structure
+ *
+ */
+static void omap_hwecc_init(struct nand_chip *chip)
+{
+ unsigned long val = 0x0;
+
+ /* Init ECC Control Register */
+ /* Clear all ECC | Enable Reg1 */
+ val = ((0x00000001 << 8) | 0x00000001);
+ __raw_writel(val, GPMC_BASE + GPMC_ECC_CONTROL);
+ __raw_writel(0x3fcff000, GPMC_BASE + GPMC_ECC_SIZE_CONFIG);
+}
+
+/*
+ * omap_correct_data - Compares the ecc read from nand spare area
with ECC registers values
+ * and corrects one bit error if it has occured
+ * @mtd: MTD device structure
+ * @dat: page data
+ * @read_ecc: ecc read from nand flash
+ * @calc_ecc: ecc read from ECC registers
+ */
+static int omap_correct_data(struct mtd_info *mtd, u_char * dat,
+ u_char * read_ecc, u_char * calc_ecc)
+{
+ return 0;
+}
+
+/*
+ * omap_calculate_ecc - Generate non-inverted ECC bytes.
+ *
+ * Using noninverted ECC can be considered ugly since writing a
blank
+ * page ie. padding will clear the ECC bytes. This is no problem as
+ * long nobody is trying to write data on the seemingly unused page.
+ * Reading an erased page will produce an ECC mismatch between
+ * generated and read ECC bytes that has to be dealt with
separately.
+ * @mtd: MTD structure
+ * @dat: unused
+ * @ecc_code: ecc_code buffer
+*/
+
+static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *
dat,
+ u_char * ecc_code)
+{
+ unsigned long val = 0x0;
+ unsigned long reg;
+
+ /* Start Reading from HW ECC1_Result = 0x200 */
+ reg = (unsigned long) (GPMC_BASE + GPMC_ECC1_RESULT);
+ val = __raw_readl(reg);
+
+ *ecc_code++ = ECC_P1_128_E(val);
+ *ecc_code++ = ECC_P1_128_O(val);
+ *ecc_code++ = ECC_P512_2048_E(val) | ECC_P512_2048_O(val) << 4;
+
+ return 0;
+}
+
+/*
+ * omap_enable_ecc - This function enables the hardware ecc
functionality
+ * @mtd: MTD device structure
+ * @mode: Read/Write mode
+ */
+static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ struct nand_chip *chip = mtd->priv;
+ unsigned int val = __raw_readl(GPMC_BASE + GPMC_ECC_CONFIG);
+ unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
+
+ switch (mode) {
+ case NAND_ECC_READ:
+ __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL);
+ /* ECC col width) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (cs << 1) | (0x1);
+ break;
+ case NAND_ECC_READSYN:
+ __raw_writel(0x100, GPMC_BASE + GPMC_ECC_CONTROL);
+ /* ECC col width) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (cs << 1) | (0x1);
+ break;
+ case NAND_ECC_WRITE:
+ __raw_writel(0x101, GPMC_BASE + GPMC_ECC_CONTROL);
+ /* ECC col width) | ( CS ) | ECC Enable */
+ val = (dev_width << 7) | (cs << 1) | (0x1);
+ break;
+ default:
+ printf("Error: Unrecognized Mode[%d]!\n", mode);
+ break;
+ }
+
+ __raw_writel(val, GPMC_BASE + GPMC_ECC_CONFIG);
+}
+
+static struct nand_oobinfo hw_nand_oob_64 = {
+ .useecc = MTD_NANDECC_AUTOPLACE,
+ .eccbytes = 12,
+ .eccpos = {
+ 2, 3, 4, 5,
+ 6, 7, 8, 9,
+ 10, 11, 12, 13},
+ .oobfree = {{20, 50}} /* don't care */
+};
+
+static struct nand_oobinfo sw_nand_oob_64 = {
+ .useecc = MTD_NANDECC_AUTOPLACE,
+ .eccbytes = 24,
+ .eccpos = {
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63},
+ .oobfree = {{2, 38}}
+};
+
+void omap_nand_switch_ecc(struct mtd_info *mtd, int hardware)
+{
+ struct nand_chip *nand = mtd->priv;
+
+ if (!hardware) {
+ nand->eccmode = NAND_ECC_SOFT;
+ nand->autooob = &sw_nand_oob_64;
+ nand->eccsize = 256; /* set default eccsize */
+ nand->eccbytes = 3;
+ nand->eccsteps = 8;
+ nand->enable_hwecc = 0;
+ nand->calculate_ecc = nand_calculate_ecc;
+ nand->correct_data = nand_correct_data;
+ } else {
+ nand->eccmode = NAND_ECC_HW3_512;
+ nand->autooob = &hw_nand_oob_64;
+ nand->eccsize = 512;
+ nand->eccbytes = 3;
+ nand->eccsteps = 4;
+ nand->enable_hwecc = omap_enable_hwecc;
+ nand->correct_data = omap_correct_data;
+ nand->calculate_ecc = omap_calculate_ecc;
+
+ omap_hwecc_init(nand);
+ }
+
+ mtd->eccsize = nand->eccsize;
+ nand->oobdirty = 1;
+
+ if (nand->options & NAND_BUSWIDTH_16) {
+ mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 2);
+ if (nand->autooob->eccbytes & 0x01)
+ mtd->oobavail--;
+ } else
+ mtd->oobavail = mtd->oobsize - (nand->autooob->eccbytes + 1);
+}
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand_new.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/
busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc
generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array
to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for
further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+ int gpmc_config = 0;
+ cs = 0;
+ while (cs <= GPMC_MAX_CS) {
+ /* Each GPMC set for a single CS is at offset 0x30 */
+ /* already remapped for us */
+ gpmc_cs_base_add = (GPMC_CONFIG_CS0 + (cs * 0x30));
+ /* xloader/Uboot would have written the NAND type for us
+ * -NOTE This is a temporary measure and cannot handle ONENAND.
+ * The proper way of doing this is to pass the setup of u-boot up
to kernel
+ * using kernel params - something on the lines of machineID
+ */
+ /* Check if NAND type is set */
+ if ((__raw_readl(gpmc_cs_base_add + GPMC_CONFIG1) & 0xC00) ==
+ 0x800) {
+ /* Found it!! */
+ break;
+ }
+ cs++;
+ }
+ if (cs > GPMC_MAX_CS) {
+ printk
+ ("NAND: Unable to find NAND settings in GPMC Configuration -
quitting\n");
+ }
+
+ gpmc_config = __raw_readl(GPMC_CONFIG);
+ /* Disable Write protect */
+ gpmc_config |= 0x10;
+ __raw_writel(gpmc_config, GPMC_CONFIG);
+
+ nand->IO_ADDR_R = (int *) gpmc_cs_base_add + GPMC_NAND_DAT;
+ nand->IO_ADDR_W = (int *) gpmc_cs_base_add + GPMC_NAND_CMD;
+
+ nand->hwcontrol = omap_nand_hwcontrol;
+ nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR |
+ NAND_BUSWIDTH_16 | NAND_NO_AUTOINCR;
+ nand->read_buf = omap_nand_read_buf;
+ nand->write_buf = omap_nand_write_buf;
+ nand->eccmode = NAND_ECC_SOFT;
+/* if RDY/BSY line is connected to OMAP then use the omap ready
function
+ * and the generic nand_wait function which reads the status register
after
+ * monitoring the RDY/BSY line. Otherwise use a standard chip delay
which
+ * is slightly more than tR (AC Timing) of the NAND device and read
the
+ * status register until you get a failure or success
+ */
+
+#if 0
+ nand->dev_ready = omap_nand_dev_ready;
+#else
+ nand->waitfunc = omap_nand_wait;
+ nand->chip_delay = 50;
+#endif
+
+ return 0;
+}
+
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff -purN orig_u-boot/board/omap3530beagle/omap3530beagle.c u-
boot_beagle/board/omap3530beagle/omap3530beagle.c
--- orig_u-boot/board/omap3530beagle/omap3530beagle.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/omap3530beagle.c 2008-04-02
17:03:27.000000000 +0530
@@ -0,0 +1,1142 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunils...@gmail.com>
+ * Shashi Ranjan <shashira...@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/mem.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+#include "beagle_logo_FNL_2.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#include <linux/mtd/nand_legacy.h>
+extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+#endif
+
+/*
+ * Dummy functions to handle errors for EABI incompatibility
+ */
+void raise(void)
+{
+}
+
+void abort(void)
+{
+}
+
+
+/*******************************************************
+ * Routine: delay
+ * Description: spinning delay to use before udelay works
+ ******************************************************/
+static inline void delay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************/
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; /* board id for
Linux */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); /* boot param
addr */
+
+ return 0;
+}
+
+/*****************************************
+ * Routine: secure_unlock
+ * Description: Setup security registers for access
+ * (GP Device only)
+ *****************************************/
+void secure_unlock_mem(void)
+{
+ /* Permission values for registers -Full fledged permissions to all
*/
+#define UNLOCK_1 0xFFFFFFFF
+#define UNLOCK_2 0x00000000
+#define UNLOCK_3 0x0000FFFF
+ /* Protection Module Register Target APE (PM_RT) */
+ __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+ __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+
+ __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+ __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+
+ /* IVA Changes */
+ __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+ __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+
+ __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
+}
+
+/**********************************************************
+ * Routine: secureworld_exit()
+ * Description: If chip is EMU and boot type is external
+ * configure secure registers and exit secure world
+ * general use.
+ ***********************************************************/
+void secureworld_exit()
+{
+ unsigned long i;
+
+ /* configrue non-secure access control register */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
+ /* enabling co-processor CP10 and CP11 accesses in NS world */
+ __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
+ /* allow allocation of locked TLBs and L2 lines in NS world */
+ /* allow use of PLE registers in NS world also */
+ __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
+
+ /* Enable ASA in ACR register */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+
+ /* Exiting secure world */
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
+}
+
+/**********************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ * general use.
+ ***********************************************************/
+void setup_auxcr()
+{
+ unsigned long i;
+ volatile unsigned int j;
+ /* Save r0, r12 and restore them after usage */
+ __asm__ __volatile__("mov %0, r12":"=r"(j));
+ __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+ /* GP Device ROM code API usage here */
+ /* r12 = AUXCR Write function and r0 value */
+ __asm__ __volatile__("mov r12, #0x3");
+ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+ /* Enabling ASA */
+ __asm__ __volatile__("orr r0, r0, #0x10");
+ /* SMI instruction to call ROM Code API */
+ __asm__ __volatile__(".word 0xE1600070");
+ __asm__ __volatile__("mov r0, %0":"=r"(i));
+ __asm__ __volatile__("mov r12, %0":"=r"(j));
+}
+
+/**********************************************************
+ * Routine: try_unlock_sram()
+ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
+ * general use.
+ ***********************************************************/
+void try_unlock_memory()
+{
+ int mode;
+ int in_sdram = running_in_sdram();
+
+ /* if GP device unlock device SRAM for general use */
+ /* secure code breaks for Secure/Emulation device - HS/E/T */
+ mode = get_device_type();
+ if (mode == GP_DEVICE) {
+ secure_unlock_mem();
+ }
+ /* If device is EMU and boot is XIP external booting
+ * Unlock firewalls and disable L2 and put chip
+ * out of secure world
+ */
+ /* Assuming memories are unlocked by the demon who put us in SDRAM
*/
+ if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
+ && (!in_sdram)) {
+ secure_unlock_mem();
+ secureworld_exit();
+ }
+
+ return;
+}
+
+/**********************************************************
+ * Routine: s_init
+ * Description: Does early system init of muxing and clocks.
+ * - Called path is with SRAM stack.
+ **********************************************************/
+void s_init(void)
+{
+ int in_sdram = running_in_sdram();
+
+#ifdef CONFIG_3430VIRTIO
+ in_sdram = 0; /* allow setup from memory for Virtio */
+#endif
+ watchdog_init();
+
+ try_unlock_memory();
+
+ /* Right now flushing at low MPU speed. Need to move after clock
init */
+ v7_flush_dcache_all(get_device_type());
+#ifndef CONFIG_ICACHE_OFF
+ icache_enable();
+#endif
+
+#ifdef CONFIG_L2_OFF
+ l2cache_disable();
+#else
+ l2cache_enable();
+#endif
+ /* Writing to AuxCR in U-boot using SMI for GP DEV */
+ /* Currently SMI in Kernel on ES2 devices seems to have an isse
+ * Once that is resolved, we can postpone this config to kernel
+ */
+ if (get_device_type() == GP_DEVICE)
+ setup_auxcr();
+
+ set_muxconf_regs();
+ delay(100);
+
+ prcm_init();
+
+ per_clocks_enable();
+
+ if (!in_sdram)
+ sdrc_init();
+}
+
+ushort tone[] = {
+ 0x0ce4, 0x0ce4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+ 0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+ 0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+ 0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+ 0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+ 0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+ 0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+ 0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+ 0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+ 0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+ 0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+ 0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+ 0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+ 0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+ 0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+ 0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+ 0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+ 0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+ 0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+ 0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+ 0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+ 0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000,
+ 0x0CE4, 0x0CE4, 0x1985, 0x1985, 0x25A1, 0x25A1, 0x30FD, 0x30FE,
+ 0x3B56, 0x3B55, 0x447A, 0x447A, 0x4C3B, 0x4C3C, 0x526D, 0x526C,
+ 0x56F1, 0x56F1, 0x59B1, 0x59B1, 0x5A9E, 0x5A9D, 0x59B1, 0x59B2,
+ 0x56F3, 0x56F2, 0x526D, 0x526D, 0x4C3B, 0x4C3B, 0x447C, 0x447C,
+ 0x3B5A, 0x3B59, 0x30FE, 0x30FE, 0x25A5, 0x25A6, 0x1989, 0x198A,
+ 0x0CE5, 0x0CE3, 0x0000, 0x0000, 0xF31C, 0xF31C, 0xE677, 0xE676,
+ 0xDA5B, 0xDA5B, 0xCF03, 0xCF03, 0xC4AA, 0xC4AA, 0xBB83, 0xBB83,
+ 0xB3C5, 0xB3C5, 0xAD94, 0xAD94, 0xA90D, 0xA90E, 0xA64F, 0xA64E,
+ 0xA562, 0xA563, 0xA64F, 0xA64F, 0xA910, 0xA90F, 0xAD93, 0xAD94,
+ 0xB3C4, 0xB3C4, 0xBB87, 0xBB86, 0xC4AB, 0xC4AB, 0xCF03, 0xCF03,
+ 0xDA5B, 0xDA5A, 0xE67B, 0xE67B, 0xF31B, 0xF3AC, 0x0000, 0x0000
+};
+
+void audio_init()
+{
+
+ unsigned char byte;
+
+ printf("Audio Tone on Speakers");
+ byte = 0x20;
+ i2c_write(0x4B, 0x7A, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x7D, 1, &byte, 1);
+ byte = 0xE0;
+ i2c_write(0x4B, 0x8E, 1, &byte, 1);
+ byte = 0x05;
+ i2c_write(0x4B, 0x91, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x49, 0x01, 1, &byte, 1);
+ byte = 0xc0;
+ i2c_write(0x49, 0x02, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x03, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x04, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x05, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x06, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x07, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x08, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x09, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x0a, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x0b, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x0c, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x0d, 1, &byte, 1);
+ byte = 0x01;
+ i2c_write(0x49, 0x0e, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x0f, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x10, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x11, 1, &byte, 1);
+ byte = 0x6c;
+ i2c_write(0x49, 0x12, 1, &byte, 1);
+ byte = 0x6c;
+ i2c_write(0x49, 0x13, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x14, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x15, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x16, 1, &byte, 1);
+ byte = 0x0c;
+ i2c_write(0x49, 0x17, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x18, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x19, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x1a, 1, &byte, 1);
+ byte = 0x2b;
+ i2c_write(0x49, 0x1b, 1, &byte, 1);
+ byte = 0x2b;
+ i2c_write(0x49, 0x1c, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x1d, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x1e, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x1f, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x20, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x21, 1, &byte, 1);
+ byte = 0x24;
+ i2c_write(0x49, 0x22, 1, &byte, 1);
+ byte = 0x0a;
+ i2c_write(0x49, 0x23, 1, &byte, 1);
+ byte = 0x42;
+ i2c_write(0x49, 0x24, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x25, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x26, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x27, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x28, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x29, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2a, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2b, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2c, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2d, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2e, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x2f, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x30, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x31, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x32, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x33, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x34, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x35, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x36, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x37, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x38, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x39, 1, &byte, 1);
+ byte = 0x15;
+ i2c_write(0x49, 0x3a, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x3b, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x3c, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x3d, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x3e, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x3f, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x40, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x41, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x42, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x43, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x44, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x45, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x46, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x47, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x48, 1, &byte, 1);
+ byte = 0x00;
+ i2c_write(0x49, 0x49, 1, &byte, 1);
+
+ *((uint *) 0x4902208c) = 0x00000208;
+ *((uint *) 0x49022090) = 0x00000000;
+ *((uint *) 0x49022094) = 0x00000000;
+ *((uint *) 0x490220ac) = 0x00001008;
+ *((uint *) 0x490220b0) = 0x00000808;
+ *((uint *) 0x49022018) = 0x00000000;
+ *((uint *) 0x4902201c) = 0x00000000;
+ *((uint *) 0x49022020) = 0x00000000;
+ *((uint *) 0x49022024) = 0x00000000;
+ *((uint *) 0x49022028) = 0x00000000;
+ *((uint *) 0x4902202c) = 0x00000000;
+ *((uint *) 0x49022048) = 0x00000083;
+ *((uint *) 0x49022010) = 0x00000200;
+ *((uint *) 0x49022014) = 0x00000000;
+ *((uint *) 0x4902207c) = 0x00000023;
+ *((uint *) 0x49022010) = 0x00000201;
+ *((uint *) 0x49022008) = 0x000056f3;
+ printf(" ... complete\n");
+
+ int count = 0;
+
+ for (count = 0; count < 50; count++) {
+ int bytes;
+ for (bytes = 0; bytes < sizeof(tone) / 2; bytes++) {
+ *((uint *) 0x49022008) = tone[bytes];
+ udelay(100);
+ }
+ }
+}
+
+void dss_init()
+{
+ unsigned int i;
+ unsigned char pixel[3];
+ int offset = 0;
+
+ /* assuming a resolution of 1280x720 - draw logo into dss buffer */
+
+ /* fill in the blank white bar at the top */
+ for (i = 0; i < (((720 / 2) - (beagle_height / 2)) * 1280) * 2; i +=
2) {
+ *((unsigned short *) (0x80500000 + i + offset)) = 0xffff;
+ }
+
+ offset += i;
+
+ /* Add the image data */
+ for (i = 0; i < ((beagle_width * beagle_height) * 2);) {
+ HEADER_PIXEL(header_data, pixel);
+ *((unsigned short *) (0x80500000 + i + offset)) =
+ ((((pixel[0]) & 0xf8) << 8) |
+ (((pixel[1]) & 0xfc) << 3) | (((pixel[2]) & 0xf8) >> 3));
+ i += 2;
+ }
+
+ offset += i;
+
+ /* fill in the blank white bar at the bottom */
+ for (i = 0; i < (720 - (offset / 2 / 1280)) * 1280 * 2; i += 2) {
+ *((unsigned short *) (0x80500000 + i + offset)) = 0xffff;
+ }
+
+ *((uint *) 0x48310034) = 0xfefffedf;
+ *((uint *) 0x48310094) = 0x01000120;
+ *((uint *) 0x48004D44) = 0x0001b00c;
+ *((uint *) 0x48004E40) = 0x00001006;
+ *((uint *) 0x48004D00) = 0x00370037;
+ *((uint *) 0x48050C00) = 0x00000002;
+ *((uint *) 0x48050C04) = 0x0000001B;
+ *((uint *) 0x48050C08) = 0x00000040;
+ *((uint *) 0x48050C0C) = 0x00000000;
+ *((uint *) 0x48050C10) = 0x00000000;
+ *((uint *) 0x48050C14) = 0x00008000;
+ *((uint *) 0x48050C18) = 0x00000000;
+ *((uint *) 0x48050C1C) = 0x00008359;
+ *((uint *) 0x48050C20) = 0x0000020C;
+ *((uint *) 0x48050C24) = 0x00000000;
+ *((uint *) 0x48050C28) = 0x043F2631;
+ *((uint *) 0x48050C2C) = 0x00000024;
+ *((uint *) 0x48050C30) = 0x00000130;
+ *((uint *) 0x48050C34) = 0x00000198;
+ *((uint *) 0x48050C38) = 0x000001C0;
+ *((uint *) 0x48050C3C) = 0x0000006A;
+ *((uint *) 0x48050C40) = 0x0000005C;
+ *((uint *) 0x48050C44) = 0x00000000;
+ *((uint *) 0x48050C48) = 0x00000001;
+ *((uint *) 0x48050C4C) = 0x0000003F;
+ *((uint *) 0x48050C50) = 0x21F07C1F;
+ *((uint *) 0x48050C54) = 0x00000000;
+ *((uint *) 0x48050C58) = 0x00000015;
+ *((uint *) 0x48050C5C) = 0x00001400;
+ *((uint *) 0x48050C60) = 0x00000000;
+ *((uint *) 0x48050C64) = 0x069300F4;
+ *((uint *) 0x48050C68) = 0x0016020C;
+ *((uint *) 0x48050C6C) = 0x00060107;
+ *((uint *) 0x48050C70) = 0x008D034E;
+ *((uint *) 0x48050C74) = 0x000F0359;
+ *((uint *) 0x48050C78) = 0x01A00000;
+ *((uint *) 0x48050C7C) = 0x020501A0;
+ *((uint *) 0x48050C80) = 0x01AC0024;
+ *((uint *) 0x48050C84) = 0x020D01AC;
+ *((uint *) 0x48050C88) = 0x00000006;
+ *((uint *) 0x48050C8C) = 0x00000000;
+ *((uint *) 0x48050C90) = 0x03480079;
+ *((uint *) 0x48050C94) = 0x02040024;
+ *((uint *) 0x48050C98) = 0x00000000;
+ *((uint *) 0x48050C9C) = 0x00000000;
+ *((uint *) 0x48050CA0) = 0x0001008A;
+ *((uint *) 0x48050CA4) = 0x01AC0106;
+ *((uint *) 0x48050CA8) = 0x01060006;
+ *((uint *) 0x48050CAC) = 0x00000000;
+ *((uint *) 0x48050CB0) = 0x00140001;
+ *((uint *) 0x48050CB4) = 0x00010001;
+ *((uint *) 0x48050CB8) = 0x00FF0000;
+ *((uint *) 0x48050CBC) = 0x00000000;
+ *((uint *) 0x48050CC0) = 0x00000000;
+ *((uint *) 0x48050CC4) = 0x0000000D;
+ *((uint *) 0x48050CC8) = 0x00000000;
+ *((uint *) 0x48050010) = 0x00000001;
+ *((uint *) 0x48050040) = 0x00000078;
+ *((uint *) 0x48050044) = 0x00000000;
+ *((uint *) 0x48050048) = 0x00000000;
+ *((uint *) 0x48050050) = 0x00000000;
+ *((uint *) 0x48050058) = 0x00000000;
+ *((uint *) 0x48050410) = 0x00002015;
+ *((uint *) 0x48050414) = 0x00000001;
+ *((uint *) 0x48050444) = 0x00000004;
+ *((uint *) 0x4805044c) = 0xFFFFFFFF;
+ *((uint *) 0x48050450) = 0x00000000;
+ *((uint *) 0x48050454) = 0x00000000;
+ *((uint *) 0x48050458) = 0x00000000;
+ *((uint *) 0x48050464) = 0x0ff03f31;
+ *((uint *) 0x48050468) = 0x01400504;
+ *((uint *) 0x4805046c) = 0x00007028;
+ *((uint *) 0x48050470) = 0x00010002;
+ *((uint *) 0x48050478) = 0x00ef027f;
+ *((uint *) 0x4805047c) = 0x02cf04ff;
+ *((uint *) 0x48050480) = 0x80500000;
+ *((uint *) 0x48050484) = 0x80500000;
+ *((uint *) 0x48050488) = 0x00000000;
+ *((uint *) 0x4805048c) = 0x02cf04ff;
+ *((uint *) 0x480504a0) = 0x0000008d;
+ *((uint *) 0x480504a4) = 0x03fc03bc;
+ *((uint *) 0x480504a8) = 0x00000400;
+ *((uint *) 0x480504ac) = 0x00000001;
+ *((uint *) 0x480504b0) = 0x00000001;
+ *((uint *) 0x480504b4) = 0x00000000;
+ *((uint *) 0x480504b8) = 0x807ff000;
+ udelay(1000);
+ *((uint *) 0x48050440) = 0x0001836b;
+ udelay(1000);
+ *((uint *) 0x48050440) = 0x0001836b;
+ udelay(1000);
+ *((uint *) 0x48050440) = 0x0001836b;
+ udelay(1000);
+
+}
+
+/*******************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ ********************************************************/
+int misc_init_r(void)
+{
+ unsigned char byte;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+ byte = 0x20;
+ i2c_write(0x4B, 0x7A, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x7D, 1, &byte, 1);
+ byte = 0xE0;
+ i2c_write(0x4B, 0x8E, 1, &byte, 1);
+ byte = 0x05;
+ i2c_write(0x4B, 0x91, 1, &byte, 1);
+ byte = 0x20;
+ i2c_write(0x4B, 0x96, 1, &byte, 1);
+ byte = 0x03;
+ i2c_write(0x4B, 0x99, 1, &byte, 1);
+ byte = 0x33;
+ i2c_write(0x4A, 0xEE, 1, &byte, 1);
+
+ *((uint *) 0x49058034) = 0xFFFFFAF9;
+ *((uint *) 0x49056034) = 0x0F9F0FFF;
+ *((uint *) 0x49058094) = 0x00000506;
+ *((uint *) 0x49056094) = 0xF060F000;
+
+ dss_init();
+ audio_init();
+
+ return (0);
+}
+
+/******************************************************
+ * Routine: wait_for_command_complete
+ * Description: Wait for posting to finish on watchdog
+ ******************************************************/
+void wait_for_command_complete(unsigned int wd_base)
+{
+ int pending = 1;
+ do {
+ pending = __raw_readl(wd_base + WWPS);
+ } while (pending);
+}
+
+/****************************************
+ * Routine: watchdog_init
+ * Description: Shut down watch dogs
+ *****************************************/
+void watchdog_init(void)
+{
+ /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
+ * either taken care of by ROM (HS/EMU) or not accessible (GP).
+ * We need to take care of WD2-MPU or take a PRCM reset. WD3
+ * should not be running and does not generate a PRCM reset.
+ */
+
+ sr32(CM_FCLKEN_WKUP, 5, 1, 1);
+ sr32(CM_ICLKEN_WKUP, 5, 1, 1);
+ wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
+
+ __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
+ wait_for_command_complete(WD2_BASE);
+ __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
+}
+
+/*******************************************************************
+ * Routine:ether_init
+ * Description: take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete.
+ ******************************************************************/
+void ether_init(void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+ int cnt = 20;
+
+ __raw_writew(0x0, LAN_RESET_REGISTER);
+ do {
+ __raw_writew(0x1, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto h4reset_err_out;
+ --cnt;
+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
+
+ cnt = 20;
+
+ do {
+ __raw_writew(0x0, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto h4reset_err_out;
+ --cnt;
+ } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
+ udelay(1000);
+
+ *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
+ udelay(1000);
+
+ h4reset_err_out:
+ return;
+#endif
+}
+
+/**********************************************
+ * Routine: dram_init
+ * Description: sets uboots idea of sdram size
+ **********************************************/
+int dram_init(void)
+{
+#define NOT_EARLY 0
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int size0 = 0, size1 = 0;
+ u32 mtype, btype;
+
+ btype = get_board_type();
+ mtype = get_mem_type();
+#ifndef CONFIG_3430ZEBU
+ /* fixme... dont know why this func is crashing in ZeBu */
+ display_board_info(btype);
+#endif
+ /* If a second bank of DDR is attached to CS1 this is
+ * where it can be started. Early init code will init
+ * memory on CS0.
+ */
+ if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
+ do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY);
+ }
+ size0 = get_sdr_cs_size(SDRC_CS0_OSET);
+ size1 = get_sdr_cs_size(SDRC_CS1_OSET);
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = size0;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
+ gd->bd->bi_dram[1].size = size1;
+
+ return 0;
+}
+
+#define MUX_VAL(OFFSET,VALUE)\
+ __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
+
+#define CP(x) (CONTROL_PADCONF_##x)
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that
pin
+ */
+#define MUX_DEFAULT_ES2()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
+ /* For Beagle Rev 1 boards */\
+ /*MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4))\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4))*/\
+ /* For Beagle Rev 2 boards*/\
+ MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1))\
+ MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1))\
+ MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))\
+ /* till here */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /
*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /
*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS ), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS ), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98 -
CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0 ), (IEN | PTD | DIS | M0)) /*CAM_D0 */\
+ MUX_VAL(CP(CAM_D1 ), (IEN | PTD | DIS | M0)) /*CAM_D1 */\
+ MUX_VAL(CP(CAM_D2 ), (IEN | PTD | DIS | M0)) /*CAM_D2 */\
+ MUX_VAL(CP(CAM_D3 ), (IEN | PTD | DIS | M0)) /*CAM_D3 */\
+ MUX_VAL(CP(CAM_D4 ), (IEN | PTD | DIS | M0)) /*CAM_D4 */\
+ MUX_VAL(CP(CAM_D5 ), (IEN | PTD | DIS | M0)) /*CAM_D5 */\
+ MUX_VAL(CP(CAM_D6 ), (IEN | PTD | DIS | M0)) /*CAM_D6 */\
+ MUX_VAL(CP(CAM_D7 ), (IEN | PTD | DIS | M0)) /*CAM_D7 */\
+ MUX_VAL(CP(CAM_D8 ), (IEN | PTD | DIS | M0)) /*CAM_D8 */\
+ MUX_VAL(CP(CAM_D9 ), (IEN | PTD | DIS | M0)) /*CAM_D9 */\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(McBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(McBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/
\
+ MUX_VAL(CP(McBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(McBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
+ MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
+ MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
+ MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(McBSP3_DX), (IDIS | PTD | DIS | M4)) /*GPIO_140*/\
+ MUX_VAL(CP(McBSP3_DR), (IDIS | PTD | DIS | M4)) /*GPIO_142*/\
+ MUX_VAL(CP(McBSP3_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_141*/\
+ MUX_VAL(CP(McBSP3_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_143*/\
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /
*GPIO_149*/\
+ MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /
*GPIO_150*/\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(McBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX
*/\
+ MUX_VAL(CP(McBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX
*/\
+ MUX_VAL(CP(McBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX
*/\
+ MUX_VAL(CP(McBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
+ MUX_VAL(CP(McBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(McBSP1_FSR), (IDIS | PTU | EN | M4)) /*GPIO_157 -
BT_WAKEUP*/\
+ MUX_VAL(CP(McBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158*/\
+ MUX_VAL(CP(McBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(McBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS */
\
+ MUX_VAL(CP(McBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(McBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162 */\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /
*UART3_CTS_RCTX */\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD
*/\
+ MUX_VAL(CP(UART3_RX_IRRX ), (IEN | PTD | DIS | M0)) /
*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX ), (IDIS | PTD | DIS | M0)) /
*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0
*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1
*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2
*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3
*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4
*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5
*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6
*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7
*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IDIS | PTU | DIS | M4)) /*GPIO_168*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
+ MUX_VAL(CP(McSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(McSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO
*/\
+ MUX_VAL(CP(McSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI
*/\
+ MUX_VAL(CP(McSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(McSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
+ MUX_VAL(CP(McSPI1_CS2), (IDIS | PTD | DIS | M4)) /*GPIO_176 -
NOR_DPD*/\
+ MUX_VAL(CP(McSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
+ MUX_VAL(CP(McSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(McSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/
\
+ MUX_VAL(CP(McSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/
\
+ MUX_VAL(CP(McSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(McSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_nIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 -
PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 -
MMC1_WP */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 -
LCD_ENVDD*/\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 -
LAN_INTR0*/\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 -
MMC2_WP*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8 -
LCD_ENBKL*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE
*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1
*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA0*/
\
+ MUX_VAL(CP(ETK_D1_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA1*/
\
+ MUX_VAL(CP(ETK_D2_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA2*/
\
+ MUX_VAL(CP(ETK_D3_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA7*/
\
+ MUX_VAL(CP(ETK_D4_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA4*/
\
+ MUX_VAL(CP(ETK_D5_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA5*/
\
+ MUX_VAL(CP(ETK_D6_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA6*/
\
+ MUX_VAL(CP(ETK_D7_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DATA3*/
\
+ MUX_VAL(CP(ETK_D8_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2 ), (IEN | PTD | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D15), (IEN | PTU | EN | M4)) /*GPIO_29*/\
+ MUX_VAL(CP(d2d_mcad1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(d2d_mcad2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(d2d_mcad3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(d2d_mcad4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(d2d_mcad5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(d2d_mcad6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(d2d_mcad7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(d2d_mcad8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(d2d_mcad9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(d2d_mcad10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(d2d_mcad11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(d2d_mcad12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(d2d_mcad13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(d2d_mcad14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(d2d_mcad15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(d2d_mcad16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(d2d_mcad17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(d2d_mcad18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(d2d_mcad19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(d2d_mcad20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(d2d_mcad21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(d2d_mcad22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(d2d_mcad23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(d2d_mcad24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(d2d_mcad25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(d2d_mcad26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(d2d_mcad27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(d2d_mcad28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(d2d_mcad29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(d2d_mcad30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(d2d_mcad31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(d2d_mcad32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(d2d_mcad33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(d2d_mcad34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(d2d_mcad35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(d2d_mcad36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(d2d_clk26mi), (IEN | PTD | DIS | M0)) /*d2d_clk26mi
*/\
+ MUX_VAL(CP(d2d_nrespwron ), (IEN | PTD | EN | M0)) /
*d2d_nrespwron*/\
+ MUX_VAL(CP(d2d_nreswarm), (IEN | PTU | EN | M0)) /*d2d_nreswarm
*/\
+ MUX_VAL(CP(d2d_arm9nirq), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq
*/\
+ MUX_VAL(CP(d2d_uma2p6fiq ), (IEN | PTD | DIS | M0)) /
*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(d2d_spint), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(d2d_frint), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(d2d_dmareq0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0
*/\
+ MUX_VAL(CP(d2d_dmareq1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1
*/\
+ MUX_VAL(CP(d2d_dmareq2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2
*/\
+ MUX_VAL(CP(d2d_dmareq3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3
*/\
+ MUX_VAL(CP(d2d_n3gtrst), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst
*/\
+ MUX_VAL(CP(d2d_n3gtdi), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(d2d_n3gtdo), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(d2d_n3gtms), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(d2d_n3gtck), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(d2d_n3grtck), (IEN | PTD | DIS | M0)) /*d2d_n3grtck
*/\
+ MUX_VAL(CP(d2d_mstdby), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(d2d_swakeup), (IEN | PTD | EN | M0)) /*d2d_swakeup
*/\
+ MUX_VAL(CP(d2d_idlereq), (IEN | PTD | DIS | M0)) /*d2d_idlereq
*/\
+ MUX_VAL(CP(d2d_idleack), (IEN | PTU | EN | M0)) /*d2d_idleack
*/\
+ MUX_VAL(CP(d2d_mwrite), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(d2d_swrite), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(d2d_mread), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(d2d_sread), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(d2d_mbusflag), (IEN | PTD | DIS | M0)) /*d2d_mbusflag
*/\
+ MUX_VAL(CP(d2d_sbusflag), (IEN | PTD | DIS | M0)) /*d2d_sbusflag
*/\
+ MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
+ MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not
used */
+
+/**********************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need
+ * to be moved from protect to primary mode.
+ *********************************************************/
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT_ES2();
+}
+
+/
******************************************************************************
+ * Routine: update_mux()
+ * Description:Update balls which are different between boards. All
should be
+ * updated to match functionality. However, I'm only
updating ones
+ * which I'll be using for now. When power comes into
play they
+ * all need updating.
+
*****************************************************************************/
+void update_mux(u32 btype, u32 mtype)
+{
+ /* NOTHING as of now... */
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+/**********************************************************
+ * Routine: nand+_init
+ * Description: Set up nand for nand and jffs2 commands
+ *********************************************************/
+void nand_init(void)
+{
+ extern flash_info_t flash_info[];
+
+ nand_probe(CFG_NAND_ADDR);
+ if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
+ print_size(nand_dev_desc[0].totlen, "\n");
+ }
+#ifdef CFG_JFFS2_MEM_NAND
+ flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
+ /* only read kernel single meg partition */
+ flash_info[CFG_JFFS2_FIRST_BANK].size = 1024 * 1024 * 2;
+ /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
+ flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;
+ /* ?, ram for now, open question, copy to RAM or adapt for NAND */
+ flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000;
+#endif
+}
+#endif
diff -purN orig_u-boot/board/omap3530beagle/sys_info.c u-boot_beagle/
board/omap3530beagle/sys_info.c
--- orig_u-boot/board/omap3530beagle/sys_info.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/sys_info.c 2008-04-02
16:44:56.000000000 +0530
@@ -0,0 +1,331 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h> /* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+#include <i2c.h>
+
+/
**************************************************************************
+ * get_cpu_type() - Read the FPGA Debug registers and provide the DIP
switch
+ * settings
+ * 1 is on
+ * 0 is off
+ * Will return Index of type of gpmc
+
***************************************************************************/
+u32 get_gpmc0_type(void)
+{
+ // Default OneNAND
+ return (1);
+}
+
+/****************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ ****************************************************/
+u32 get_cpu_type(void)
+{
+ // fixme, need to get register defines for OMAP3
+ return (CPU_3430);
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+ u32 cpuid = 0;
+ /* On ES1.0 the IDCODE register is not exposed on L4
+ * so using CPU ID to differentiate
+ * between ES2.0 and ES1.0.
+ */
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+ if ((cpuid & 0xf) == 0x0)
+ return CPU_3430_ES1;
+ else
+ return CPU_3430_ES2;
+
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+ volatile u32 *burst = (volatile u32 *) (SDRC_MR_0 + SDRC_CS0_OSET);
+ if (*burst == SDP_SDRC_MR_0_SDR)
+ return (1);
+ return (0);
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ ***********************************************************/
+u32 get_mem_type(void)
+{
+ /* Current SDP3430 uses 2x16 MDDR Infenion parts */
+ return (DDR_DISCRETE);
+}
+
+/
***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+
************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+ u32 size;
+
+ /* get ram size field */
+ size = __raw_readl(SDRC_MCFG_0 + offset) >> 8;
+ size &= 0x3FF; /* remove unwanted bits */
+ size *= SZ_2M; /* find size in MB */
+ return (size);
+}
+
+/
***********************************************************************
+ * get_board_type() - get board type based on current production
stats.
+ * - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper
info.
+ * when they are available we can get info from there. This
should
+ * be correct of all known boards up until today.
+ * - NOTE-2- EEPROMs are populated but they are updated very
slowly. To
+ * avoid waiting on them we will use ES version of the chip to get
info.
+ * A later version of the FPGA migth solve their speed issue.
+
************************************************************************/
+u32 get_board_type(void)
+{
+ if (get_cpu_rev() == CPU_3430_ES2)
+ return SDP_3430_V2;
+ else
+ return SDP_3430_V1;
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+ return (0x0000003F & __raw_readl(CONTROL_STATUS));
+}
+
+/
***************************************************************************
+ * get_gpmc0_base() - Return current address hardware will be
+ * fetching from. The below effectively gives what is correct,
its a bit
+ * mis-leading compared to the TRM. For the most general case the
mask
+ * needs to be also taken into account this does work in practice.
+ * - for u-boot we currently map:
+ * -- 0 to nothing,
+ * -- 4 to flash
+ * -- 8 to enent
+ * -- c to wifi
+
****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+ u32 b;
+
+ b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7);
+ b &= 0x1F; /* keep base [5:0] */
+ b = b << 24; /* ret 0x0b000000 */
+ return (b);
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+ return (WIDTH_16BIT);
+}
+
+/
*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+
*************************************************************************/
+u32 get_board_rev(void)
+{
+ return (0x20);
+}
+
+/
*********************************************************************
+ * display_board_info() - print banner with board info.
+
*********************************************************************/
+void display_board_info(u32 btype)
+{
+ char *bootmode[] = {
+ "NOR",
+ "ONND",
+ "NAND",
+ "P2a",
+ "NOR",
+ "NOR",
+ "P2a",
+ "P2b",
+ };
+ u32 brev = get_board_rev();
+ char cpu_3430s[] = "3430";
+ char db_ver[] = "0.0"; /* board type */
+ char mem_sdr[] = "mSDR"; /* memory type */
+ char mem_ddr[] = "mDDR";
+ char t_tst[] = "TST"; /* security level */
+ char t_emu[] = "EMU";
+ char t_hs[] = "HS";
+ char t_gp[] = "GP";
+ char unk[] = "?";
+#ifdef CONFIG_LED_INFO
+ char led_string[CONFIG_LED_LEN] = { 0 };
+#endif
+
+#if defined(L3_165MHZ)
+ char p_l3[] = "165";
+#elif defined(L3_110MHZ)
+ char p_l3[] = "110";
+#elif defined(L3_133MHZ)
+ char p_l3[] = "133";
+#elif defined(L3_100MHZ)
+ char p_l3[] = "100"
+#endif
+#if defined(PRCM_PCLK_OPP1)
+ char p_cpu[] = "1";
+#elif defined(PRCM_PCLK_OPP2)
+ char p_cpu[] = "2";
+#elif defined(PRCM_PCLK_OPP3)
+ char p_cpu[] = "3";
+#elif defined(PRCM_PCLK_OPP4)
+ char p_cpu[] = "4"
+#endif
+ char *cpu_s, *db_s, *mem_s, *sec_s;
+ u32 cpu, rev, sec;
+
+ rev = get_cpu_rev();
+ cpu = get_cpu_type();
+ sec = get_device_type();
+
+ if (is_mem_sdr())
+ mem_s = mem_sdr;
+ else
+ mem_s = mem_ddr;
+
+ cpu_s = cpu_3430s;
+
+ db_s = db_ver;
+ db_s[0] += (brev >> 4) & 0xF;
+ db_s[2] += brev & 0xF;
+
+ switch (sec) {
+ case TST_DEVICE:
+ sec_s = t_tst;
+ break;
+ case EMU_DEVICE:
+ sec_s = t_emu;
+ break;
+ case HS_DEVICE:
+ sec_s = t_hs;
+ break;
+ case GP_DEVICE:
+ sec_s = t_gp;
+ break;
+ default:
+ sec_s = unk;
+ }
+
+ printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", cpu_s, sec_s, rev,
+ p_cpu, p_l3);
+ printf("OMAP3 Beagle Board %s Version + %s (Boot %s)\n", db_s,
+ mem_s, bootmode[get_gpmc0_type()]);
+
+}
+
+/********************************************************
+ * get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+ u32 val;
+
+ __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+ val &= 0xF0000000;
+ val >>= 28;
+ return (val);
+}
+
+/********************************************************
+ * running_in_flash() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_flash(void)
+{
+ if (get_base() < 4)
+ return (1); /* in flash */
+
+ return (0); /* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ * running_in_sram() - tell if currently running in
+ * sram.
+ *******************************************************/
+u32 running_in_sram(void)
+{
+ if (get_base() == 4)
+ return (1); /* in SRAM */
+
+ return (0); /* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ * running_in_sdram() - tell if currently running in
+ * flash.
+ *******************************************************/
+u32 running_in_sdram(void)
+{
+ if (get_base() > 4)
+ return (1); /* in sdram */
+
+ return (0); /* running in SRAM or FLASH */
+}
+
+/***************************************************************
+ * get_boot_type() - Is this an XIP type device or a stream one
+ * bits 4-0 specify type. Bit 5 sys mem/perif
+ ***************************************************************/
+u32 get_boot_type(void)
+{
+ u32 v;
+
+ v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+ return v;
+}
+
+/*************************************************************
+ * get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+ int mode;
+
+ mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
+ return (mode >>= 8);
+}
diff -purN orig_u-boot/board/omap3530beagle/syslib.c u-boot_beagle/
board/omap3530beagle/syslib.c
--- orig_u-boot/board/omap3530beagle/syslib.c 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/syslib.c 2008-04-02
16:45:47.000000000 +0530
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Richard Woodruff <r-woo...@ti.com>
+ * Syed Mohammed Khasim <kha...@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = __raw_readl(addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ __raw_writel(tmp, addr);
+}
+
+/
*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+
*********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr,
u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = __raw_readl(read_addr) & read_bit_mask;
+ if (val == match_value)
+ return (1);
+ if (i == bound)
+ return (0);
+ } while (1);
+}
diff -purN orig_u-boot/board/omap3530beagle/u-boot.lds u-boot_beagle/
board/omap3530beagle/u-boot.lds
--- orig_u-boot/board/omap3530beagle/u-boot.lds 1970-01-01
05:30:00.000000000 +0530
+++ u-boot_beagle/board/omap3530beagle/u-boot.lds 2008-04-02
11:05:56.000000000 +0530
@@ -0,0 +1,63 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <g...@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-
littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/omap3/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+ __exidx_start = .;
+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+ __exidx_end = .;
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
Jason Kridner
Apr 2, 2008, 9:45:19 PM4/2/08
to beagl...@googlegroups.com
Sunil,
I'd remove the logo when submitting to denx.de, or at least make it
separate. I don't know what the reaction is likely to be, but it
dominates the patch and that doesn't seem like a nice way to win
initial favor. Do we know if other board support includes custom logos?
The logo seems to be 1280 wide. I think we need to figure out how to
support variable display resolutions. The logo could be smaller.
I'll have to try it later because I'm curious what it looks like. :)
You seem to be using tabs. Is that the norm for the list?
I noticed you misspelled "Begale Board". It should be spelled "Beagle
Board".
I believe the audio tone used to test the boards can be provided as a
separate patch. That wouldn't be normal to have in a production u-boot.
For sysinfo.c, I'd be inclined to put OMAP3530, rather than OMAP3430,
but that isn't significant. Since it is a banner, I could imagine it
confusing someone.
Regards,
Jason
On Apr 2, 2008, at 8:24 AM, sunil wrote:
>
>
> This patch adds board directory for BeagleBoard.
>
> Signed-off-by:
> Sunil Kumar <sunils...@gmail.com>
> Shashi Ranjan <shashira...@gmail.com>
> Syed Mohammed Khasim <kha...@ti.com>
> ---
> Makefile | 47
> beagle_logo_FNL_2.h | 8815 +++++++++++++++++++++++++++++++++++++++++++
> +++++++++
> clock.c | 350 ++
> config.mk | 17
> lowlevel_init.S | 361 ++
> mem.c | 263 +
> nand.c | 455 ++
> omap3530beagle.c | 1142 ++++++
> sys_info.c | 331 +
> syslib.c | 74
> u-boot.lds | 63
> 11 files changed, 11918 insertions(+)
>
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