Enable L2 cache in git

[Philip]

Now that I am running at 500 MHz, I've been looking at enabling L2
cache. Is it as simple as adding this code:

#if defined(CONFIG_ARCH_OMAP3)
@ L2 cache is enabled in the aux control register
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #0x11 @ speculative+no-alais
protection
#ifdef CONFIG_CPU_L2CACHE_DISABLE
bic r0, r0, #0x2 @ disable L2 Cache.
#else
orr r0, r0, #0x2 @ enaable L2 Cache.
#endif

to arch/arm/mm/proc-v7.S, and adding the CONFIG_CPU_L2CACHE_DISABLE
config option?

If so, I'll work on a patch.

Philip

[Syed Mohammed, Khasim]

I don't know how this is not available on OMAP GIT yet, long time back we had merged Catalin's (ARM) tree with OMAP GIT.

 

Anyways, if you are using u-boot 1.1.4 from code.google.com, then it has ICACHE and L2CACHE already enabled. You might not need this in kernel, but for furture we might have to add this piece of code and it has to be discussed on ARM kernel mailing list.

 

Regards

Khasim

[Dirk Behme]

Syed Mohammed, Khasim wrote:
>
>
> On 4/29/08, *Philip* <philip....@gmail.com

> <mailto:philip....@gmail.com>> wrote:
>
>
> Now that I am running at 500 MHz, I've been looking at enabling L2
> cache. Is it as simple as adding this code:
>
> #if defined(CONFIG_ARCH_OMAP3)
> @ L2 cache is enabled in the aux control register
> mrc p15, 0, r0, c1, c0, 1
> orr r0, r0, #0x11 @ speculative+no-alais
> protection
> #ifdef CONFIG_CPU_L2CACHE_DISABLE
> bic r0, r0, #0x2 @ disable L2 Cache.
> #else
> orr r0, r0, #0x2 @ enaable L2 Cache.
> #endif
>
> to arch/arm/mm/proc-v7.S, and adding the CONFIG_CPU_L2CACHE_DISABLE
> config option?
>
> If so, I'll work on a patch.
>
>
> I don't know how this is not available on OMAP GIT yet, long time back
> we had merged Catalin's (ARM) tree with OMAP GIT.
>
> Anyways, if you are using u-boot 1.1.4 from code.google.com

> <http://code.google.com>, then it has ICACHE and L2CACHE already
> enabled.

Uumph :(

The long story:

Yesterday, on IRC we discussed about L2 cache

http://www.beagleboard.org/irclogs/index.php?date=2008-05-03#T18:01:43

and came to the conclusion that L2 cache is *not* enabled by uboot
because reading from kernel

p15, 0, Rd, c1, c0, 1: 0x00000050

Now, I had a look to U-Boot 1.1.4 from

http://code.google.com/p/beagleboard/wiki/BeagleSourceCode

, applied Khasim's u-boot_500mpu_166ddr.patch patch and added some
debug output.

Result:

-- cut --
U-Boot 1.1.4 (May 4 2008 - 09:58:48)

OMAP3430-GP rev 2, CPU-OPP2 L3-133MHz
TI 3430Beagle 2.0 Version + mDDR (Boot ONND)
DRAM: 128 MB
Flash: 0 kB
NAND:256 MiB
In: serial
Out: serial
Err: serial
Audio Tone on Speakers ... complete
--> p15, 0, Rd, c0, c0, 0: 0x411fc082
--> p15, 0, Rd, c1, c0, 0: 0x00c5187a
--> p15, 0, Rd, c1, c0, 1: 0x00000052
OMAP3 beagleboard.org #
-- cut --

So in uboot L2 *is* enabled. But if we look into c1, c0, 1 register in
kernel again, it is *disabled*. :(

Any idea? Had a short look to kernel but couldn't find any place in
kernel where is is disabled again.

Full boot output below [1], see the different "p15, 0, Rd, c1, c0, 1"
outputs from uboot and kernel.

> You might not need this in kernel, but for furture we might
> have to add this piece of code and it has to be discussed on ARM kernel
> mailing list.

Sounds like we will add L2 enable to uboot and don't touch kernel.

Dirk

[1] Complete boot output:

...40T......PH.H.U�..Instruments X-Loader 1.41
Starting on with MMC
Reading boot sector

714748 Bytes Read from MMC
Starting OS Bootloader from MMC...

U-Boot 1.1.4 (May 4 2008 - 09:58:48)

OMAP3430-GP rev 2, CPU-OPP2 L3-133MHz
TI 3430Beagle 2.0 Version + mDDR (Boot ONND)
DRAM: 128 MB
Flash: 0 kB
NAND:256 MiB
In: serial
Out: serial
Err: serial
Audio Tone on Speakers ... complete
--> p15, 0, Rd, c0, c0, 0: 0x411fc082
--> p15, 0, Rd, c1, c0, 0: 0x00c5187a
--> p15, 0, Rd, c1, c0, 1: 0x00000052
OMAP3 beagleboard.org # run linux

2713700 bytes read
## Booting image at 80000000 ...
Image Name: Linux-2.6.25-omap1-09100-g547ba9
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 2713636 Bytes = 2.6 MB
Load Address: 80008000
Entry Point: 80008000
Verifying Checksum ... OK
OK

Starting kernel ...

Uncompressing
Linux.........................................................................................................
<5>Linux version 2.6.25-omap1-09100-g547ba92-dirty (dirk@foo) (gcc
version 4.2.3 (Sourcery G++ Lite 2008q1-126)) #11 8
CPU: ARMv7 Processor [411fc082] revision 2 (ARMv7), cr=00c5387f
Machine: OMAP3 Beagle Board
Memory policy: ECC disabled, Data cache writeback
<7>On node 0 totalpages: 32768
<7> DMA zone: 256 pages used for memmap
<7> DMA zone: 0 pages reserved
<7> DMA zone: 32512 pages, LIFO batch:7
<7> Normal zone: 0 pages used for memmap
<7> Movable zone: 0 pages used for memmap
<6>OMAP3430 ES2.0
<6>SRAM: Mapped pa 0x40200000 to va 0xd7000000 size: 0x100000
CPU0: D VIPT write-through cache
CPU0: cache: 768 bytes, associativity 1, 8 byte lines, 64 sets
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
<5>Kernel command line: console=ttyS2,115200n8=noinitrd
root=/dev/mmcblk0p1 rootdelay=1 rootfstype=ext2 rw ip=off devfs=mout
<6>Clocking rate (Crystal/DPLL/ARM core): 26.0/332/500 MHz
<6>GPMC revision 5.0
<6>IRQ: Found an INTC at 0xd8200000 (revision 4.0) with 96 interrupts
<6>Total of 96 interrupts on 1 active controller
<6>OMAP34xx GPIO hardware version 2.5
PID hash table entries: 512 (order: 9, 2048 bytes)
Console: colour dummy device 80x30
<6>Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
<6>Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
<6>Memory: 128MB 0MB = 128MB total
<5>Memory: 125696KB available (2544K code, 219K data, 1408K init)
<7>Calibrating delay loop... 498.87 BogoMIPS (lpj=1945600)
Mount-cache hash table entries: 512
<6>CPU: Testing write buffer coherency: ok
<6>net_namespace: 192 bytes
<6>NET: Registered protocol family 16
--> p15, 0, Rd, c0, c0, 0: 0x411fc082
--> p15, 0, Rd, c1, c0, 0: 0x00c5387f
--> p15, 0, Rd, c1, c0, 1: 0x00000050
<6>OMAP DMA hardware revision 4.0
<3>USB: No board-specific platform config found
<5>SCSI subsystem initialized
<6>NET: Registered protocol family 2
<7>Switched to high resolution mode on CPU 0
<6>IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
<6>TCP established hash table entries: 4096 (order: 3, 32768 bytes)
<6>TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
<6>TCP: Hash tables configured (established 4096 bind 4096)
<6>TCP reno registered
...

[Dirk Behme]

Okay, found it. It is done in u-boot:

-- cut --
cpu/omap3/cpu.c:

int cleanup_before_linux (void)
{
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts ();

#ifdef CONFIG_LCD
{
extern void lcd_disable(void);
extern void lcd_panel_disable(void);

lcd_disable(); /* proper disable of lcd & panel */
lcd_panel_disable();
}
#endif

{
unsigned int i;

/* turn off I/D-cache */
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~(C1_DC | C1_IC);
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));

/* invalidate I-cache */
arm_cache_flush();
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2cache_disable();
/* invalidate L2 cache also */
v7_flush_dcache_all(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i));
}
-- cut --

So, conclusion is, we *can't* rely on uboot. L2 cache *is* enabled in
uboot, but *disabled* again before kernel start.

Two options then:

- If we are really sure that we don't need to disable L2 cache before
kernel starts, then we can re-enable L2 cache in U-Boot above.

or

- We have to re-add something like

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=7092fc38ee770251aed361572bf6bed05fcf3ee2

in kernel.

Opinions?

Dirk