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Description:
Open Discussion on the Advanced Verification Methodology published by Mentor Graphics Corporation
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AVM User Group is closed.
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Due to disuse, this mailing list is now closed. Please go to the OVM
forum at [link].
Thank you all who have contributed to this mailing list.
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Create a mini-VIP in SystemVerilog/VMM in 2 weeks
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Hi,
Create a mini-VIP in SystemVerilog/VMM in 2 weeks
…a project driven incubation for Verification engineers
CVC ([link]) is announcing a 2-weeks intensive incubation on
SystemVerilog-VMM VIP creation challenge. This is primarily targeted
for recently displaced workers in ASIC domain looking to hone their... more »
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2-days course on “Do-it Right – Basic VMM”
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Hi,
2-days course on “Do-it Right – Basic VMM”
…SystemVerilog framework for creating effective Verification
Environment
CVC ([link]) is announcing a new session of its 2-days course
on “Do-it Right – Basic VMM” - a step-by-step guide to building
scalable, reusable and flexible Verification Environment using VMM.... more »
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1-day course on “Do-it Right – Advanced VMM”
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Hi,
1-day course on “Do-it Right – Advanced VMM”
…SystemVerilog framework for creating effective Verification
Environment
CVC ([link]) is announcing a new session of its 1-day course
on “Do-it Right – Advanced VMM” including new base classes and RAL.
Duration
Topic Duration... more »
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Create a mini-VIP in SystemVerilog/VMM in 2 weeks
|
| |
Hi,
Create a mini-VIP in SystemVerilog/VMM in 2 weeks
…a project driven incubation for Verification engineers
CVC ([link]) is announcing a 2-weeks intensive incubation on
SystemVerilog-VMM VIP creation challenge. This is primarily targeted
for recently displaced workers in ASIC domain looking to hone their... more »
|
|
|
2-day course on “Do-it Right – VMM
|
| |
Hi,
2-day course on “Do-it Right – VMM”
…SystemVerilog framework for creating effective Verification
Environment
CVC ([link]) is announcing a new session of its 2-day course
on “Do-it Right – VMM” - a step-by-step guide to building scalable,
reusable and flexible Verification Environment using VMM.... more »
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UCDB XML support in candence ?
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Dear ALL,
I'm new in this group and not really a verification expert.
I need same basic help on UCDB API and XML.
I found an API decription to access UCDB. But there is nothing like
"save XML". I found also a schema file which is describing the
namespace of the UCDB well in my understanding.... more »
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Verification on Wheels (VoW) series – SystemVerilog in action
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Quick facts:
• When: June 1st 2009, 4PM to 6PM
• Where: Board Room, Mentor Graphics, Hyderabad
• Agenda: 1 hour: SystemVerilog language tutorial. 45 min: Case
study, 15 min: Q&A
• Who: Srinivasan Venkataramanan, Chief Technology Officer, CVC Pvt.
Ltd.
• Cost: No cost, but limited space, first-come-first-serve... more »
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