Duplicate Traces

[Deepak]

When I enable -Xjitverbose, I see that traces along with the assembly
generated gets printed. To my surprise I also see that same traces are
compiled by the JIT compiler and a duplicate code copy is installed in
code cache at multiple locations.

My question is does/does not the JIT compiler check if a particular
trace is compiled before compiling it ? If it does check, why do I see
duplicate codes in the verbose mode ? And also where does it check ?

Thanks
Deepak

[Ben Cheng]

The check is at the beginning of the dvmCompileTrace() function in dalvik/vm/compiler/Frontend.c:

    /* If we've already compiled this trace, just return success */

    if (dvmJitGetCodeAddr(startCodePtr) && !info->discardResult) {

        return true;

    }

Could you attach the trace dump from the log so that we can take a look? Please also note that the same trace may be compiled multiple times in different apps (ie processes), and you can tell if it's the case from the pid field in the log.

-Ben

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[Deepak]

Below is the Java program and the corresponding dump when I enable
Xjitverbose. The traces that get recompiled are not always the same.

class somethingjit {
public static void main(String[] args)
{
int i;
for(i=0;i<100;i++)
{
f(i);
}
}

static void f(int var)
{
int i=0,j=0;
for(i=0;i<1000;i++)
{
if(var%2 == 0)
j++;
else
j++;
}
}

}

****************************************************************

Dumping LIR insns
installed code is at 0x42aa7708
total size is 48 bytes
0x42aa7708 (0000): data 0x001c(28)
-------- entry offset: 0x0002
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa770a (0002): ldr r0, [pc, #40]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa770c (0004): ldr r1, [r5, #4]
0x42aa770e (0006): cmp r1, r0
0x42aa7710 (0008): str r0, [r5, #8]
0x42aa7712 (000a): bge 0x42aa771c
Exception_Handling:
0x42aa7714 (000c): .align4
-------- chaining cell (normal): 0x0006
0x42aa7714 (000c): ldr r0, [r6, #84]
0x42aa7716 (000e): blx r0
0x42aa7718 (0010): data 0x8170(33136)
0x42aa771a (0012): data 0x42b2(17074)
0x42aa771c (0014): .align4
-------- chaining cell (normal): 0x0012
0x42aa771c (0014): ldr r0, [r6, #84]
0x42aa771e (0016): blx r0
0x42aa7720 (0018): data 0x8188(33160)
0x42aa7722 (001a): data 0x42b2(17074)
-------- end of chaining cells (0x001c)
0x42aa7734 (002c): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa7738
total size is 64 bytes
0x42aa7738 (0000): data 0x0028(40)
-------- entry offset: 0x000a
L0x000a:
-------- dalvik offset: 0x000a @ add-int/lit8 v0, v0, (#1)
0x42aa773a (0002): ldr r0, [r5, #0]
0x42aa773c (0004): ldr r1, [r5, #4]
0x42aa773e (0006): adds r0, r0, #1
-------- dalvik offset: 0x000c @ add-int/lit8 v1, v1, (#1)
0x42aa7740 (0008): adds r1, r1, #1
-------- dalvik offset: 0x000e @ goto, (#0), (#0)
0x42aa7742 (000a): str r0, [r5, #0]
0x42aa7744 (000c): str r1, [r5, #4]
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa7746 (000e): ldr r2, [pc, #44]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa7748 (0010): ldr r3, [r5, #4]
0x42aa774a (0012): cmp r3, r2
0x42aa774c (0014): str r2, [r5, #8]
0x42aa774e (0016): bge 0x42aa7758
Exception_Handling:
0x42aa7750 (0018): .align4
-------- chaining cell (normal): 0x0006
0x42aa7750 (0018): ldr r0, [r6, #84]
0x42aa7752 (001a): blx r0
0x42aa7754 (001c): data 0x8170(33136)
0x42aa7756 (001e): data 0x42b2(17074)
0x42aa7758 (0020): .align4
-------- chaining cell (normal): 0x0012
0x42aa7758 (0020): ldr r0, [r6, #84]
0x42aa775a (0022): blx r0
0x42aa775c (0024): data 0x8188(33160)
0x42aa775e (0026): data 0x42b2(17074)
-------- end of chaining cells (0x0028)
0x42aa7774 (003c): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa7778
total size is 52 bytes
0x42aa7778 (0000): data 0x0020(32)
-------- entry offset: 0x0006
L0x0006:
-------- dalvik offset: 0x0006 @ rem-int/lit8 v2, v3, (#2)
0x42aa777a (0002): ldr r2, [pc, #44]
0x42aa777c (0004): ldr r0, [r5, #12]
0x42aa777e (0006): movs r1, #2
0x42aa7780 (0008): blx r2
-------- dalvik offset: 0x0008 @ if-nez v2, (#7), (#0)
0x42aa7782 (000a): cmp r1, #0
0x42aa7784 (000c): str r1, [r5, #8]
0x42aa7786 (000e): bne 0x42aa7790
Exception_Handling:
0x42aa7788 (0010): .align4
-------- chaining cell (normal): 0x000a
0x42aa7788 (0010): ldr r0, [r6, #84]
0x42aa778a (0012): blx r0
0x42aa778c (0014): data 0x8178(33144)
0x42aa778e (0016): data 0x42b2(17074)
0x42aa7790 (0018): .align4
-------- chaining cell (normal): 0x000f
0x42aa7790 (0018): ldr r0, [r6, #84]
0x42aa7792 (001a): blx r0
0x42aa7794 (001c): data 0x8182(33154)
0x42aa7796 (001e): data 0x42b2(17074)
-------- end of chaining cells (0x0020)
0x42aa77a8 (0030): .word (0xafd33294)
Dumping LIR insns
installed code is at 0x42aa77ac
total size is 60 bytes
0x42aa77ac (0000): data 0x0024(36)
-------- entry offset: 0x000c
L0x000c:
-------- dalvik offset: 0x000c @ add-int/lit8 v1, v1, (#1)
0x42aa77ae (0002): ldr r0, [r5, #4]
0x42aa77b0 (0004): adds r0, r0, #1
0x42aa77b2 (0006): str r0, [r5, #4]
-------- dalvik offset: 0x000e @ goto, (#0), (#0)
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa77b4 (0008): ldr r1, [pc, #44]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa77b6 (000a): ldr r2, [r5, #4]
0x42aa77b8 (000c): cmp r2, r1
0x42aa77ba (000e): str r1, [r5, #8]
0x42aa77bc (0010): bge 0x42aa77c8
Exception_Handling:
0x42aa77be (0012): .align4
-------- chaining cell (normal): 0x0006
0x42aa77c0 (0014): ldr r0, [r6, #84]
0x42aa77c2 (0016): blx r0
0x42aa77c4 (0018): data 0x8170(33136)
0x42aa77c6 (001a): data 0x42b2(17074)
0x42aa77c8 (001c): .align4
-------- chaining cell (normal): 0x0012
0x42aa77c8 (001c): ldr r0, [r6, #84]
0x42aa77ca (001e): blx r0
0x42aa77cc (0020): data 0x8188(33160)
0x42aa77ce (0022): data 0x42b2(17074)
-------- end of chaining cells (0x0024)
0x42aa77e4 (0038): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa77e8
total size is 68 bytes
0x42aa77e8 (0000): data 0x0028(40)
-------- entry offset: 0x000f
L0x000f:
-------- dalvik offset: 0x000f @ add-int/lit8 v0, v0, (#1)
0x42aa77ea (0002): ldr r0, [r5, #0]
0x42aa77ec (0004): adds r0, r0, #1
0x42aa77ee (0006): str r0, [r5, #0]
-------- dalvik offset: 0x0011 @ goto, (#0), (#0)
L0x000c:
-------- dalvik offset: 0x000c @ add-int/lit8 v1, v1, (#1)
0x42aa77f0 (0008): ldr r1, [r5, #4]
0x42aa77f2 (000a): adds r1, r1, #1
0x42aa77f4 (000c): str r1, [r5, #4]
-------- dalvik offset: 0x000e @ goto, (#0), (#0)
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa77f6 (000e): ldr r2, [pc, #48]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa77f8 (0010): ldr r3, [r5, #4]
0x42aa77fa (0012): cmp r3, r2
0x42aa77fc (0014): str r2, [r5, #8]
0x42aa77fe (0016): bge 0x42aa7808
Exception_Handling:
0x42aa7800 (0018): .align4
-------- chaining cell (normal): 0x0006
0x42aa7800 (0018): ldr r0, [r6, #84]
0x42aa7802 (001a): blx r0
0x42aa7804 (001c): data 0x8170(33136)
0x42aa7806 (001e): data 0x42b2(17074)
0x42aa7808 (0020): .align4
-------- chaining cell (normal): 0x0012
0x42aa7808 (0020): ldr r0, [r6, #84]
0x42aa780a (0022): blx r0
0x42aa780c (0024): data 0x8188(33160)
0x42aa780e (0026): data 0x42b2(17074)
-------- end of chaining cells (0x0028)
0x42aa7828 (0040): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa782c
total size is 64 bytes
0x42aa782c (0000): data 0x0028(40)
-------- entry offset: 0x000a
L0x000a:
-------- dalvik offset: 0x000a @ add-int/lit8 v0, v0, (#1)
0x42aa782e (0002): ldr r0, [r5, #0]
0x42aa7830 (0004): ldr r1, [r5, #4]
0x42aa7832 (0006): adds r0, r0, #1
-------- dalvik offset: 0x000c @ add-int/lit8 v1, v1, (#1)
0x42aa7834 (0008): adds r1, r1, #1
-------- dalvik offset: 0x000e @ goto, (#0), (#0)
0x42aa7836 (000a): str r0, [r5, #0]
0x42aa7838 (000c): str r1, [r5, #4]
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa783a (000e): ldr r2, [pc, #44]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa783c (0010): ldr r3, [r5, #4]
0x42aa783e (0012): cmp r3, r2
0x42aa7840 (0014): str r2, [r5, #8]
0x42aa7842 (0016): bge 0x42aa784c
Exception_Handling:
0x42aa7844 (0018): .align4
-------- chaining cell (normal): 0x0006
0x42aa7844 (0018): ldr r0, [r6, #84]
0x42aa7846 (001a): blx r0
0x42aa7848 (001c): data 0x8170(33136)
0x42aa784a (001e): data 0x42b2(17074)
0x42aa784c (0020): .align4
-------- chaining cell (normal): 0x0012
0x42aa784c (0020): ldr r0, [r6, #84]
0x42aa784e (0022): blx r0
0x42aa7850 (0024): data 0x8188(33160)
0x42aa7852 (0026): data 0x42b2(17074)
-------- end of chaining cells (0x0028)
0x42aa7868 (003c): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa786c
total size is 52 bytes
0x42aa786c (0000): data 0x0020(32)
-------- entry offset: 0x0006
L0x0006:
-------- dalvik offset: 0x0006 @ rem-int/lit8 v2, v3, (#2)
0x42aa786e (0002): ldr r2, [pc, #44]
0x42aa7870 (0004): ldr r0, [r5, #12]
0x42aa7872 (0006): movs r1, #2
0x42aa7874 (0008): blx r2
-------- dalvik offset: 0x0008 @ if-nez v2, (#7), (#0)
0x42aa7876 (000a): cmp r1, #0
0x42aa7878 (000c): str r1, [r5, #8]
0x42aa787a (000e): bne 0x42aa7884
Exception_Handling:
0x42aa787c (0010): .align4
-------- chaining cell (normal): 0x000a
0x42aa787c (0010): ldr r0, [r6, #84]
0x42aa787e (0012): blx r0
0x42aa7880 (0014): data 0x8178(33144)
0x42aa7882 (0016): data 0x42b2(17074)
0x42aa7884 (0018): .align4
-------- chaining cell (normal): 0x000f
0x42aa7884 (0018): ldr r0, [r6, #84]
0x42aa7886 (001a): blx r0
0x42aa7888 (001c): data 0x8182(33154)
0x42aa788a (001e): data 0x42b2(17074)
-------- end of chaining cells (0x0020)
0x42aa789c (0030): .word (0xafd33294)
Dumping LIR insns
installed code is at 0x42aa78a0
total size is 68 bytes
0x42aa78a0 (0000): data 0x0028(40)
-------- entry offset: 0x000f
L0x000f:
-------- dalvik offset: 0x000f @ add-int/lit8 v0, v0, (#1)
0x42aa78a2 (0002): ldr r0, [r5, #0]
0x42aa78a4 (0004): adds r0, r0, #1
0x42aa78a6 (0006): str r0, [r5, #0]
-------- dalvik offset: 0x0011 @ goto, (#0), (#0)
L0x000c:
-------- dalvik offset: 0x000c @ add-int/lit8 v1, v1, (#1)
0x42aa78a8 (0008): ldr r1, [r5, #4]
0x42aa78aa (000a): adds r1, r1, #1
0x42aa78ac (000c): str r1, [r5, #4]
-------- dalvik offset: 0x000e @ goto, (#0), (#0)
L0x0002:
-------- dalvik offset: 0x0002 @ const/16 v2, (#1000), (#0)
0x42aa78ae (000e): ldr r2, [pc, #48]
-------- dalvik offset: 0x0004 @ if-ge v1, v2, (#14)
0x42aa78b0 (0010): ldr r3, [r5, #4]
0x42aa78b2 (0012): cmp r3, r2
0x42aa78b4 (0014): str r2, [r5, #8]
0x42aa78b6 (0016): bge 0x42aa78c0
Exception_Handling:
0x42aa78b8 (0018): .align4
-------- chaining cell (normal): 0x0006
0x42aa78b8 (0018): ldr r0, [r6, #84]
0x42aa78ba (001a): blx r0
0x42aa78bc (001c): data 0x8170(33136)
0x42aa78be (001e): data 0x42b2(17074)
0x42aa78c0 (0020): .align4
-------- chaining cell (normal): 0x0012
0x42aa78c0 (0020): ldr r0, [r6, #84]
0x42aa78c2 (0022): blx r0
0x42aa78c4 (0024): data 0x8188(33160)
0x42aa78c6 (0026): data 0x42b2(17074)
-------- end of chaining cells (0x0028)
0x42aa78e0 (0040): .word (0x3e8)
Dumping LIR insns
installed code is at 0x42aa78e4
total size is 40 bytes
0x42aa78e4 (0000): data 0x0018(24)
-------- entry offset: 0x0008
L0x0008:
-------- dalvik offset: 0x0008 @ if-nez v2, (#7), (#0)
0x42aa78e6 (0002): ldr r0, [r5, #8]
0x42aa78e8 (0004): cmp r0, #0
0x42aa78ea (0006): bne 0x42aa78f4
Exception_Handling:
0x42aa78ec (0008): .align4
-------- chaining cell (normal): 0x000a
0x42aa78ec (0008): ldr r0, [r6, #84]
0x42aa78ee (000a): blx r0
0x42aa78f0 (000c): data 0x8178(33144)
0x42aa78f2 (000e): data 0x42b2(17074)
0x42aa78f4 (0010): .align4
-------- chaining cell (normal): 0x000f
0x42aa78f4 (0010): ldr r0, [r6, #84]
0x42aa78f6 (0012): blx r0
0x42aa78f8 (0014): data 0x8182(33154)
0x42aa78fa (0016): data 0x42b2(17074)
-------- end of chaining cells (0x0018)
#

[Ben Cheng]

It looks like you have hit a known bug in the JIT that we have fixed internally but the change didn't make it to the Froyo release. The duplicated traces will only happen during a short window which tends to only exist in micro benchmarks (that's how we found it out too). 

Thanks for reporting it.

-Ben

--

[Javed Absar]

Hi Ben:

 

The duplicated traces are there it seems even for EEMBC benchmarks (so not entirely sure if its only for micro-benchmarks..... unless I mis-understand what u mean by micro). 

 

Any particular "technical" reason why the fix didnt make it to Froyo release?

 

Also could u share the nature of the fix.

 

I also notice that there is some self-verification code as part of the trace-construction. Is it necessary?

 

Best Regards

J.

--
my homepage: http://www.javedabsar.com

[Deepak]

Would that mean the performance gains would further increase with this
fix ? What is the magnitude of increase ?

Is it possible to share this fix ?

Thanks,
Deepak

> ...
>
> read more »

[Ben Cheng]

The problem is really minor - the duplication only happens when multiple compilation requests for the same trace are entered in the compiler queue, and micro benchmarks with tight tiny loops happen to fit the timing criteria. The compiled code of the last compilation request will be dispatched so the performance impact is negligible albeit a small number of wasted bytes in the code cache.

The fix is trivial too. Since you can spot this problem you should be able to figure out where to patch the code in red. :-)

1) dalvik/vm/compiler/Frontend.c:dvmCompileTrace()

    /* If we've already compiled this trace, just return success */

    if (dvmJitGetCodeAddr(startCodePtr) && !info->discardResult) {

        /*

         * Make sure the codeAddress is NULL so that it won't clobber the

         * existing entry.

         */

        info->codeAddress = NULL;

        return true;

    }

2) dalvik/vm/compiler/Compiler.c:compilerThreadStart()

                    } else if (!work.result.discardResult &&

                               work.result.codeAddress) {

                        dvmJitSetCodeAddr(work.pc, work.result.codeAddress,

                                          work.result.instructionSet);

                    }

Hope this helps,

-Ben

--

[Deepak]

It did help. Thanks for sharing :-)