Bob Supnik <bsup
...@nauticusnet.nospam.com> wrote in message <
news:aggu1v0eqk48s6f34t9otfohatrp9c9f13@4ax.com>...
> Does anyone have a primary bootstrap for the PDP-11's Ethernet
> controllers (specifically the DEQNA/DELQA)?
> I'm looking for the 'small' bootstrap that would have been included in
> the MXV11B ROM's, or the KDJ11B ROMs, not the 4KB secondary boot ROM
> that was part of the DEQNA/DELQA itself.
Hopefully better late than never, but I finally got to digging and
found that the CIQNDC0 sources give an example bootstrap:
IDENTIFICATION
--------------
PRODUCT CODE: AC-T612A-MC
PRODUCT NAME: CIQNDC0 DEQNA ROM RESIDENT CODE
PRODUCT DATE: 29 June 1984
MAINTAINER: DIAGNOSTIC ENGINEERING
[...]
4.1 PRIMARY BOOT PROCESS
The primary boot, resident in the host, normally checks for the existence
of the device it is going to boot from, boots 512. bytes from the device,
verifies the operation, sets parameters and transfers to the "booted" code.
A suggested method for "checking" for a QNA is as follows:
Write a "2" (a module reset) into the QNA's CSR at location
17774456 or 17774476.
Read back the CSR and compare against an octal 000062.
If equal then there is most likely a QNA there.
If not equal (Bus time-out?) then "sniff" elsewhere.
Write a "0" back into the CSR to "reset" the reset bit.
If a QNA is present and it is to be used for the boot the first thing
then:
A descriptor for a 256. word "receive" is validated in the QNA.
Data is read into the host starting at location 0
The descriptor is 8 words long, words 0, 4, 5 and 6 will
contain operation status. Words 1, 2, 3, and 7 are constant.
Write a "1010" into the CSR to move the boot code into the QNA's
internal receive buffer and delay for approximately one second.
Write a "1000" into the CSR to move the data in the internal
receive buffer into host memory and delay for approximately one
second.
Reset the QNA and check the CSR for proper status.
Checked the receive descriptor for nominal states.
The Data transfer is verified.
If the QNA primary boot code detects a failure at this point the
host boot is re-entered.
Transfer is made to the first location of the freshly loaded
portion of the QNA BD ROM.
R1 contains the I/O Page address of the QNA (174440)
R0 contains a "000000" if the DECnet boot resident on the
QNA is to be used.
- or -
If R0 is greater than "000777" an effective JMP (R0) is
executed in lieu of the DECnet boot.
Location 12 contains a "000000" if the EPB is to halt when
an error is detected.
- or -
If loaction 12 is greater than "000000" an effective JMP @12
is executed in lieu of a "HALT".
4.1.1 EXPECTED VALUES FOR VERIFICATION
CSR is checked for a nominal state as are the status words in the receive
descriptor.
Status Nominal
---------------
CSR 000060 or 010060
FLAG 14xxxx
BSW1 14xxxx
BSW2 14xxxx
CSW0 177777
x - don't care bits
Next the actual data transfer is verified by checking the first three bytes
of the data transferred for standard values. These first locations and their
expected contents are:
Location Contents
--------------------------
0000-1 000240 (NOP)
0002 001 (a BR instruction)
0003 xxx
0004
.. The QNA Extended Primary Boot (EPB) code
0777
4.1.2 SAMPLE PRIMARY BOOT CODE
Below is an example of how a primary boot could be implemented on a typical
PDP-11 based host.
Upon entry R0 is coded to indicate which QNA is to be used for the boot.
The first 32K bytes of the host memory is assumed to be mapped 1 to 1
physical to logical. The I/O page is mapped to the last 4K.
Assume settings for R0 as follows:
R0 - Contains a "4" for QNA#1 @ 174440
Contains a "5" for QNA#2 @ 174460
PDP-11 code for booting the DEQNA EPB might be as follows:
mov #174440,r1 ; assume device is DEQNA #1
cmp #4,r0
beq 10$ ; good assumption
mov #174460,r1 ; select device at DEQNA #2
10$: mov #2,16(r1) ; assert QNA software reset
cmp #000062,16(r1) ; "nominal" status during reset
bne 90$ ;? not a proper response, halt
clr 16(r1) ; clear reset state and all others
mov #2000,r3 ; pick an address for descriptor
mov r3,r4
mov #100000,(r4)+ ; Flag word, changed to -1
mov (r3),(r4)+ ; Valid buffer descriptor, receive
clr (r4)+ ; location zero
mov #-400,(r4)+ ; 256. words or 512. bytes
clr (r4)+ ; Descriptor status 1, changed to -1
clr (r4)+ ; Descriptor status 2, changed to -1
mov (r3),(r4)+ ; Chain flag word, changed to -1
mov #020000,(r4) ; end descriptor code
mov r3,04(r1)
clr 06(r1) ; validate a receive descriptor
mov #1010,16(r1) ; Instruct QNA to unload the EPB code
clr r0 ; delay about 60 ms for transfer of
sob r0,. ; i8051 contents to receive FIFO
clr #1000,16(r1) ; Complete the EPB unload
clr r0 ; delay about 60 ms for transfer of
sob r0,. ; receive FIFO to host memory
mov #2,16(r1)
clr 16(r1) ; Final reset to complete operation
mov #2014,r4
bic #037777,(r4) ; check if last status word was updated
cmp #140000,(r4) ;
bne 90$ ;
cmp #240,@#0 ; check for QNA boot block
bne 90$ ;? operation data check
cmpb #001,@#3 ; check for "BR" opcode
bne 90$ ;? operation data check
mov #DECnet,r0 ; Load DECnet code (or other code into R0)
jmp @#0 ; go to extended primary boot
; R0 - set to zero for DECnet boot
; R1 - has address of QNA #1 or #2
90$: halt ;? QNA error, get back to host boot control?
br 90$
Tim.
