PDP-10, pager, and AC's

[Rob Doyle]

I'm still working on my KS10 FPGA. The CPU passes diagnostics but the
pager is still inoperative. Most of my PDP-10 experience was with a
KA-10 so I�m unfamiliar with PDP-10 paging�

I don�t understand how the pager interacts with the addressing of the
general purpose registers (AC�s). The logic that decodes the addressing
for the registers also includes the physical addressing signal. I can�t
figure out the polarity of the physical addressing signal.

Are AC accesses always physical or never physical?

What is the reasoning?

Rob.

[Dave Dyer]

The page mapping page 0 has to ignore addresses corresponding to the acs.

[jmfbahciv]

Dave Dyer wrote:
>
> The page mapping page 0 has to ignore addresses corresponding to the acs.
>

I just don't remember this stuff. he's working on a KS and that was different
from the KL or KI. Has the OP tried to read the monitor listings? For
TOPS-10, the contrasts between architectures will be on one listing page
under IFN< ...> macros.

I don't recall anything coming from Lewine about the KS design.

/BAH

[Alan Bawden]

Rob Doyle <radi...@gmail.com> writes:

> I'm still working on my KS10 FPGA. The CPU passes diagnostics but the
> pager is still inoperative. Most of my PDP-10 experience was with a

> KA-10 so I’m unfamiliar with PDP-10 paging…
>
> I don’t understand how the pager interacts with the addressing of the
> general purpose registers (AC’s). The logic that decodes the addressing
> for the registers also includes the physical addressing signal. I can’t

> figure out the polarity of the physical addressing signal.
>
> Are AC accesses always physical or never physical?

If I'm interpreting your question properly, I think the answer is "never
physical". But let me expand on that, because perhaps I'm misunderstanding
you.

So the KS10 (like the KL10) has 8 selectable sets of registers. The mechanism
for selecting which set of registers you are actually using has to be very
similar to the mechanism you use for selecting your page table, because
both are potentially involved whenever you access the contents of an
address.

So you might wonder what happens when you turn paging -off-? Now what are
you using for ACs? I can actually imagine -three- possible answers:

1. Addresses 0 - 17 actually reference physical memory 0 - 17.

2. You are using some -fixed- AC block (probably block 0).

3. The AC block selection mechanism is still in effect.

To remind myself how this works, I went and found some code I wrote many
years ago that ran on a bare metal KS10. One of the first things that code
does right after it is loaded, is to cycle through all 8 AC blocks,
selecting each in turn, and clearing all its ACs. Only -after- doing that
does my code enable paging. That code only makes sense if number 3 above
is the way the machine actually behaves.

In other words, there is no way to to disable the AC selection mechanism,
which is what I think you mean by "AC access is never physical".

--
Alan Bawden

[Rob Doyle]

My question is regarding PDP-10 paging - I don't think the question is
unique to the KS10 implementation.

This isn't a monitor issue. The KS pager is implemented in hardware
that is supported by microcode. The KS pager will emulate KI paging,
KL paging (limited to two sections), or both. The KS shipped with
both KI and KL paging enabled in the microcode.

Beyond that, the executive mode instructions that control the pager
are the same for the KL and KS.

Rob.

[glen herrmannsfeldt]

Rob Doyle <radi...@gmail.com> wrote:

> I'm still working on my KS10 FPGA. The CPU passes diagnostics but the
> pager is still inoperative. Most of my PDP-10 experience was with a

> KA-10 so I???m unfamiliar with PDP-10 paging???

> I don???t understand how the pager interacts with the addressing of the
> general purpose registers (AC???s). The logic that decodes the addressing
> for the registers also includes the physical addressing signal. I can???t

> figure out the polarity of the physical addressing signal.

> Are AC accesses always physical or never physical?

AA-H391A-TK_DECsystem-10_DECSYSTEM-20_Processor_Reference_Jun1982.pdf

ACs are always virtual addressed. The system would be much more
difficult to use otherwise.

As I understand from the above document, though, there are eight sets
of ACs, and the system can change which ones are addressed at any
one time.

See figure 1.6 in the above. The different virtual address space
configurations all have "fast memory" (ACs) at the top.

-- glen

[jmfbahciv]

Rob Doyle wrote:
> On 4/21/2013 7:46 AM, jmfbahciv wrote:
>>Dave Dyer wrote:
>>>
>>> The page mapping page 0 has to ignore addresses corresponding to
>>> the acs.
>>>
>>
>> I just don't remember this stuff. he's working on a KS and that was
>> different from the KL or KI. Has the OP tried to read the monitor
>> listings? For TOPS-10, the contrasts between architectures will be
>> on one listing page under IFN< ...> macros.
>>
>> I don't recall anything coming from Lewine about the KS design.
>>
>> /BAH
>
> My question is regarding PDP-10 paging - I don't think the question is
> unique to the KS10 implementation.
>
> This isn't a monitor issue. The KS pager is implemented in hardware
> that is supported by microcode. The KS pager will emulate KI paging,
> KL paging (limited to two sections), or both. The KS shipped with
> both KI and KL paging enabled in the microcode.

If you don't have the hardware reference manual for the KS, the only
documents which accurately describes the 3 flavors of paging is
the monitor because it uses the paging. I don't ever remember
reviewing the KS' spec. You can find the differences between the
3 by reading monitor listings and noticing which lines of code
require a IFN macro for KS, KL and KI. REading the MCOs may also
help for any differenced between the three but most of the KS
implementation work was done under a generic MCO. Fixes would
be isolated in later MCOs but I dodn't remember any about different
behaviro between paging styles.

I understand about hardware and software. I'm trying to tell you
wehre to find documentation.

>
> Beyond that, the executive mode instructions that control the pager
> are the same for the KL and KS.

I understand they may be spelled the same; this doesn't imply that
they behave the same. :-) The TOPS-10 monitor listings will help.

/BAH

[Rich Alderson]

Alan Bawden <al...@scooby-doo.csail.mit.edu> writes:

> Rob Doyle <radi...@gmail.com> writes:

>> I'm still working on my KS10 FPGA. The CPU passes diagnostics but the
>> pager is still inoperative. Most of my PDP-10 experience was with a
>> KA-10 so I'm unfamiliar with PDP-10 paging

>> I don't understand how the pager interacts with the addressing of the
>> general purpose registers (AC's). The logic that decodes the addressing
>> for the registers also includes the physical addressing signal. I can't
>> figure out the polarity of the physical addressing signal.

>> Are AC accesses always physical or never physical?

> If I'm interpreting your question properly, I think the answer is "never
> physical". But let me expand on that, because perhaps I'm misunderstanding
> you.

[snip]

> In other words, there is no way to to disable the AC selection mechanism,
> which is what I think you mean by "AC access is never physical".

Further to Alan's comments, there is another wrinkle in the handling of ACs
with respect to extended addressing as implemented in the KL10 and KS10
processors.

Memory locations 0-17 are masked by the ACs only in sections 0 and 1, which is
to say in addresses 0000,,000000-0000,,000017 and 0001,,00000000-0001,,000017.
In sections 2 and up, there is no masking of the first 16 locations of the
section by the ACs.

This was done so as to allow code that treated the ACs as memory locations to
move into a non-zero section and thereby address the full extent of the
extended address space (sections 0 and 1 on the KS10, 0 to 27 on the KL10).
Section 0 is treated differently, ordinarily providing only the address range
available to user mode progams on the KA10 and KI10; there is a special
sequence of instructions to change addressing from section 0 into a non-zero
section.

--
Rich Alderson ne...@alderson.users.panix.com
the russet leaves of an autumn oak/inspire once again the failed poet/
to take up his pen/and essay to place his meagre words upon the page...