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Message from discussion L3 protocol for data transmission from low resource FPGA to Linux embedded system [6/6]

Wojciech M. Zabolotny

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More options Aug 30 2012, 6:42 pm

Newsgroups: alt.sources

From: Wojciech M. Zabolotny <w...@ise.pw.edu.pl>

Date: Thu, 30 Aug 2012 22:42:22 +0000 (UTC)

Local: Thurs, Aug 30 2012 6:42 pm

Subject: L3 protocol for data transmission from low resource FPGA to Linux embedded system [6/6]

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Archive-name: fpga_l3_fade
Version: 0.2
Submitted-by: w...@ise.pw.edu.pl
Last-modified: 2012-08-30 +00:00
Copyright-Notice: Free software (partly GPL, partly BSD, partly public domain)

The 6th part - sources and scripts needed to compile the FPGA IP core for Spartan-3E Starter Kit board

#!/bin/sh
# This is a shell archive (produced by GNU sharutils 4.11.1).
# To extract the files from this archive, save it to some FILE, remove
# everything before the `#!/bin/sh' line above, then type `sh FILE'.
#
lock_dir=_sh00877
# Made on 2012-08-31 00:08 CEST by <root@WZLap>.
# Source directory was `/tmp/publik'.
#
# Existing files will *not* be overwritten, unless `-c' is specified.
#
# This shar contains:
# length mode name
# ------ ---------- ------------------------------------------
# 226 -rw-r--r-- FPGA/sk3e/coregen.cgp
# 3043 -rw-r--r-- FPGA/sk3e/dcm1.vhd
# 10494 -rw-r--r-- FPGA/sk3e/reg_int.v
# 23733 -rw-r--r-- FPGA/sk3e/sk3e_eth_art.tcl
# 23730 -rw-r--r-- FPGA/sk3e/spartan3e_eth_top.vhd
# 19847 -rw-r--r-- FPGA/sk3e/spartan3e.ucf
# 7066 -rw-r--r-- FPGA/sk3e/ack_fifo.xco
# 134 -rwxr--r-- FPGA/sk3e/build.sh
# 20545 -rw-r--r-- FPGA/sk3e/desc_manager_simple.vhd
#
MD5SUM=${MD5SUM-md5sum}
f=`${MD5SUM} --version | egrep '^md5sum .*(core|text)utils'`
test -n "${f}" && md5check=true || md5check=false
${md5check} || \
echo 'Note: not verifying md5sums. Consider installing GNU coreutils.'
if test "X$1" = "X-c"
then keep_file=''
else keep_file=true
fi
echo=echo
save_IFS="${IFS}"
IFS="${IFS}:"
gettext_dir=
locale_dir=
set_echo=false

for dir in $PATH
do
if test -f $dir/gettext \
&& ($dir/gettext --version >/dev/null 2>&1)
then
case `$dir/gettext --version 2>&1 | sed 1q` in
*GNU*) gettext_dir=$dir
set_echo=true
break ;;
esac
fi
done

if ${set_echo}
then
set_echo=false
for dir in $PATH
do
if test -f $dir/shar \
&& ($dir/shar --print-text-domain-dir >/dev/null 2>&1)
then
locale_dir=`$dir/shar --print-text-domain-dir`
set_echo=true
break
fi
done

if ${set_echo}
then
TEXTDOMAINDIR=$locale_dir
export TEXTDOMAINDIR
TEXTDOMAIN=sharutils
export TEXTDOMAIN
echo="$gettext_dir/gettext -s"
fi
fi
IFS="$save_IFS"
if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null
then if (echo -n test; echo 1,2,3) | grep n >/dev/null
then shar_n= shar_c='
'
else shar_n=-n shar_c= ; fi
else shar_n= shar_c='\c' ; fi
f=shar-touch.$$
st1=200112312359.59
st2=123123592001.59
st2tr=123123592001.5 # old SysV 14-char limit
st3=1231235901

if touch -am -t ${st1} ${f} >/dev/null 2>&1 && \
test ! -f ${st1} && test -f ${f}; then
shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"'

elif touch -am ${st2} ${f} >/dev/null 2>&1 && \
test ! -f ${st2} && test ! -f ${st2tr} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"'

elif touch -am ${st3} ${f} >/dev/null 2>&1 && \
test ! -f ${st3} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$2 "$8"'

else
shar_touch=:
echo
${echo} 'WARNING: not restoring timestamps. Consider getting and
installing GNU `touch'\'', distributed in GNU coreutils...'
echo
fi
rm -f ${st1} ${st2} ${st2tr} ${st3} ${f}
#
if test ! -d ${lock_dir} ; then :
else ${echo} "lock directory ${lock_dir} exists"
exit 1
fi
if mkdir ${lock_dir}
then ${echo} "x - created lock directory ${lock_dir}."
else ${echo} "x - failed to create lock directory ${lock_dir}."
exit 1
fi
# ============= FPGA/sk3e/coregen.cgp ==============
if test ! -d 'FPGA'; then
mkdir 'FPGA'
if test $? -eq 0
then ${echo} "x - created directory FPGA."
else ${echo} "x - failed to create directory FPGA."
exit 1
fi
fi
if test ! -d 'FPGA/sk3e'; then
mkdir 'FPGA/sk3e'
if test $? -eq 0
then ${echo} "x - created directory FPGA/sk3e."
else ${echo} "x - failed to create directory FPGA/sk3e."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'FPGA/sk3e/coregen.cgp'
then
${echo} "x - SKIPPING FPGA/sk3e/coregen.cgp (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/coregen.cgp (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/coregen.cgp' &&
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET package = fg320
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
SHAR_EOF
(set 20 12 08 28 23 58 22 'FPGA/sk3e/coregen.cgp'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/coregen.cgp'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/coregen.cgp failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/coregen.cgp': 'MD5 check failed'
) << \SHAR_EOF
2fc0dcd6fcfe038de688aa4cd86d4925 FPGA/sk3e/coregen.cgp
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/coregen.cgp'` -ne 226 && \
${echo} "restoration warning: size of 'FPGA/sk3e/coregen.cgp' is not 226"
fi
fi
# ============= FPGA/sk3e/dcm1.vhd ==============
if test ! -d 'FPGA/sk3e'; then
mkdir 'FPGA/sk3e'
if test $? -eq 0
then ${echo} "x - created directory FPGA/sk3e."
else ${echo} "x - failed to create directory FPGA/sk3e."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'FPGA/sk3e/dcm1.vhd'
then
${echo} "x - SKIPPING FPGA/sk3e/dcm1.vhd (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/dcm1.vhd (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/dcm1.vhd' &&
--------------------------------------------------------------------------- -----
-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------- -----
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application : xaw2vhdl
-- / / Filename : dcm1.vhd
-- /___/ /\ Timestamp : 08/28/2012 23:23:31
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/xl/ise_projects/sk3e_wz/sk3e_eth_art/src/dcm1.xaw -st dcm1.vhd
--Design Name: dcm1
--Device: xc3s500e-4fg320
--
-- Module dcm1
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.09 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.34 ns
X
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
X
entity dcm1 is
X port ( CLKIN_IN : in std_logic;
X RST_IN : in std_logic;
X CLKFX_OUT : out std_logic;
X CLKIN_IBUFG_OUT : out std_logic;
X CLK0_OUT : out std_logic;
X LOCKED_OUT : out std_logic);
end dcm1;
X
architecture BEHAVIORAL of dcm1 is
X signal CLKFB_IN : std_logic;
X signal CLKFX_BUF : std_logic;
X signal CLKIN_IBUFG : std_logic;
X signal CLK0_BUF : std_logic;
X signal GND_BIT : std_logic;
begin
X GND_BIT <= '0';
X CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
X CLK0_OUT <= CLKFB_IN;
X CLKFX_BUFG_INST : BUFG
X port map (I=>CLKFX_BUF,
X O=>CLKFX_OUT);
X
X CLKIN_IBUFG_INST : IBUFG
X port map (I=>CLKIN_IN,
X O=>CLKIN_IBUFG);
X
X CLK0_BUFG_INST : BUFG
X port map (I=>CLK0_BUF,
X O=>CLKFB_IN);
X
X DCM_SP_INST : DCM_SP
X generic map( CLK_FEEDBACK => "1X",
X CLKDV_DIVIDE => 2.0,
X CLKFX_DIVIDE => 25,
X CLKFX_MULTIPLY => 32,
X CLKIN_DIVIDE_BY_2 => FALSE,
X CLKIN_PERIOD => 20.000,
X CLKOUT_PHASE_SHIFT => "NONE",
X DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
X DFS_FREQUENCY_MODE => "LOW",
X DLL_FREQUENCY_MODE => "LOW",
X DUTY_CYCLE_CORRECTION => TRUE,
X FACTORY_JF => x"C080",
X PHASE_SHIFT => 0,
X STARTUP_WAIT => FALSE)
X port map (CLKFB=>CLKFB_IN,
X CLKIN=>CLKIN_IBUFG,
X DSSEN=>GND_BIT,
X PSCLK=>GND_BIT,
X PSEN=>GND_BIT,
X PSINCDEC=>GND_BIT,
X RST=>RST_IN,
X CLKDV=>open,
X CLKFX=>CLKFX_BUF,
X CLKFX180=>open,
X CLK0=>CLK0_BUF,
X CLK2X=>open,
X CLK2X180=>open,
X CLK90=>open,
X CLK180=>open,
X CLK270=>open,
X LOCKED=>LOCKED_OUT,
X PSDONE=>open,
X STATUS=>open);
X
end BEHAVIORAL;
X
X
SHAR_EOF
(set 20 12 08 28 23 23 31 'FPGA/sk3e/dcm1.vhd'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/dcm1.vhd'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/dcm1.vhd failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/dcm1.vhd': 'MD5 check failed'
) << \SHAR_EOF
77187cac0ee6d4a05ec9e9ca44b3c4d3 FPGA/sk3e/dcm1.vhd
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/dcm1.vhd'` -ne 3043 && \
${echo} "restoration warning: size of 'FPGA/sk3e/dcm1.vhd' is not 3043"
fi
fi
# ============= FPGA/sk3e/reg_int.v ==============
if test -n "${keep_file}" && test -f 'FPGA/sk3e/reg_int.v'
then
${echo} "x - SKIPPING FPGA/sk3e/reg_int.v (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/reg_int.v (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/reg_int.v' &&
module Reg_int (
input Reset ,
input Clk_reg ,
input CSB ,
input WRB ,
input [15:0] CD_in ,
output reg [15:0] CD_out ,
input [7:0] CA ,
X //Tx host interface
output [4:0] Tx_Hwmark ,
output [4:0] Tx_Lwmark ,
output pause_frame_send_en ,
output [15:0] pause_quanta_set ,
output MAC_tx_add_en ,
output FullDuplex ,
output [3:0] MaxRetry ,
output [5:0] IFGset ,
output [7:0] MAC_tx_add_prom_data ,
output [2:0] MAC_tx_add_prom_add ,
output MAC_tx_add_prom_wr ,
output tx_pause_en ,
output xoff_cpu ,
output xon_cpu ,
X //Rx host interface
output MAC_rx_add_chk_en ,
output [7:0] MAC_rx_add_prom_data ,
output [2:0] MAC_rx_add_prom_add ,
output MAC_rx_add_prom_wr ,
output broadcast_filter_en ,
output [15:0] broadcast_bucket_depth ,
output [15:0] broadcast_bucket_interval ,
output RX_APPEND_CRC ,
output [4:0] Rx_Hwmark ,
output [4:0] Rx_Lwmark ,
output CRC_chk_en ,
output [5:0] RX_IFG_SET ,
output [15:0] RX_MAX_LENGTH ,// 1518
output [6:0] RX_MIN_LENGTH ,// 64
X //RMON host interface
output [5:0] CPU_rd_addr ,
output CPU_rd_apply ,
input CPU_rd_grant ,
input [31:0] CPU_rd_dout ,
X //Phy int host interface
output Line_loop_en ,
output [2:0] Speed ,
X //MII to CPU
output [7:0] Divider ,// Divider for the host clock
output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
output [4:0] Rgad ,// Register Address (within the PHY)
output [4:0] Fiad ,// PHY Address
output NoPre ,// No Preamble (no 32-bit preamble)
output WCtrlData ,// Write Control Data operation
output RStat ,// Read Status operation
output ScanStat ,// Scan Status operation
input Busy ,// Busy Signal
input LinkFail ,// Link Integrity Signal
input Nvalid ,// Invalid Status (qualifier for the valid scan result)
input [15:0] Prsd ,// Read Status Data (data read from the PHY)
input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data
);
X
// RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA ,CD_in);
X RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
//Line below for 1Gb Ethernet
// RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
//Line below for 100Mb Ethernet
X RegCPUData U_0_034(Speed ,7'd034,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X
always @ (posedge Clk_reg or posedge Reset)
X if (Reset)
X CD_out <=0;
X else if (!CSB&&WRB)
X case (CA[7:1])
X 7'd00: CD_out<=Tx_Hwmark ;
X 7'd01: CD_out<=Tx_Lwmark ;
X 7'd02: CD_out<=pause_frame_send_en ;
X 7'd03: CD_out<=pause_quanta_set ;
X 7'd04: CD_out<=IFGset ;
X 7'd05: CD_out<=FullDuplex ;
X 7'd06: CD_out<=MaxRetry ;
X 7'd07: CD_out<=MAC_tx_add_en ;
X 7'd08: CD_out<=MAC_tx_add_prom_data ;
X 7'd09: CD_out<=MAC_tx_add_prom_add ;
X 7'd10: CD_out<=MAC_tx_add_prom_wr ;
X 7'd11: CD_out<=tx_pause_en ;
X 7'd12: CD_out<=xoff_cpu ;
X 7'd13: CD_out<=xon_cpu ;
X 7'd14: CD_out<=MAC_rx_add_chk_en ;
X 7'd15: CD_out<=MAC_rx_add_prom_data ;
X 7'd16: CD_out<=MAC_rx_add_prom_add ;
X 7'd17: CD_out<=MAC_rx_add_prom_wr ;
X 7'd18: CD_out<=broadcast_filter_en ;
X 7'd19: CD_out<=broadcast_bucket_depth ;
X 7'd20: CD_out<=broadcast_bucket_interval ;
X 7'd21: CD_out<=RX_APPEND_CRC ;
X 7'd22: CD_out<=Rx_Hwmark ;
X 7'd23: CD_out<=Rx_Lwmark ;
X 7'd24: CD_out<=CRC_chk_en ;
X 7'd25: CD_out<=RX_IFG_SET ;
X 7'd26: CD_out<=RX_MAX_LENGTH ;
X 7'd27: CD_out<=RX_MIN_LENGTH ;
X 7'd28: CD_out<=CPU_rd_addr ;
X 7'd29: CD_out<=CPU_rd_apply ;
X 7'd30: CD_out<=CPU_rd_grant ;
X 7'd31: CD_out<=CPU_rd_dout[15:0] ;
X 7'd32: CD_out<=CPU_rd_dout[31:16] ;
X 7'd33: CD_out<=Line_loop_en ;
X 7'd34: CD_out<=Speed ;
X default: CD_out<=0 ;
X endcase
X
X
endmodule
X
module RegCPUData(
RegOut,
CA_reg_set,
RegInit,
X
Reset,
Clk,
CWR_pulse,
CCSB,
CA_reg,
CD_in_reg
);
output[15:0] RegOut;
input[6:0] CA_reg_set;
input[15:0] RegInit;
//
input Reset;
input Clk;
input CWR_pulse;
input CCSB;
input[7:0] CA_reg;
input[15:0] CD_in_reg;
//
reg[15:0] RegOut;
X
always @(posedge Reset or posedge Clk)
X if(Reset)
X RegOut <=RegInit;
X else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
X RegOut <=CD_in_reg;
X
endmodule
SHAR_EOF
(set 20 12 08 29 14 23 34 'FPGA/sk3e/reg_int.v'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/reg_int.v'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/reg_int.v failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/reg_int.v': 'MD5 check failed'
) << \SHAR_EOF
2e6cec28738252a769ffd5d25886fe73 FPGA/sk3e/reg_int.v
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/reg_int.v'` -ne 10494 && \
${echo} "restoration warning: size of 'FPGA/sk3e/reg_int.v' is not 10494"
fi
fi
# ============= FPGA/sk3e/sk3e_eth_art.tcl ==============
if test -n "${keep_file}" && test -f 'FPGA/sk3e/sk3e_eth_art.tcl'
then
${echo} "x - SKIPPING FPGA/sk3e/sk3e_eth_art.tcl (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/sk3e_eth_art.tcl (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/sk3e_eth_art.tcl' &&
#
# Project automation script for sk3e_eth_art
#
# Created for ISE version 13.4
#
# This file contains several Tcl procedures (procs) that you can use to automate
# your project by running from xtclsh or the Project Navigator Tcl console.
# If you load this file (using the Tcl command: source sk3e_eth_art.tcl), then you can
# run any of the procs included here.
#
# This script is generated assuming your project has HDL sources.
# Several of the defined procs won't apply to an EDIF or NGC based project.
# If that is the case, simply remove them from this script.
#
# You may also edit any of these procs to customize them. See comments in each
# proc for more instructions.
#
# This file contains the following procedures:
#
# Top Level procs (meant to be called directly by the user):
# run_process: you can use this top-level procedure to run any processes
# that you choose to by adding and removing comments, or by
# adding new entries.
# rebuild_project: you can alternatively use this top-level procedure
# to recreate your entire project, and the run selected processes.
#
# Lower Level (helper) procs (called under in various cases by the top level procs):
# show_help: print some basic information describing how this script works
# add_source_files: adds the listed source files to your project.
# set_project_props: sets the project properties that were in effect when this
# script was generated.
# create_libraries: creates and adds file to VHDL libraries that were defined when
# this script was generated.
# set_process_props: set the process properties as they were set for your project
# when this script was generated.
#
X
set myProject "sk3e_eth_art"
set myScript "sk3e_eth_art.tcl"
X
#
# Main (top-level) routines
#
# run_process
# This procedure is used to run processes on an existing project. You may comment or
# uncomment lines to control which processes are run. This routine is set up to run
# the Implement Design and Generate Programming File processes by default. This proc
# also sets process properties as specified in the "set_process_props" proc. Only
# those properties which have values different from their current settings in the project
# file will be modified in the project.
#
proc run_process {} {
X
X global myScript
X global myProject
X
X ## put out a 'heartbeat' - so we know something's happening.
X puts "\n$myScript: running ($myProject)...\n"
X
X if { ! [ open_project ] } {
X return false
X }
X
X set_process_props
X #
X # Remove the comment characters (#'s) to enable the following commands
X # process run "Synthesize"
X # process run "Translate"
X # process run "Map"
X # process run "Place & Route"
X #
X set task "Implement Design"
X if { ! [run_task $task] } {
X puts "$myScript: $task run failed, check run output for details."
X project close
X return
X }
X
X set task "Generate Programming File"
X if { ! [run_task $task] } {
X puts "$myScript: $task run failed, check run output for details."
X project close
X return
X }
X
X puts "Run completed (successfully)."
X project close
X

}

X
#
# rebuild_project
#
# This procedure renames the project file (if it exists) and recreates the project.
# It then sets project properties and adds project sources as specified by the
# set_project_props and add_source_files support procs. It recreates VHDL Libraries
# as they existed at the time this script was generated.
#
# It then calls run_process to set process properties and run selected processes.
#
proc rebuild_project {} {
X
X global myScript
X global myProject
X
X project close
X ## put out a 'heartbeat' - so we know something's happening.
X puts "\n$myScript: Rebuilding ($myProject)...\n"
X
X set proj_exts [ list ise xise gise ]
X foreach ext $proj_exts {
X set proj_name "${myProject}.$ext"
X if { [ file exists $proj_name ] } {
X file delete $proj_name
X }
X }
X
X project new $myProject
X set_project_props
X add_source_files
X create_libraries
X puts "$myScript: project rebuild completed."
X
X run_process
X

}

X
#
# Support Routines
#
X
#
proc run_task { task } {
X
X # helper proc for run_process
X
X puts "Running '$task'"
X set result [ process run "$task" ]
X #
X # check process status (and result)
X set status [ process get $task status ]
X if { ( ( $status != "up_to_date" ) && \
X ( $status != "warnings" ) ) || \
X ! $result } {
X return false
X }
X return true

}

X
#
# show_help: print information to help users understand the options available when
# running this script.
#
proc show_help {} {
X
X global myScript
X
X puts ""
X puts "usage: xtclsh $myScript <options>"
X puts " or you can run xtclsh and then enter 'source $myScript'."
X puts ""
X puts "options:"
X puts " run_process - set properties and run processes."
X puts " rebuild_project - rebuild the project from scratch and run processes."
X puts " set_project_props - set project properties (device, speed, etc.)"
X puts " add_source_files - add source files"
X puts " create_libraries - create vhdl libraries"
X puts " set_process_props - set process property values"
X puts " show_help - print this message"
X puts ""

}

X
proc open_project {} {
X
X global myScript
X global myProject
X
X if { ! [ file exists ${myProject}.xise ] } {
X ## project file isn't there, rebuild it.
X puts "Project $myProject not found. Use project_rebuild to recreate it."
X return false
X }
X
X project open $myProject
X
X return true
X

}

#
# set_project_props
#
# This procedure sets the project properties as they were set in the project
# at the time this script was generated.
#
proc set_project_props {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Setting project properties..."
X
X project set family "Spartan3E"
X project set device "xc3s500e"
X project set package "fg320"
X project set speed "-4"
X project set top_level_module_type "HDL"
X project set synthesis_tool "XST (VHDL/Verilog)"
X project set simulator "ISim (VHDL/Verilog)"
X project set "Preferred Language" "VHDL"
X project set "Enable Message Filtering" "false"
X

}

X
X
#
# add_source_files
#
# This procedure add the source files that were known to the project at the
# time this script was generated.
#
proc add_source_files {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Adding sources to project..."
X
X xfile add "./ack_fifo.xco"
X xfile add "../src/ack_fifo/pkt_ack_pkg.vhd"
X xfile add "./dcm1.vhd"
X xfile add "../src/common/desc_manager_simple.vhd"
X xfile add "../src/common/dpram_inf.vhd"
X xfile add "../src/eth/Clk_ctrl.v"
X xfile add "../src/eth/MAC_rx.v"
X xfile add "../src/eth/MAC_rx/Broadcast_filter.v"
X xfile add "../src/eth/MAC_rx/CRC_chk.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_FF.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_add_chk.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_ctrl.v"
X xfile add "../src/eth/MAC_top.v"
X xfile add "../src/eth/MAC_tx.v"
X xfile add "../src/eth/MAC_tx/CRC_gen.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_Ctrl.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_FF.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_addr_add.v"
X xfile add "../src/eth/MAC_tx/Ramdon_gen.v"
X xfile add "../src/eth/MAC_tx/flow_ctrl.v"
X xfile add "../src/eth/Phy_int.v"
X xfile add "../src/eth/RMON.v"
X xfile add "../src/eth/RMON/RMON_addr_gen.v"
X xfile add "../src/eth/RMON/RMON_ctrl.v"
X xfile add "../src/eth/RMON/RMON_dpram.v"
X xfile add "../src/eth/TECH/xilinx/CLK_DIV2.v"
X xfile add "../src/eth/TECH/xilinx/CLK_SWITCH.v"
X xfile add "../src/eth/TECH/xilinx/duram.v"
X xfile add "../src/eth/afifo.v"
X xfile add "../src/eth/eth_miim.v"
X xfile add "../src/eth/miim/eth_clockgen.v"
X xfile add "../src/eth/miim/eth_outputcontrol.v"
X xfile add "../src/eth/miim/eth_shiftreg.v"
X xfile add "../src/eth/miim/timescale.v"
X xfile add "./reg_int.v"
X xfile add "../src/common/eth_receiver.vhd"
X xfile add "../src/common/eth_sender.vhd"
X xfile add "./spartan3e.ucf"
X xfile add "./spartan3e_eth_top.vhd"
X puts ""
X puts "WARNING: project contains IP cores, synthesis will fail if any of the cores require regenerating."
X puts ""
X
X # Set the Top Module as well...
X project set top "beh" "spart3e_sk_eth"
X
X puts "$myScript: project sources reloaded."
X

} ; # end add_source_files

X
#
# create_libraries
#
# This procedure defines VHDL libraries and associates files with those libraries.
# It is expected to be used when recreating the project. Any libraries defined
# when this script was generated are recreated by this procedure.
#
proc create_libraries {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Creating libraries..."
X
X
X # must close the project or library definitions aren't saved.
X project save
X

} ; # end create_libraries

X
#
# set_process_props
#
# This procedure sets properties as requested during script generation (either
# all of the properties, or only those modified from their defaults).
#
proc set_process_props {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: setting process properties..."
X
X project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
X project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
X project set "Filter Files From Compile Order" "true"
X project set "Last Applied Goal" "Balanced"
X project set "Last Applied Strategy" "Xilinx Default (unlocked)"
X project set "Last Unlock Status" "false"
X project set "Manual Compile Order" "false"
X project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
X project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
X project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
X project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
X project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
X project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
X project set "Project Description" ""
X project set "Property Specification in Project File" "Store all values"
X project set "Case Implementation Style" "None" -process "Synthesize - XST"
X project set "Decoder Extraction" "true" -process "Synthesize - XST"
X project set "Priority Encoder Extraction" "Yes" -process "Synthesize - XST"
X project set "Mux Extraction" "Yes" -process "Synthesize - XST"
X project set "RAM Extraction" "true" -process "Synthesize - XST"
X project set "ROM Extraction" "true" -process "Synthesize - XST"
X project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
X project set "Logical Shifter Extraction" "true" -process "Synthesize - XST"
X project set "Optimization Goal" "Speed" -process "Synthesize - XST"
X project set "Optimization Effort" "High" -process "Synthesize - XST"
X project set "Resource Sharing" "true" -process "Synthesize - XST"
X project set "Shift Register Extraction" "true" -process "Synthesize - XST"
X project set "XOR Collapsing" "true" -process "Synthesize - XST"
X project set "User Browsed Strategy Files" ""
X project set "VHDL Source Analysis Standard" "VHDL-93"
X project set "Input TCL Command Script" "" -process "Generate Text Power Report"
X project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
X project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Simulation File" "Default" -process "Generate Text Power Report"
X project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Setting File" "" -process "Generate Text Power Report"
X project set "Setting Output File" "" -process "Generate Text Power Report"
X project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
X project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
X project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
X project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
X project set "Show All Models" "false" -process "Generate IBIS Model"
X project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
X project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
X project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
X project set "Ignore User Timing Constraints" "false" -process "Map"
X project set "Use RLOC Constraints" "Yes" -process "Map"
X project set "Other Map Command Line Options" "" -process "Map"
X project set "Use LOC Constraints" "true" -process "Translate"
X project set "Other Ngdbuild Command Line Options" "" -process "Translate"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
X project set "Ignore User Timing Constraints" "false" -process "Place & Route"
X project set "Other Place & Route Command Line Options" "" -process "Place & Route"
X project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
X project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
X project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
X project set "Create Bit File" "true" -process "Generate Programming File"
X project set "Enable BitStream Compression" "false" -process "Generate Programming File"
X project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
X project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
X project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
X project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
X project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
X project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
X project set "Drive Done Pin High" "false" -process "Generate Programming File"
X project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
X project set "Wait for DLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
X project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
X project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
X project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
X project set "Optimization Strategy (Cover Mode)" "Area" -process "Map"
X project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
X project set "Generate Detailed MAP Report" "false" -process "Map"
X project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
X project set "Perform Timing-Driven Packing and Placement" "false" -process "Map"
X project set "Trim Unconnected Signals" "true" -process "Map"
X project set "Create I/O Pads from Ports" "false" -process "Translate"
X project set "Macro Search Path" "" -process "Translate"
X project set "Netlist Translation Type" "Timestamp" -process "Translate"
X project set "User Rules File for Netlister Launcher" "" -process "Translate"
X project set "Allow Unexpanded Blocks" "false" -process "Translate"
X project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
X project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
X project set "Placer Effort Level (Overrides Overall Level)" "None" -process "Place & Route"
X project set "Router Effort Level (Overrides Overall Level)" "None" -process "Place & Route"
X project set "Place And Route Mode" "Normal Place and Route" -process "Place & Route"
X project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
X project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
X project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
X project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
X project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
X project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
X project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
X project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
X project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
X project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
X project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
X project set "Add I/O Buffers" "true" -process "Synthesize - XST"
X project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
X project set "Keep Hierarchy" "No" -process "Synthesize - XST"
X project set "Register Balancing" "Yes" -process "Synthesize - XST"
X project set "Register Duplication" "true" -process "Synthesize - XST"
X project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
X project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
X project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
X project set "Bus Delimiter" "<>" -process "Synthesize - XST"
X project set "Case" "Maintain" -process "Synthesize - XST"
X project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
X project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
X project set "FSM Style" "LUT" -process "Synthesize - XST"
X project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
X project set "Generics, Parameters" "" -process "Synthesize - XST"
X project set "Hierarchy Separator" "/" -process "Synthesize - XST"
X project set "HDL INI File" "" -process "Synthesize - XST"
X project set "Library Search Order" "" -process "Synthesize - XST"
X project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
X project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST"
X project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
X project set "Read Cores" "true" -process "Synthesize - XST"
X project set "Slice Packing" "true" -process "Synthesize - XST"
X project set "Slice Utilization Ratio" "100" -process "Synthesize - XST"
X project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
X project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
X project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
X project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
X project set "Verilog Include Directories" "" -process "Synthesize - XST"
X project set "Verilog 2001" "true" -process "Synthesize - XST"
X project set "Verilog Macros" "" -process "Synthesize - XST"
X project set "Work Directory" "./xst" -process "Synthesize - XST"
X project set "Write Timing Constraints" "true" -process "Synthesize - XST"
X project set "Other XST Command Line Options" "" -process "Synthesize - XST"
X project set "Auto Implementation Compile Order" "true"
X project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
X project set "Power Reduction" "false" -process "Map"
X project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
X project set "Synthesis Constraints File" "" -process "Synthesize - XST"
X project set "Mux Style" "Auto" -process "Synthesize - XST"
X project set "RAM Style" "Auto" -process "Synthesize - XST"
X project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
X project set "Output File Name" "spart3e_sk_eth" -process "Generate IBIS Model"
X project set "Timing Mode" "Non Timing Driven" -process "Map"
X project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
X project set "Generate Clock Region Report" "false" -process "Place & Route"
X project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
X project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
X project set "Power Reduction" "false" -process "Place & Route"
X project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
X project set "Create Binary Configuration File" "false" -process "Generate Programming File"
X project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
X project set "CLB Pack Factor Percentage" "100" -process "Map"
X project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
X project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
X project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
X project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
X project set "ROM Style" "Auto" -process "Synthesize - XST"
X project set "Safe Implementation" "No" -process "Synthesize - XST"
X project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
X project set "Starting Placer Cost Table (1-100)" "1" -process "Place & Route"
X project set "Functional Model Target Language" "VHDL" -process "View HDL Source"
X project set "Change Device Speed To" "-4" -process "Generate Post-Place & Route Static Timing"
X project set "Change Device Speed To" "-4" -process "Generate Post-Map Static Timing"
X
X puts "$myScript: project property values set."
X

} ; # end set_process_props

X
proc main {} {
X
X if { [llength $::argv] == 0 } {
X show_help
X return true
X }
X
X foreach option $::argv {
X switch $option {
X "show_help" { show_help }
X "run_process" { run_process }
X "rebuild_project" { rebuild_project }
X "set_project_props" { set_project_props }
X "add_source_files" { add_source_files }
X "create_libraries" { create_libraries }
X "set_process_props" { set_process_props }
X default { puts "unrecognized option: $option"; show_help }
X }
X }

}

X
if { $tcl_interactive } {
X show_help

} else {

X if {[catch {main} result]} {
X puts "$myScript failed: $result."
X }

}

X
SHAR_EOF
(set 20 12 08 29 23 42 57 'FPGA/sk3e/sk3e_eth_art.tcl'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/sk3e_eth_art.tcl'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/sk3e_eth_art.tcl failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/sk3e_eth_art.tcl': 'MD5 check failed'
) << \SHAR_EOF
86d76a7a62cac2c9b35cbf013a6561a9 FPGA/sk3e/sk3e_eth_art.tcl
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/sk3e_eth_art.tcl'` -ne 23733 && \
${echo} "restoration warning: size of 'FPGA/sk3e/sk3e_eth_art.tcl' is not 23733"
fi
fi
# ============= FPGA/sk3e/spartan3e_eth_top.vhd ==============
if test -n "${keep_file}" && test -f 'FPGA/sk3e/spartan3e_eth_top.vhd'
then
${echo} "x - SKIPPING FPGA/sk3e/spartan3e_eth_top.vhd (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/spartan3e_eth_top.vhd (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/spartan3e_eth_top.vhd' &&
--------------------------------------------------------------------------- ----
-- Title : L3 FADE protocol demo for Spartan-3E Starter Kit board
-- Project :
--------------------------------------------------------------------------- ----
-- File : spartan3e_eth_top.vhd
-- Author : Wojciech M. Zabolotny <w...@ise.pw.edu.pl>
-- Company :
-- Created : 2007-12-31
-- Last update: 2012-08-29
-- Platform :
-- Standard : VHDL
--------------------------------------------------------------------------- ----
-- Description:
-- This file implements a simple entity with JTAG driven internal bus
-- allowing to control LEDs, read buttons, set two registers
-- and to read results of simple arithmetical operations
--------------------------------------------------------------------------- ----
-- Copyright (c) 2010
-- This is public domain code!!!
--------------------------------------------------------------------------- ----
-- Revisions :
-- Date Version Author Description
-- 2010-08-03 1.0 wzab Created
--------------------------------------------------------------------------- ----
X
X
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
X
library unisim;
use unisim.vcomponents.all;
X
entity spart3e_sk_eth is
X port(CLK_50MHZ : in std_logic;
X RS232_DCE_RXD : in std_logic;
X RS232_DCE_TXD : out std_logic;
X
X SD_CK_P : out std_logic; --DDR SDRAM clock_positive
X SD_CK_N : out std_logic; --clock_negative
X SD_CKE : out std_logic; --clock_enable
X
X SD_BA : out std_logic_vector(1 downto 0); --bank_address
X SD_A : out std_logic_vector(12 downto 0); --address(row or col)
X SD_CS : out std_logic; --chip_select
X SD_RAS : out std_logic; --row_address_strobe
X SD_CAS : out std_logic; --column_address_strobe
X SD_WE : out std_logic; --write_enable
X
X SD_DQ : inout std_logic_vector(15 downto 0); --data
X SD_UDM : out std_logic; --upper_byte_enable
X SD_UDQS : inout std_logic; --upper_data_strobe
X SD_LDM : out std_logic; --low_byte_enable
X SD_LDQS : inout std_logic; --low_data_strobe
X
X E_MDC : out std_logic; --Ethernet PHY
X E_MDIO : inout std_logic; --management data in/out
X E_COL : in std_logic;
X E_CRS : in std_logic;
X E_RX_CLK : in std_logic; --receive clock
X E_RX_ER : in std_logic; --receive error
X E_RX_DV : in std_logic; --data valid
X E_RXD : in std_logic_vector(3 downto 0);
X E_TX_CLK : in std_logic; --transmit clock
X E_TX_EN : out std_logic; --data valid
X E_TX_ER : out std_logic; --transmit error
X E_TXD : out std_logic_vector(3 downto 0);
X
X SF_CE0 : out std_logic; --NOR flash
X SF_OE : out std_logic;
X SF_WE : out std_logic;
X SF_BYTE : out std_logic;
X SF_STS : in std_logic; --status
X SF_A : out std_logic_vector(24 downto 0);
X SF_D : inout std_logic_vector(15 downto 1);
X SPI_MISO : inout std_logic;
X
X CDC_MCK : out std_logic;
X CDC_CSn : out std_logic;
X CDC_SDIN : out std_logic;
X CDC_SCLK : out std_logic;
X CDC_DIN : out std_logic;
X CDC_BCLK : out std_logic;
X --CDC_CLKOUT : in std_logic;
X CDC_DOUT : in std_logic;
X CDC_LRC_IN_OUT : out std_logic;
X
X VGA_VSYNC : out std_logic; --VGA port
X VGA_HSYNC : out std_logic;
X VGA_RED : out std_logic;
X VGA_GREEN : out std_logic;
X VGA_BLUE : out std_logic;
X
X PS2_CLK : in std_logic; --Keyboard
X PS2_DATA : in std_logic;
X
X LED : out std_logic_vector(7 downto 0);
X ROT_CENTER : in std_logic;
X ROT_A : in std_logic;
X ROT_B : in std_logic;
X BTN_EAST : in std_logic;
X BTN_NORTH : in std_logic;
X BTN_SOUTH : in std_logic;
X BTN_WEST : in std_logic;
X SW : in std_logic_vector(3 downto 0));
X
end spart3e_sk_eth;
X
architecture beh of spart3e_sk_eth is
X
X component dp_ram_scl
X generic (
X DATA_WIDTH : integer;
X ADDR_WIDTH : integer);
X port (
X clk : in std_logic;
X we_a : in std_logic;
X addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
X data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
X q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
X we_b : in std_logic;
X addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
X data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
X q_b : out std_logic_vector(DATA_WIDTH-1 downto 0));
X end component;
X
X component ack_fifo
X port (
X clk : in std_logic;
X rst : in std_logic;
X din : in std_logic_vector(pkt_ack_width-1 downto 0);
X wr_en : in std_logic;
X rd_en : in std_logic;
X dout : out std_logic_vector(pkt_ack_width-1 downto 0);
X full : out std_logic;
X empty : out std_logic);
X end component;
X
X component dcm1
X port(
X CLKIN_IN : in std_logic;
X RST_IN : in std_logic;
X CLKFX_OUT : out std_logic;
X CLKIN_IBUFG_OUT : out std_logic;
X CLK0_OUT : out std_logic;
X LOCKED_OUT : out std_logic
X );
X end component;
X
X component desc_manager
X generic (
X N_OF_PKTS : integer);
X port (
X dta : in std_logic_vector(31 downto 0);
X dta_we : in std_logic;
X dta_ready : out std_logic;
X set_number : out unsigned(15 downto 0);
X pkt_number : out unsigned(15 downto 0);
X snd_start : out std_logic;
X snd_ready : in std_logic;
X dmem_addr : out std_logic_vector(13 downto 0);
X dmem_dta : out std_logic_vector(31 downto 0);
X dmem_we : out std_logic;
X ack_fifo_empty : in std_logic;
X ack_fifo_rd_en : out std_logic;
X ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
X transmit_data : in std_logic;
X transm_delay : out unsigned(31 downto 0);
X clk : in std_logic;
X rst_n : in std_logic);
X end component;
X
X component eth_sender
X port (
X peer_mac : in std_logic_vector(47 downto 0);
X my_mac : in std_logic_vector(47 downto 0);
X my_ether_type : in std_logic_vector(15 downto 0);
X set_number : in unsigned(15 downto 0);
X pkt_number : in unsigned(15 downto 0);
X retry_number : in unsigned(15 downto 0);
X transm_delay : in unsigned(31 downto 0);
X clk : in std_logic;
X rst_n : in std_logic;
X ready : out std_logic;
X start : in std_logic;
X tx_mem_addr : out std_logic_vector(13 downto 0);
X tx_mem_data : in std_logic_vector(31 downto 0);
X Tx_mac_wa : in std_logic;
X Tx_mac_wr : out std_logic;
X Tx_mac_data : out std_logic_vector(31 downto 0);
X Tx_mac_BE : out std_logic_vector(1 downto 0);
X Tx_mac_sop : out std_logic;
X Tx_mac_eop : out std_logic);
X end component;
X
X component eth_receiver
X port (
X peer_mac : out std_logic_vector(47 downto 0);
X my_mac : in std_logic_vector(47 downto 0);
X my_ether_type : in std_logic_vector(15 downto 0);
X transmit_data : out std_logic;
X restart : out std_logic;
X ack_fifo_full : in std_logic;
X ack_fifo_wr_en : out std_logic;
X ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0);
X clk : in std_logic;
X rst_n : in std_logic;
X Rx_mac_pa : in std_logic;
X Rx_mac_ra : in std_logic;
X Rx_mac_rd : out std_logic;
X Rx_mac_data : in std_logic_vector(31 downto 0);
X Rx_mac_BE : in std_logic_vector(1 downto 0);
X Rx_mac_sop : in std_logic;
X Rx_mac_eop : in std_logic);
X end component;
X
X component jtag_bus_ctl
X generic (
X d_width : integer;
X a_width : integer);
X port (
X din : in std_logic_vector((d_width-1) downto 0);
X dout : out std_logic_vector((d_width-1) downto 0);
X addr : out std_logic_vector((a_width-1) downto 0);
X nwr : out std_logic;
X nrd : out std_logic);
X end component;
X
X component MAC_top
X port (
X --system signals
X Reset : in std_logic;
X Clk_125M : in std_logic;
X Clk_user : in std_logic;
X Clk_reg : in std_logic;
X Speed : out std_logic_vector(2 downto 0);
X --user interface
X Rx_mac_ra : out std_logic;
X Rx_mac_rd : in std_logic;
X Rx_mac_data : out std_logic_vector(31 downto 0);
X Rx_mac_BE : out std_logic_vector(1 downto 0);
X Rx_mac_pa : out std_logic;
X Rx_mac_sop : out std_logic;
X Rx_mac_eop : out std_logic;
X --user interface
X Tx_mac_wa : out std_logic;
X Tx_mac_wr : in std_logic;
X Tx_mac_data : in std_logic_vector(31 downto 0);
X Tx_mac_BE : in std_logic_vector(1 downto 0);
X Tx_mac_sop : in std_logic;
X Tx_mac_eop : in std_logic;
X -- pkg_lgth fifo
X Pkg_lgth_fifo_rd : in std_logic;
X Pkg_lgth_fifo_ra : out std_logic;
X Pkg_lgth_fifo_data : out std_logic_vector(15 downto 0);
X --Phy interface
X Gtx_clk : out std_logic; -- used only in GMII mode
X Rx_clk : in std_logic;
X Tx_clk : in std_logic; -- used only in MII mode
X Tx_er : out std_logic;
X Tx_en : out std_logic;
X Txd : out std_logic_vector(7 downto 0);
X Rx_er : in std_logic;
X Rx_dv : in std_logic;
X Rxd : in std_logic_vector(7 downto 0);
X Crs : in std_logic;
X Col : in std_logic;
X -- host interface
X CSB : in std_logic;
X WRB : in std_logic;
X CD_in : in std_logic_vector(15 downto 0);
X CD_out : out std_logic_vector(15 downto 0);
X CA : in std_logic_vector(7 downto 0);
X -- mdx
X Mdo : out std_logic; -- MII Management Data Output
X MdoEn : out std_logic; -- MII Management Data Output Enable
X Mdi : in std_logic;
X Mdc : out std_logic -- MII Management Data Clock
X );
X end component;
X
X signal my_mac : std_logic_vector(47 downto 0);
X constant my_ether_type : std_logic_vector(15 downto 0) := x"fade";
X signal transm_delay : unsigned(31 downto 0);
X signal restart : std_logic;
X signal dta : std_logic_vector(31 downto 0);
X signal dta_we : std_logic := '0';
X signal dta_ready : std_logic;
X signal snd_start : std_logic;
X signal snd_ready : std_logic;
X signal dmem_addr : std_logic_vector(13 downto 0);
X signal dmem_dta : std_logic_vector(31 downto 0);
X signal dmem_we : std_logic;
X signal addr_a, addr_b : integer;
X signal test_dta : unsigned(31 downto 0);
X signal tx_mem_addr : std_logic_vector(13 downto 0);
X signal tx_mem_data : std_logic_vector(31 downto 0);
X
X signal arg1, arg2, res1 : unsigned(7 downto 0);
X signal res2 : unsigned(15 downto 0);
X signal sender : std_logic_vector(47 downto 0);
X signal peer_mac : std_logic_vector(47 downto 0);
X signal inputs, din, dout : std_logic_vector(7 downto 0);
X signal addr : std_logic_vector(3 downto 0);
X signal leds : std_logic_vector(7 downto 0);
X signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic;
X signal cpu_reset, not_cpu_reset, rst_del : std_logic;
X
X signal set_number : unsigned(15 downto 0);
X signal pkt_number : unsigned(15 downto 0);
X signal retry_number : unsigned(15 downto 0) := (others => '0');
X signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0');
X
X
X signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0);
X signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic;
X signal transmit_data : std_logic := '0';
X
X signal read_addr : std_logic_vector(15 downto 0);
X signal read_data : std_logic_vector(15 downto 0);
X signal read_done, read_in_progress : std_logic;
X
X
X signal led_counter : integer := 0;
X signal tx_counter : integer := 10000;
X signal Reset : std_logic;
X signal s_gtx_clk : std_logic;
X signal sysclk : std_logic;
X signal Clk_125M : std_logic;
X signal Clk_user : std_logic;
X signal Clk_reg : std_logic;
X signal Speed : std_logic_vector(2 downto 0);
X signal Rx_mac_ra : std_logic;
X signal Rx_mac_rd : std_logic;
X signal Rx_mac_data : std_logic_vector(31 downto 0);
X signal Rx_mac_BE : std_logic_vector(1 downto 0);
X signal Rx_mac_pa : std_logic;
X signal Rx_mac_sop : std_logic;
X signal Rx_mac_eop : std_logic;
X signal Tx_mac_wa : std_logic;
X signal Tx_mac_wr : std_logic;
X signal Tx_mac_data : std_logic_vector(31 downto 0);
X signal Tx_mac_BE : std_logic_vector(1 downto 0);
X signal Tx_mac_sop : std_logic;
X signal Tx_mac_eop : std_logic;
X signal Pkg_lgth_fifo_rd : std_logic;
X signal Pkg_lgth_fifo_ra : std_logic;
X signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0);
X signal Gtx_clk : std_logic;
X signal Rx_clk : std_logic;
X signal Tx_clk : std_logic;
X signal Tx_er : std_logic;
X signal Tx_en : std_logic;
X signal s_Txd : std_logic_vector(7 downto 0);
X signal Rx_er : std_logic;
X signal Rx_dv : std_logic;
X signal s_Rxd : std_logic_vector(7 downto 0);
X signal Crs : std_logic;
X signal Col : std_logic;
X signal CSB : std_logic := '1';
X signal WRB : std_logic := '1';
X signal CD_in : std_logic_vector(15 downto 0) := (others => '0');
X signal CD_out : std_logic_vector(15 downto 0) := (others => '0');
X signal CA : std_logic_vector(7 downto 0) := (others => '0');
X signal s_Mdo : std_logic;
X signal s_MdoEn : std_logic;
X signal s_Mdi : std_logic;
X
X signal s_dta_we : std_logic;
X constant zeroes_32 : std_logic_vector(31 downto 0) := (others => '0');
X
begin -- beh
X
X cpu_reset <= not ROT_CENTER;
X -- Different not used signals
X sysclk <= clk_50mhz;
X sd_dq <= (others => 'Z');
X sf_oe <= '1';
X sf_we <= '1';
X sf_d <= (others => 'Z');
X
X sd_cs <= '1';
X sd_we <= '1';
X sd_ras <= '1';
X sd_cas <= '1';
X
X SD_CK_P <= '0';
X SD_CK_N <= '1';
X SD_CKE <= '0';
X
X SD_BA <= (others => '0');
X SD_A <= (others => '0');
X
X SD_UDM <= 'Z';
X SD_UDQS <= 'Z';
X SD_LDM <= 'Z';
X SD_LDQS <= 'Z';
X
X --E_MDC <= '1';
X --E_MDIO <= 'Z';
X --E_TX_ER <= '0';
X --E_TXD <= (others => '0');
X
X SF_CE0 <= '0';
X SF_BYTE <= '0';
X SF_A <= (others => '0');
X SPI_MISO <= 'Z';
X
X VGA_VSYNC <= '0';
X VGA_HSYNC <= '0';
X VGA_RED <= '0';
X VGA_GREEN <= '0';
X VGA_BLUE <= '0';
X
X -- Codec is not connected
X CDC_DIN <= '0';
X CDC_LRC_IN_OUT <= '0';
X CDC_BCLK <= '0';
X CDC_MCK <= '0';
X CDC_SCLK <= '0';
X CDC_SDIN <= '0';
X CDC_CSn <= '0';
X
X -- LEDs are not used
X LED <= LEDs;
X
X -- RS not used
X RS232_DCE_TXD <= '1';
X
X -- Allow selection of MAC with the DIP switch to allow testing
X -- with multiple boards!
X with SW(1 downto 0) select
X my_mac <=
X x"de_ad_ba_be_be_ef" when "00",
X x"de_ad_ba_be_be_e1" when "01",
X x"de_ad_ba_be_be_e2" when "10",
X x"de_ad_ba_be_be_e3" when "11",
X x"de_ad_ba_be_be_e4" when others;
X
-- iic_sda_main <= 'Z';
-- iic_scl_main <= 'Z';
X
X not_cpu_reset <= not cpu_reset;
X rst_p <= not rst_n;
X
-- flash_oe_b <= '1';
-- flash_we_b <= '1';
-- flash_ce_b <= '1';
X
X MAC_top_1 : MAC_top
X port map (
X Reset => rst_p,
X Clk_125M => Clk_125M,
X Clk_user => Clk_user,
X Clk_reg => Clk_user, -- was Clk_reg
X Speed => Speed,
X Rx_mac_ra => Rx_mac_ra,
X Rx_mac_rd => Rx_mac_rd,
X Rx_mac_data => Rx_mac_data,
X Rx_mac_BE => Rx_mac_BE,
X Rx_mac_pa => Rx_mac_pa,
X Rx_mac_sop => Rx_mac_sop,
X Rx_mac_eop => Rx_mac_eop,
X Tx_mac_wa => Tx_mac_wa,
X Tx_mac_wr => Tx_mac_wr,
X Tx_mac_data => Tx_mac_data,
X Tx_mac_BE => Tx_mac_BE,
X Tx_mac_sop => Tx_mac_sop,
X Tx_mac_eop => Tx_mac_eop,
X Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd,
X Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra,
X Pkg_lgth_fifo_data => Pkg_lgth_fifo_data,
X Gtx_clk => s_gtx_clk, -- not used
X Rx_clk => E_RX_CLK,
X Tx_clk => E_TX_CLK,
X Tx_er => E_TX_ER,
X Tx_en => E_TX_EN,
X Txd => s_TXD,
X Rx_er => E_RX_ER,
X Rx_dv => E_RX_DV,
X Rxd => s_RXD,
X Crs => E_CRS,
X Col => E_COL,
X -- Host interface
X CSB => CSB,
X WRB => WRB,
X CD_in => CD_in,
X CD_out => CD_out,
X CA => CA,
X -- MDI interface
X Mdo => s_Mdo,
X MdoEn => s_MdoEn,
X Mdi => s_Mdi,
X Mdc => E_MDC);
X
X s_RXD(3 downto 0) <= E_RXD;
X s_RXD(7 downto 4) <= (others => '0');
X E_TXD <= s_TXD(3 downto 0);
X
X Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra;
X
X addr_a <= to_integer(unsigned(dmem_addr));
X addr_b <= to_integer(unsigned(tx_mem_addr));
X
X dp_ram_scl_1 : dp_ram_scl
X generic map (
X DATA_WIDTH => 32,
X ADDR_WIDTH => 13)
X port map (
X clk => clk_user,
X we_a => dmem_we,
X addr_a => dmem_addr(12 downto 0),
X data_a => dmem_dta,
X q_a => open,
X we_b => '0',
X addr_b => tx_mem_addr(12 downto 0),
X data_b => zeroes_32,
X q_b => tx_mem_data);
X
X desc_manager_1 : desc_manager
X generic map (
X N_OF_PKTS => N_OF_PKTS)
X port map (
X dta => dta,
X dta_we => dta_we,
X dta_ready => dta_ready,
X set_number => set_number,
X pkt_number => pkt_number,
X snd_start => snd_start,
X snd_ready => snd_ready,
X dmem_addr => dmem_addr,
X dmem_dta => dmem_dta,
X dmem_we => dmem_we,
X ack_fifo_empty => ack_fifo_empty,
X ack_fifo_rd_en => ack_fifo_rd_en,
X ack_fifo_dout => ack_fifo_dout,
X transmit_data => transmit_data,
X transm_delay => transm_delay,
X clk => clk_user,
X rst_n => rst_n);
X
X eth_sender_1 : eth_sender
X port map (
X peer_mac => peer_mac,
X my_mac => my_mac,
X my_ether_type => my_ether_type,
X transm_delay => transm_delay,
X set_number => set_number,
X pkt_number => pkt_number,
X retry_number => retry_number,
X clk => clk_user,
X rst_n => rst_n,
X ready => snd_ready,
X start => snd_start,
X tx_mem_addr => tx_mem_addr,
X tx_mem_data => tx_mem_data,
X Tx_mac_wa => Tx_mac_wa,
X Tx_mac_wr => Tx_mac_wr,
X Tx_mac_data => Tx_mac_data,
X Tx_mac_BE => Tx_mac_BE,
X Tx_mac_sop => Tx_mac_sop,
X Tx_mac_eop => Tx_mac_eop);
X
X eth_receiver_1 : eth_receiver
X port map (
X peer_mac => peer_mac,
X my_mac => my_mac,
X my_ether_type => my_ether_type,
X restart => restart,
X transmit_data => transmit_data,
X ack_fifo_full => ack_fifo_full,
X ack_fifo_wr_en => ack_fifo_wr_en,
X ack_fifo_din => ack_fifo_din,
X clk => clk_user,
X rst_n => rst_n,
X Rx_mac_pa => Rx_mac_pa,
X Rx_mac_ra => Rx_mac_ra,
X Rx_mac_rd => Rx_mac_rd,
X Rx_mac_data => Rx_mac_data,
X Rx_mac_BE => Rx_mac_BE,
X Rx_mac_sop => Rx_mac_sop,
X Rx_mac_eop => Rx_mac_eop);
X
X -- We don't use 125MHz clock!
X s_gtx_clk <= '0';
X dcm1_1 : dcm1
X port map (
X CLKIN_IN => sysclk,
X RST_IN => not_cpu_reset,
X CLKFX_OUT => clk_user,
X CLKIN_IBUFG_OUT => open,
X CLK0_OUT => open,
X LOCKED_OUT => dcm_locked);
X
X process (Clk_user, not_cpu_reset)
X begin -- process
X if not_cpu_reset = '1' then -- asynchronous reset (active low)
X rst_n <= '0';
X rst_del <= '0';
X elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
X if restart = '1' then
X rst_n <= '0';
X rst_del <= '0';
X else
X if dcm_locked = '1' then
X rst_del <= '1';
X rst_n <= rst_del;
X end if;
X end if;
X end if;
X end process;
X
X -- reset
X
X --phy_reset <= rst_n;
X
X -- Connection of MDI
X s_Mdi <= E_MDIO;
X E_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo;
X
X ack_fifo_1 : ack_fifo
X port map (
X clk => Clk_user,
X rst => rst_p,
X din => ack_fifo_din,
X wr_en => ack_fifo_wr_en,
X rd_en => ack_fifo_rd_en,
X dout => ack_fifo_dout,
X full => ack_fifo_full,
X empty => ack_fifo_empty);
X
X --E_TXD <= s_Txd(3 downto 0);
X --s_Rxd <= "0000" & E_RXD;
X
X -- signal generator
X
X dta <= std_logic_vector(test_dta);
X s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0';
X dta_we <= s_dta_we;
X
X process (Clk_user, rst_n)
X begin -- process
X if rst_n = '0' then -- asynchronous reset (active low)
X test_dta <= (others => '0');
X elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
X if s_dta_we = '1' then
X test_dta <= test_dta + 1;
X end if;
X end if;
X end process;
X
X -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2));
X LEDs(0) <= snd_ready;
X LEDs(1) <= transmit_data;
X LEDs(2) <= not_cpu_reset;
X LEDs(3) <= Tx_mac_wa;
X
X
end beh;
SHAR_EOF
(set 20 12 08 29 01 07 00 'FPGA/sk3e/spartan3e_eth_top.vhd'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/spartan3e_eth_top.vhd'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/spartan3e_eth_top.vhd failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/spartan3e_eth_top.vhd': 'MD5 check failed'
) << \SHAR_EOF
6ff4e141ffbdb8e72d92118cc7dc1fcd FPGA/sk3e/spartan3e_eth_top.vhd
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/spartan3e_eth_top.vhd'` -ne 23730 && \
${echo} "restoration warning: size of 'FPGA/sk3e/spartan3e_eth_top.vhd' is not 23730"
fi
fi
# ============= FPGA/sk3e/spartan3e.ucf ==============
if test -n "${keep_file}" && test -f 'FPGA/sk3e/spartan3e.ucf'
then
${echo} "x - SKIPPING FPGA/sk3e/spartan3e.ucf (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/spartan3e.ucf (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/spartan3e.ucf' &&
#####################################################
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
#####################################################
# ==== Analog-to-Digital Converter (ADC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Programmable Gain Amplifier (AMP) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Pushbuttons (BTN) ====
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== Clock inputs (CLK) ====
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
#NET "CLK_50MHZ" PERIOD = 20 ns HIGH 40 %;
NET "CLK_50MHZ" PERIOD = 20 ns HIGH 50 %;
#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
# ==== Digital-to-Analog Converter (DAC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# ==== 1-Wire Secure EEPROM (DS)
#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== Ethernet PHY (E) ====
NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_ER" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" PERIOD = 30 ns HIGH 50 %;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TX_ER" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
# ==== FX2 Connector (FX2) ====
#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J1 6-pin accessory header
#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J2 6-pin accessory header
#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J4 6-pin accessory header
#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
X
NET "CDC_MCK" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_CSn" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_SDIN" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_SCLK" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_DIN" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_BCLK" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_DOUT" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
NET "CDC_LRC_IN_OUT" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
X
# ==== 6-pin header J1 ====
# These are shared connections with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J2 ====
# These are shared connections with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J4 ====
# These are shared connections with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== Character LCD (LCD) ====
#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# LCD data connections are shared with StrataFlash connections SF_D<11:8>
#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== Discrete LEDs (LED) ====
# These are shared connections with the FX2 connector
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== PS/2 Mouse/Keyboard Port (PS2) ====
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
# ==== Rotary Pushbutton Switch (ROT) ====
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== RS-232 Serial Ports (RS232) ====
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== STMicro SPI serial Flash (SPI) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Slide Switches (SW) ====
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
# ==== VGA Port (VGA) ====
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
# ==== Xilinx CPLD (XC) ====
#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "CLK_50MHZ" TNM_NET = "CLK_50MHZ";
#NET "clk_reg1" TNM_NET = "clk_reg1";
#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;
NET "E_TX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
X
TIMEGRP "E_TX_OUTS" OFFSET=OUT 20 ns BEFORE E_TX_CLK;
INST "E_TXD<0>" TNM="E_TX_OUTS";
INST "E_TXD<1>" TNM="E_TX_OUTS";
INST "E_TXD<2>" TNM="E_TX_OUTS";
INST "E_TXD<3>" TNM="E_TX_OUTS";
INST "E_TX_EN" TNM="E_TX_OUTS";
X
TIMEGRP "CDC_INS" OFFSET=IN 5 ns BEFORE "clk_50MHz";
INST "CDC_DOUT" TNM="CDC_INS";
X
TIMEGRP "CDC_SPI" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
INST "CDC_CSn" TNM="CDC_SPI";
INST "CDC_SDIN" TNM="CDC_SPI";
INST "CDC_SCLK" TNM="CDC_SPI";
X
TIMEGRP "CDC_CLK" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
INST "CDC_BCLK" TNM="CDC_CLK";
INST "CDC_MCK" TNM="CDC_CLK";
X
TIMEGRP "CDC_OUTS" OFFSET= OUT 10 ns BEFORE "clk_50MHz";
#TIMEGRP "CDC_OUTS" OFFSET= OUT 0 ns BEFORE "clk_50MHz";
INST "CDC_DIN" TNM="CDC_OUTS";
INST "CDC_LRC_IN_OUT" TNM="CDC_OUTS";
X
NET "E_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
X
#NET "CLK_50MHZ" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "dcm2_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
#PIN "dcm1_1/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
SHAR_EOF
(set 20 12 08 29 01 01 23 'FPGA/sk3e/spartan3e.ucf'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sk3e/spartan3e.ucf'
if test $? -ne 0
then ${echo} "restore of FPGA/sk3e/spartan3e.ucf failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sk3e/spartan3e.ucf': 'MD5 check failed'
) << \SHAR_EOF
ae744c15c5ac9d5ac3d630fdf0dcc853 FPGA/sk3e/spartan3e.ucf
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sk3e/spartan3e.ucf'` -ne 19847 && \
${echo} "restoration warning: size of 'FPGA/sk3e/spartan3e.ucf' is not 19847"
fi
fi
# ============= FPGA/sk3e/ack_fifo.xco ==============
if test -n "${keep_file}" && test -f 'FPGA/sk3e/ack_fifo.xco'
then
${echo} "x - SKIPPING FPGA/sk3e/ack_fifo.xco (file already exists)"
else
${echo} "x - extracting FPGA/sk3e/ack_fifo.xco (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sk3e/ack_fifo.xco' &&
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Tue Aug 28 21:19:54 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:8.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=ack_fifo
CSET data_count=false
CSET data_count_width=11
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_handshake_flag_options_axis=false
CSET enable_handshake_flag_options_rach=false
CSET enable_handshake_flag_options_rdch=false
CSET enable_handshake_flag_options_wach=false
CSET enable_handshake_flag_options_wdch=false
CSET enable_handshake_flag_options_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=Empty
CSET programmable_empty_type_rach=Empty
CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
CSET programmable_full_type_wach=Full
CSET programmable_full_type_wdch=Full
CSET programmable_full_type_wrch=Full
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET ...

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