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From: Wojciech M. Zabolotny <w...@ise.pw.edu.pl>
Newsgroups: alt.sources
Subject: L3 protocol for data transmission from low resource FPGA to Linux
embedded system [5/6]
Date: Thu, 30 Aug 2012 22:34:58 +0000 (UTC)
Organization: ICM, Uniwersytet Warszawski
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Archive-name: fpga_l3_fade
Version: 0.2
Submitted-by: w...@ise.pw.edu.pl
Last-modified: 2012-08-30 +00:00
Copyright-Notice: Free software (partly GPL, partly BSD, partly public domain)
The 5th part - sources and scripts needed to compile FPGA core for the SP601 board
#!/bin/sh
# This is a shell archive (produced by GNU sharutils 4.11.1).
# To extract the files from this archive, save it to some FILE, remove
# everything before the `#!/bin/sh' line above, then type `sh FILE'.
#
lock_dir=_sh00858
# Made on 2012-08-31 00:08 CEST by <root@WZLap>.
# Source directory was `/tmp/publik'.
#
# Existing files will *not* be overwritten, unless `-c' is specified.
#
# This shar contains:
# length mode name
# ------ ---------- ------------------------------------------
# 226 -rw-r--r-- FPGA/sp601/coregen.cgp
# 10494 -rw-r--r-- FPGA/sp601/reg_int.v
# 27783 -rw-r--r-- FPGA/sp601/sp601_eth.tcl
# 7864 -rw-r--r-- FPGA/sp601/dcm1.xco
# 2715 -rw-r--r-- FPGA/sp601/ack_fifo.xco
# 4827 -rw-r--r-- FPGA/sp601/sp601_eth.ucf
# 22288 -rw-r--r-- FPGA/sp601/sp601_eth_top.vhd
# 130 -rwxr--r-- FPGA/sp601/build.sh
#
MD5SUM=${MD5SUM-md5sum}
f=`${MD5SUM} --version | egrep '^md5sum .*(core|text)utils'`
test -n "${f}" && md5check=true || md5check=false
${md5check} || \
echo 'Note: not verifying md5sums. Consider installing GNU coreutils.'
if test "X$1" = "X-c"
then keep_file=''
else keep_file=true
fi
echo=echo
save_IFS="${IFS}"
IFS="${IFS}:"
gettext_dir=
locale_dir=
set_echo=false
for dir in $PATH
do
if test -f $dir/gettext \
&& ($dir/gettext --version >/dev/null 2>&1)
then
case `$dir/gettext --version 2>&1 | sed 1q` in
*GNU*) gettext_dir=$dir
set_echo=true
break ;;
esac
fi
done
if ${set_echo}
then
set_echo=false
for dir in $PATH
do
if test -f $dir/shar \
&& ($dir/shar --print-text-domain-dir >/dev/null 2>&1)
then
locale_dir=`$dir/shar --print-text-domain-dir`
set_echo=true
break
fi
done
if ${set_echo}
then
TEXTDOMAINDIR=$locale_dir
export TEXTDOMAINDIR
TEXTDOMAIN=sharutils
export TEXTDOMAIN
echo="$gettext_dir/gettext -s"
fi
fi
IFS="$save_IFS"
if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null
then if (echo -n test; echo 1,2,3) | grep n >/dev/null
then shar_n= shar_c='
'
else shar_n=-n shar_c= ; fi
else shar_n= shar_c='\c' ; fi
f=shar-touch.$$
st1=200112312359.59
st2=123123592001.59
st2tr=123123592001.5 # old SysV 14-char limit
st3=1231235901
if touch -am -t ${st1} ${f} >/dev/null 2>&1 && \
test ! -f ${st1} && test -f ${f}; then
shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"'
elif touch -am ${st2} ${f} >/dev/null 2>&1 && \
test ! -f ${st2} && test ! -f ${st2tr} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"'
elif touch -am ${st3} ${f} >/dev/null 2>&1 && \
test ! -f ${st3} && test -f ${f}; then
shar_touch='touch -am $3$4$5$6$2 "$8"'
else
shar_touch=:
echo
${echo} 'WARNING: not restoring timestamps. Consider getting and
installing GNU `touch'\'', distributed in GNU coreutils...'
echo
fi
rm -f ${st1} ${st2} ${st2tr} ${st3} ${f}
#
if test ! -d ${lock_dir} ; then :
else ${echo} "lock directory ${lock_dir} exists"
exit 1
fi
if mkdir ${lock_dir}
then ${echo} "x - created lock directory ${lock_dir}."
else ${echo} "x - failed to create lock directory ${lock_dir}."
exit 1
fi
# ============= FPGA/sp601/coregen.cgp ==============
if test ! -d 'FPGA'; then
mkdir 'FPGA'
if test $? -eq 0
then ${echo} "x - created directory FPGA."
else ${echo} "x - failed to create directory FPGA."
exit 1
fi
fi
if test ! -d 'FPGA/sp601'; then
mkdir 'FPGA/sp601'
if test $? -eq 0
then ${echo} "x - created directory FPGA/sp601."
else ${echo} "x - failed to create directory FPGA/sp601."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'FPGA/sp601/coregen.cgp'
then
${echo} "x - SKIPPING FPGA/sp601/coregen.cgp (file already exists)"
else
${echo} "x - extracting FPGA/sp601/coregen.cgp (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/coregen.cgp' &&
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SHAR_EOF
(set 20 12 08 30 22 51 39 'FPGA/sp601/coregen.cgp'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/coregen.cgp'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/coregen.cgp failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/coregen.cgp': 'MD5 check failed'
) << \SHAR_EOF
f7526add2d4aee2f71160b2c32ea5c47 FPGA/sp601/coregen.cgp
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/coregen.cgp'` -ne 226 && \
${echo} "restoration warning: size of 'FPGA/sp601/coregen.cgp' is not 226"
fi
fi
# ============= FPGA/sp601/reg_int.v ==============
if test ! -d 'FPGA/sp601'; then
mkdir 'FPGA/sp601'
if test $? -eq 0
then ${echo} "x - created directory FPGA/sp601."
else ${echo} "x - failed to create directory FPGA/sp601."
exit 1
fi
fi
if test -n "${keep_file}" && test -f 'FPGA/sp601/reg_int.v'
then
${echo} "x - SKIPPING FPGA/sp601/reg_int.v (file already exists)"
else
${echo} "x - extracting FPGA/sp601/reg_int.v (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/reg_int.v' &&
module Reg_int (
input Reset ,
input Clk_reg ,
input CSB ,
input WRB ,
input [15:0] CD_in ,
output reg [15:0] CD_out ,
input [7:0] CA ,
X //Tx host interface
output [4:0] Tx_Hwmark ,
output [4:0] Tx_Lwmark ,
output pause_frame_send_en ,
output [15:0] pause_quanta_set ,
output MAC_tx_add_en ,
output FullDuplex ,
output [3:0] MaxRetry ,
output [5:0] IFGset ,
output [7:0] MAC_tx_add_prom_data ,
output [2:0] MAC_tx_add_prom_add ,
output MAC_tx_add_prom_wr ,
output tx_pause_en ,
output xoff_cpu ,
output xon_cpu ,
X //Rx host interface
output MAC_rx_add_chk_en ,
output [7:0] MAC_rx_add_prom_data ,
output [2:0] MAC_rx_add_prom_add ,
output MAC_rx_add_prom_wr ,
output broadcast_filter_en ,
output [15:0] broadcast_bucket_depth ,
output [15:0] broadcast_bucket_interval ,
output RX_APPEND_CRC ,
output [4:0] Rx_Hwmark ,
output [4:0] Rx_Lwmark ,
output CRC_chk_en ,
output [5:0] RX_IFG_SET ,
output [15:0] RX_MAX_LENGTH ,// 1518
output [6:0] RX_MIN_LENGTH ,// 64
X //RMON host interface
output [5:0] CPU_rd_addr ,
output CPU_rd_apply ,
input CPU_rd_grant ,
input [31:0] CPU_rd_dout ,
X //Phy int host interface
output Line_loop_en ,
output [2:0] Speed ,
X //MII to CPU
output [7:0] Divider ,// Divider for the host clock
output [15:0] CtrlData ,// Control Data (to be written to the PHY reg.)
output [4:0] Rgad ,// Register Address (within the PHY)
output [4:0] Fiad ,// PHY Address
output NoPre ,// No Preamble (no 32-bit preamble)
output WCtrlData ,// Write Control Data operation
output RStat ,// Read Status operation
output ScanStat ,// Scan Status operation
input Busy ,// Busy Signal
input LinkFail ,// Link Integrity Signal
input Nvalid ,// Invalid Status (qualifier for the valid scan result)
input [15:0] Prsd ,// Read Status Data (data read from the PHY)
input WCtrlDataStart ,// This signals resets the WCTRLDATA bit in the MIIM Command register
input RStatStart ,// This signal resets the RSTAT BIT in the MIIM Command register
input UpdateMIIRX_DATAReg // Updates MII RX_DATA register with read data
);
X
// RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_000(Tx_Hwmark ,7'd000,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_001(Tx_Lwmark ,7'd001,16'h0009,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_002(pause_frame_send_en ,7'd002,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_003(pause_quanta_set ,7'd003,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_004(IFGset ,7'd004,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_005(FullDuplex ,7'd005,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_006(MaxRetry ,7'd006,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_007(MAC_tx_add_en ,7'd007,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_008(MAC_tx_add_prom_data ,7'd008,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_009(MAC_tx_add_prom_add ,7'd009,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_010(MAC_tx_add_prom_wr ,7'd010,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_011(tx_pause_en ,7'd011,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_012(xoff_cpu ,7'd012,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_013(xon_cpu ,7'd013,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_014(MAC_rx_add_chk_en ,7'd014,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_015(MAC_rx_add_prom_data ,7'd015,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_016(MAC_rx_add_prom_add ,7'd016,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_017(MAC_rx_add_prom_wr ,7'd017,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_018(broadcast_filter_en ,7'd018,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_019(broadcast_bucket_depth ,7'd019,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_020(broadcast_bucket_interval,7'd020,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_021(RX_APPEND_CRC ,7'd021,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_022(Rx_Hwmark ,7'd022,16'h001a,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_023(Rx_Lwmark ,7'd023,16'h0010,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_024(CRC_chk_en ,7'd024,16'h0001,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_025(RX_IFG_SET ,7'd025,16'h000c,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_026(RX_MAX_LENGTH ,7'd026,16'h2710,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_027(RX_MIN_LENGTH ,7'd027,16'h0040,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_028(CPU_rd_addr ,7'd028,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_029(CPU_rd_apply ,7'd029,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_030(CPU_rd_grant ,7'd030,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_031(CPU_rd_dout_l ,7'd031,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
// RegCPUData U_0_032(CPU_rd_dout_h ,7'd032,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X RegCPUData U_0_033(Line_loop_en ,7'd033,16'h0000,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
//Line below for 1Gb Ethernet
X RegCPUData U_0_034(Speed ,7'd034,16'h0004,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
//Line below for 100Mb Ethernet
// RegCPUData U_0_034(Speed ,7'd034,16'h0002,Reset,Clk_reg,!WRB,CSB,CA,CD_in);
X
always @ (posedge Clk_reg or posedge Reset)
X if (Reset)
X CD_out <=0;
X else if (!CSB&&WRB)
X case (CA[7:1])
X 7'd00: CD_out<=Tx_Hwmark ;
X 7'd01: CD_out<=Tx_Lwmark ;
X 7'd02: CD_out<=pause_frame_send_en ;
X 7'd03: CD_out<=pause_quanta_set ;
X 7'd04: CD_out<=IFGset ;
X 7'd05: CD_out<=FullDuplex ;
X 7'd06: CD_out<=MaxRetry ;
X 7'd07: CD_out<=MAC_tx_add_en ;
X 7'd08: CD_out<=MAC_tx_add_prom_data ;
X 7'd09: CD_out<=MAC_tx_add_prom_add ;
X 7'd10: CD_out<=MAC_tx_add_prom_wr ;
X 7'd11: CD_out<=tx_pause_en ;
X 7'd12: CD_out<=xoff_cpu ;
X 7'd13: CD_out<=xon_cpu ;
X 7'd14: CD_out<=MAC_rx_add_chk_en ;
X 7'd15: CD_out<=MAC_rx_add_prom_data ;
X 7'd16: CD_out<=MAC_rx_add_prom_add ;
X 7'd17: CD_out<=MAC_rx_add_prom_wr ;
X 7'd18: CD_out<=broadcast_filter_en ;
X 7'd19: CD_out<=broadcast_bucket_depth ;
X 7'd20: CD_out<=broadcast_bucket_interval ;
X 7'd21: CD_out<=RX_APPEND_CRC ;
X 7'd22: CD_out<=Rx_Hwmark ;
X 7'd23: CD_out<=Rx_Lwmark ;
X 7'd24: CD_out<=CRC_chk_en ;
X 7'd25: CD_out<=RX_IFG_SET ;
X 7'd26: CD_out<=RX_MAX_LENGTH ;
X 7'd27: CD_out<=RX_MIN_LENGTH ;
X 7'd28: CD_out<=CPU_rd_addr ;
X 7'd29: CD_out<=CPU_rd_apply ;
X 7'd30: CD_out<=CPU_rd_grant ;
X 7'd31: CD_out<=CPU_rd_dout[15:0] ;
X 7'd32: CD_out<=CPU_rd_dout[31:16] ;
X 7'd33: CD_out<=Line_loop_en ;
X 7'd34: CD_out<=Speed ;
X default: CD_out<=0 ;
X endcase
X
X
endmodule
X
module RegCPUData(
RegOut,
CA_reg_set,
RegInit,
X
Reset,
Clk,
CWR_pulse,
CCSB,
CA_reg,
CD_in_reg
);
output[15:0] RegOut;
input[6:0] CA_reg_set;
input[15:0] RegInit;
//
input Reset;
input Clk;
input CWR_pulse;
input CCSB;
input[7:0] CA_reg;
input[15:0] CD_in_reg;
//
reg[15:0] RegOut;
X
always @(posedge Reset or posedge Clk)
X if(Reset)
X RegOut <=RegInit;
X else if (CWR_pulse && !CCSB && CA_reg[7:1] ==CA_reg_set[6:0])
X RegOut <=CD_in_reg;
X
endmodule
SHAR_EOF
(set 20 12 08 27 22 09 21 'FPGA/sp601/reg_int.v'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/reg_int.v'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/reg_int.v failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/reg_int.v': 'MD5 check failed'
) << \SHAR_EOF
7154c0d5f387ee902082584c226ee09d FPGA/sp601/reg_int.v
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/reg_int.v'` -ne 10494 && \
${echo} "restoration warning: size of 'FPGA/sp601/reg_int.v' is not 10494"
fi
fi
# ============= FPGA/sp601/sp601_eth.tcl ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/sp601_eth.tcl'
then
${echo} "x - SKIPPING FPGA/sp601/sp601_eth.tcl (file already exists)"
else
${echo} "x - extracting FPGA/sp601/sp601_eth.tcl (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/sp601_eth.tcl' &&
#
# Project automation script for sp601_eth
#
# Created for ISE version 13.4
#
# This file contains several Tcl procedures (procs) that you can use to automate
# your project by running from xtclsh or the Project Navigator Tcl console.
# If you load this file (using the Tcl command: source sp601_eth.tcl), then you can
# run any of the procs included here.
#
# This script is generated assuming your project has HDL sources.
# Several of the defined procs won't apply to an EDIF or NGC based project.
# If that is the case, simply remove them from this script.
#
# You may also edit any of these procs to customize them. See comments in each
# proc for more instructions.
#
# This file contains the following procedures:
#
# Top Level procs (meant to be called directly by the user):
# run_process: you can use this top-level procedure to run any processes
# that you choose to by adding and removing comments, or by
# adding new entries.
# rebuild_project: you can alternatively use this top-level procedure
# to recreate your entire project, and the run selected processes.
#
# Lower Level (helper) procs (called under in various cases by the top level procs):
# show_help: print some basic information describing how this script works
# add_source_files: adds the listed source files to your project.
# set_project_props: sets the project properties that were in effect when this
# script was generated.
# create_libraries: creates and adds file to VHDL libraries that were defined when
# this script was generated.
# set_process_props: set the process properties as they were set for your project
# when this script was generated.
#
X
set myProject "sp601_eth"
set myScript "sp601_eth.tcl"
X
#
# Main (top-level) routines
#
# run_process
# This procedure is used to run processes on an existing project. You may comment or
# uncomment lines to control which processes are run. This routine is set up to run
# the Implement Design and Generate Programming File processes by default. This proc
# also sets process properties as specified in the "set_process_props" proc. Only
# those properties which have values different from their current settings in the project
# file will be modified in the project.
#
proc run_process {} {
X
X global myScript
X global myProject
X
X ## put out a 'heartbeat' - so we know something's happening.
X puts "\n$myScript: running ($myProject)...\n"
X
X if { ! [ open_project ] } {
X return false
X }
X
X set_process_props
X #
X # Remove the comment characters (#'s) to enable the following commands
X # process run "Synthesize"
X # process run "Translate"
X # process run "Map"
X # process run "Place & Route"
X #
X set task "Implement Design"
X if { ! [run_task $task] } {
X puts "$myScript: $task run failed, check run output for details."
X project close
X return
X }
X
X set task "Generate Programming File"
X if { ! [run_task $task] } {
X puts "$myScript: $task run failed, check run output for details."
X project close
X return
X }
X
X puts "Run completed (successfully)."
X project close
X
}
X
#
# rebuild_project
#
# This procedure renames the project file (if it exists) and recreates the project.
# It then sets project properties and adds project sources as specified by the
# set_project_props and add_source_files support procs. It recreates VHDL Libraries
# as they existed at the time this script was generated.
#
# It then calls run_process to set process properties and run selected processes.
#
proc rebuild_project {} {
X
X global myScript
X global myProject
X
X project close
X ## put out a 'heartbeat' - so we know something's happening.
X puts "\n$myScript: Rebuilding ($myProject)...\n"
X
X set proj_exts [ list ise xise gise ]
X foreach ext $proj_exts {
X set proj_name "${myProject}.$ext"
X if { [ file exists $proj_name ] } {
X file delete $proj_name
X }
X }
X
X project new $myProject
X set_project_props
X add_source_files
X create_libraries
X puts "$myScript: project rebuild completed."
X
X run_process
X
}
X
#
# Support Routines
#
X
#
proc run_task { task } {
X
X # helper proc for run_process
X
X puts "Running '$task'"
X set result [ process run "$task" ]
X #
X # check process status (and result)
X set status [ process get $task status ]
X if { ( ( $status != "up_to_date" ) && \
X ( $status != "warnings" ) ) || \
X ! $result } {
X return false
X }
X return true
}
X
#
# show_help: print information to help users understand the options available when
# running this script.
#
proc show_help {} {
X
X global myScript
X
X puts ""
X puts "usage: xtclsh $myScript <options>"
X puts " or you can run xtclsh and then enter 'source $myScript'."
X puts ""
X puts "options:"
X puts " run_process - set properties and run processes."
X puts " rebuild_project - rebuild the project from scratch and run processes."
X puts " set_project_props - set project properties (device, speed, etc.)"
X puts " add_source_files - add source files"
X puts " create_libraries - create vhdl libraries"
X puts " set_process_props - set process property values"
X puts " show_help - print this message"
X puts ""
}
X
proc open_project {} {
X
X global myScript
X global myProject
X
X if { ! [ file exists ${myProject}.xise ] } {
X ## project file isn't there, rebuild it.
X puts "Project $myProject not found. Use project_rebuild to recreate it."
X return false
X }
X
X project open $myProject
X
X return true
X
}
#
# set_project_props
#
# This procedure sets the project properties as they were set in the project
# at the time this script was generated.
#
proc set_project_props {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Setting project properties..."
X
X project set family "Spartan6"
X project set device "xc6slx16"
X project set package "csg324"
X project set speed "-2"
X project set top_level_module_type "HDL"
X project set synthesis_tool "XST (VHDL/Verilog)"
X project set simulator "ISim (VHDL/Verilog)"
X project set "Preferred Language" "VHDL"
X project set "Enable Message Filtering" "false"
X
}
X
X
#
# add_source_files
#
# This procedure add the source files that were known to the project at the
# time this script was generated.
#
proc add_source_files {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Adding sources to project..."
X
X xfile add "./ack_fifo.xco"
X xfile add "../src/ack_fifo/pkt_ack_pkg.vhd"
X xfile add "./dcm1.xco"
X xfile add "../src/common/desc_manager_simple.vhd"
X xfile add "../src/common/dpram_inf.vhd"
X xfile add "../src/eth/Clk_ctrl.v"
X xfile add "../src/eth/MAC_rx.v"
X xfile add "../src/eth/MAC_rx/Broadcast_filter.v"
X xfile add "../src/eth/MAC_rx/CRC_chk.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_FF.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_add_chk.v"
X xfile add "../src/eth/MAC_rx/MAC_rx_ctrl.v"
X xfile add "../src/eth/MAC_top.v"
X xfile add "../src/eth/MAC_tx.v"
X xfile add "../src/eth/MAC_tx/CRC_gen.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_Ctrl.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_FF.v"
X xfile add "../src/eth/MAC_tx/MAC_tx_addr_add.v"
X xfile add "../src/eth/MAC_tx/Ramdon_gen.v"
X xfile add "../src/eth/MAC_tx/flow_ctrl.v"
X xfile add "../src/eth/Phy_int.v"
X xfile add "../src/eth/RMON.v"
X xfile add "../src/eth/RMON/RMON_addr_gen.v"
X xfile add "../src/eth/RMON/RMON_ctrl.v"
X xfile add "../src/eth/RMON/RMON_dpram.v"
X xfile add "../src/eth/TECH/xilinx/CLK_DIV2.v"
X xfile add "../src/eth/TECH/xilinx/CLK_SWITCH.v"
X xfile add "../src/eth/TECH/xilinx/duram.v"
X xfile add "../src/eth/afifo.v"
X xfile add "../src/eth/eth_miim.v"
X xfile add "../src/eth/miim/eth_clockgen.v"
X xfile add "../src/eth/miim/eth_outputcontrol.v"
X xfile add "../src/eth/miim/eth_shiftreg.v"
X xfile add "../src/eth/miim/timescale.v"
X xfile add "./reg_int.v"
X xfile add "../src/common/eth_receiver.vhd"
X xfile add "../src/common/eth_sender.vhd"
X xfile add "./sp601_eth.ucf"
X xfile add "./sp601_eth_top.vhd"
X puts ""
X puts "WARNING: project contains IP cores, synthesis will fail if any of the cores require regenerating."
X puts ""
X
X # Set the Top Module as well...
X project set top "beh" "sp601_eth"
X
X puts "$myScript: project sources reloaded."
X
} ; # end add_source_files
X
#
# create_libraries
#
# This procedure defines VHDL libraries and associates files with those libraries.
# It is expected to be used when recreating the project. Any libraries defined
# when this script was generated are recreated by this procedure.
#
proc create_libraries {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: Creating libraries..."
X
X
X # must close the project or library definitions aren't saved.
X project save
X
} ; # end create_libraries
X
#
# set_process_props
#
# This procedure sets properties as requested during script generation (either
# all of the properties, or only those modified from their defaults).
#
proc set_process_props {} {
X
X global myScript
X
X if { ! [ open_project ] } {
X return false
X }
X
X puts "$myScript: setting process properties..."
X
X project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
X project set "Global Optimization" "Off" -process "Map"
X project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
X project set "Place And Route Mode" "Route Only" -process "Place & Route"
X project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
X project set "Filter Files From Compile Order" "true"
X project set "Last Applied Goal" "Balanced"
X project set "Last Applied Strategy" "Xilinx Default (unlocked)"
X project set "Last Unlock Status" "false"
X project set "Manual Compile Order" "false"
X project set "Placer Effort Level" "High" -process "Map"
X project set "Extra Cost Tables" "0" -process "Map"
X project set "LUT Combining" "Off" -process "Map"
X project set "Combinatorial Logic Optimization" "true" -process "Map"
X project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
X project set "Power Reduction" "Off" -process "Map"
X project set "Overwrite Existing Symbol" "false" -process "Create Schematic Symbol"
X project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
X project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
X project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
X project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
X project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
X project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
X project set "Project Description" ""
X project set "Property Specification in Project File" "Store all values"
X project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
X project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
X project set "Case Implementation Style" "None" -process "Synthesize - XST"
X project set "RAM Extraction" "true" -process "Synthesize - XST"
X project set "ROM Extraction" "true" -process "Synthesize - XST"
X project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
X project set "Optimization Goal" "Speed" -process "Synthesize - XST"
X project set "Optimization Effort" "High" -process "Synthesize - XST"
X project set "Resource Sharing" "true" -process "Synthesize - XST"
X project set "Shift Register Extraction" "true" -process "Synthesize - XST"
X project set "User Browsed Strategy Files" ""
X project set "VHDL Source Analysis Standard" "VHDL-93"
X project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
X project set "Input TCL Command Script" "" -process "Generate Text Power Report"
X project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
X project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Simulation File" "Default" -process "Generate Text Power Report"
X project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
X project set "Load Setting File" "" -process "Generate Text Power Report"
X project set "Setting Output File" "" -process "Generate Text Power Report"
X project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
X project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
X project set "Essential Bits" "false" -process "Generate Programming File"
X project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
X project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
X project set "Show All Models" "false" -process "Generate IBIS Model"
X project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
X project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
X project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
X project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
X project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
X project set "Ignore User Timing Constraints" "false" -process "Map"
X project set "Register Ordering" "4" -process "Map"
X project set "Use RLOC Constraints" "Yes" -process "Map"
X project set "Other Map Command Line Options" "" -process "Map"
X project set "Use LOC Constraints" "true" -process "Translate"
X project set "Other Ngdbuild Command Line Options" "" -process "Translate"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
X project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
X project set "Ignore User Timing Constraints" "false" -process "Place & Route"
X project set "Other Place & Route Command Line Options" "" -process "Place & Route"
X project set "Use DSP Block" "Auto" -process "Synthesize - XST"
X project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
X project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
X project set "Enable External Master Clock" "false" -process "Generate Programming File"
X project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
X project set "Create Bit File" "true" -process "Generate Programming File"
X project set "Enable BitStream Compression" "false" -process "Generate Programming File"
X project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
X project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
X project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
X project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
X project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
X project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
X project set "Configuration Rate" "2" -process "Generate Programming File"
X project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
X project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
X project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
X project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
X project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File"
X project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
X project set "FPGA Start-Up Clock" "JTAG Clock" -process "Generate Programming File"
X project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
X project set "Drive Done Pin High" "false" -process "Generate Programming File"
X project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
X project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
X project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
X project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
X project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
X project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
X project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
X project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
X project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
X project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
X project set "Allow Logic Optimization Across Hierarchy" "true" -process "Map"
X project set "Maximum Compression" "false" -process "Map"
X project set "Generate Detailed MAP Report" "false" -process "Map"
X project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
X project set "Perform Timing-Driven Packing and Placement" "false"
X project set "Trim Unconnected Signals" "true" -process "Map"
X project set "Create I/O Pads from Ports" "false" -process "Translate"
X project set "Macro Search Path" "" -process "Translate"
X project set "Netlist Translation Type" "Timestamp" -process "Translate"
X project set "User Rules File for Netlister Launcher" "" -process "Translate"
X project set "Allow Unexpanded Blocks" "false" -process "Translate"
X project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
X project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
X project set "Perform Advanced Analysis" "true" -process "Generate Post-Place & Route Static Timing"
X project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
X project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
X project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
X project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
X project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
X project set "Perform Advanced Analysis" "true" -process "Generate Post-Map Static Timing"
X project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
X project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
X project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
X project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
X project set "Number of Clock Buffers" "4" -process "Synthesize - XST"
X project set "Add I/O Buffers" "true" -process "Synthesize - XST"
X project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
X project set "Keep Hierarchy" "Yes" -process "Synthesize - XST"
X project set "Max Fanout" "100000" -process "Synthesize - XST"
X project set "Register Balancing" "Yes" -process "Synthesize - XST"
X project set "Register Duplication" "true" -process "Synthesize - XST"
X project set "Library for Verilog Sources" "" -process "Synthesize - XST"
X project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
X project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
X project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
X project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
X project set "Bus Delimiter" "<>" -process "Synthesize - XST"
X project set "Case" "Maintain" -process "Synthesize - XST"
X project set "Cores Search Directories" "" -process "Synthesize - XST"
X project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
X project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
X project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
X project set "FSM Style" "LUT" -process "Synthesize - XST"
X project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
X project set "Generics, Parameters" "" -process "Synthesize - XST"
X project set "Hierarchy Separator" "/" -process "Synthesize - XST"
X project set "HDL INI File" "" -process "Synthesize - XST"
X project set "LUT Combining" "Auto" -process "Synthesize - XST"
X project set "Library Search Order" "" -process "Synthesize - XST"
X project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
X project set "Optimize Instantiated Primitives" "true" -process "Synthesize - XST"
X project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
X project set "Power Reduction" "false" -process "Synthesize - XST"
X project set "Read Cores" "true" -process "Synthesize - XST"
X project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
X project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
X project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
X project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
X project set "Verilog Include Directories" "" -process "Synthesize - XST"
X project set "Verilog Macros" "" -process "Synthesize - XST"
X project set "Work Directory" "./xst" -process "Synthesize - XST"
X project set "Write Timing Constraints" "false" -process "Synthesize - XST"
X project set "Other XST Command Line Options" "" -process "Synthesize - XST"
X project set "Timing Mode" "Performance Evaluation" -process "Map"
X project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
X project set "Generate Clock Region Report" "false" -process "Place & Route"
X project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
X project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
X project set "Power Reduction" "false" -process "Place & Route"
X project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
X project set "Auto Implementation Compile Order" "true"
X project set "Equivalent Register Removal" "true" -process "Map"
X project set "Placer Extra Effort" "None" -process "Map"
X project set "Power Activity File" "" -process "Map"
X project set "Register Duplication" "On" -process "Map"
X project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
X project set "Synthesis Constraints File" "" -process "Synthesize - XST"
X project set "RAM Style" "Auto" -process "Synthesize - XST"
X project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
X project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
X project set "Output File Name" "sp601_eth" -process "Generate IBIS Model"
X project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
X project set "Create Binary Configuration File" "false" -process "Generate Programming File"
X project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
X project set "Create Logic Allocation File" "false" -process "Generate Programming File"
X project set "Create Mask File" "false" -process "Generate Programming File"
X project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
X project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
X project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File"
X project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
X project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
X project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
X project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
X project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
X project set "Enable Multi-Threading" "2" -process "Map"
X project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
X project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
X project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
X project set "ROM Style" "Auto" -process "Synthesize - XST"
X project set "Safe Implementation" "No" -process "Synthesize - XST"
X project set "Power Activity File" "" -process "Place & Route"
X project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
X project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
X project set "Encrypt Bitstream" "false" -process "Generate Programming File"
X project set "Enable Multi-Threading" "Off" -process "Place & Route"
X project set "AES Initial Vector" "" -process "Generate Programming File"
X project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
X project set "AES Key (Hex String)" "" -process "Generate Programming File"
X project set "Input Encryption Key File" "" -process "Generate Programming File"
X project set "Functional Model Target Language" "VHDL" -process "View HDL Source"
X project set "Change Device Speed To" "-2" -process "Generate Post-Place & Route Static Timing"
X project set "Change Device Speed To" "-2" -process "Generate Post-Map Static Timing"
X
X puts "$myScript: project property values set."
X
} ; # end set_process_props
X
proc main {} {
X
X if { [llength $::argv] == 0 } {
X show_help
X return true
X }
X
X foreach option $::argv {
X switch $option {
X "show_help" { show_help }
X "run_process" { run_process }
X "rebuild_project" { rebuild_project }
X "set_project_props" { set_project_props }
X "add_source_files" { add_source_files }
X "create_libraries" { create_libraries }
X "set_process_props" { set_process_props }
X default { puts "unrecognized option: $option"; show_help }
X }
X }
}
X
if { $tcl_interactive } {
X show_help
} else {
X if {[catch {main} result]} {
X puts "$myScript failed: $result."
X }
}
X
SHAR_EOF
(set 20 12 08 30 23 09 47 'FPGA/sp601/sp601_eth.tcl'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/sp601_eth.tcl'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/sp601_eth.tcl failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/sp601_eth.tcl': 'MD5 check failed'
) << \SHAR_EOF
935a96b930b9c9b82657740138717b26 FPGA/sp601/sp601_eth.tcl
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/sp601_eth.tcl'` -ne 27783 && \
${echo} "restoration warning: size of 'FPGA/sp601/sp601_eth.tcl' is not 27783"
fi
fi
# ============= FPGA/sp601/dcm1.xco ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/dcm1.xco'
then
${echo} "x - SKIPPING FPGA/sp601/dcm1.xco (file already exists)"
else
${echo} "x - extracting FPGA/sp601/dcm1.xco (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/dcm1.xco' &&
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Wed Aug 29 21:33:33 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:clk_wiz:3.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.3
# END Select
# BEGIN Parameters
CSET calc_done=DONE
CSET clk_in_sel_port=CLK_IN_SEL
CSET clk_out1_port=CLK_OUT1
CSET clk_out1_use_fine_ps_gui=false
CSET clk_out2_port=CLK_OUT2
CSET clk_out2_use_fine_ps_gui=false
CSET clk_out3_port=CLK_OUT3
CSET clk_out3_use_fine_ps_gui=false
CSET clk_out4_port=CLK_OUT4
CSET clk_out4_use_fine_ps_gui=false
CSET clk_out5_port=CLK_OUT5
CSET clk_out5_use_fine_ps_gui=false
CSET clk_out6_port=CLK_OUT6
CSET clk_out6_use_fine_ps_gui=false
CSET clk_out7_port=CLK_OUT7
CSET clk_out7_use_fine_ps_gui=false
CSET clk_valid_port=CLK_VALID
CSET clkfb_in_n_port=CLKFB_IN_N
CSET clkfb_in_p_port=CLKFB_IN_P
CSET clkfb_in_port=CLKFB_IN
CSET clkfb_in_signaling=SINGLE
CSET clkfb_out_n_port=CLKFB_OUT_N
CSET clkfb_out_p_port=CLKFB_OUT_P
CSET clkfb_out_port=CLKFB_OUT
CSET clkfb_stopped_port=CLKFB_STOPPED
CSET clkin1_jitter_ps=50.0
CSET clkin1_ui_jitter=0.010
CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=125.000
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
CSET clkout2_requested_out_freq=64.000
CSET clkout2_requested_phase=0.000
CSET clkout2_used=true
CSET clkout3_drives=BUFG
CSET clkout3_requested_duty_cycle=50.000
CSET clkout3_requested_out_freq=64.000
CSET clkout3_requested_phase=0.000
CSET clkout3_used=true
CSET clkout4_drives=BUFG
CSET clkout4_requested_duty_cycle=50.000
CSET clkout4_requested_out_freq=100.000
CSET clkout4_requested_phase=0.000
CSET clkout4_used=false
CSET clkout5_drives=BUFG
CSET clkout5_requested_duty_cycle=50.000
CSET clkout5_requested_out_freq=100.000
CSET clkout5_requested_phase=0.000
CSET clkout5_used=false
CSET clkout6_drives=BUFG
CSET clkout6_requested_duty_cycle=50.000
CSET clkout6_requested_out_freq=100.000
CSET clkout6_requested_phase=0.000
CSET clkout6_used=false
CSET clkout7_drives=BUFG
CSET clkout7_requested_duty_cycle=50.000
CSET clkout7_requested_out_freq=100.000
CSET clkout7_requested_phase=0.000
CSET clkout7_used=false
CSET clock_mgr_type=AUTO
CSET component_name=dcm1
CSET daddr_port=DADDR
CSET dclk_port=DCLK
CSET dcm_clk_feedback=1X
CSET dcm_clk_out1_port=CLKFX
CSET dcm_clk_out2_port=CLKDV
CSET dcm_clk_out3_port=CLK0
CSET dcm_clk_out4_port=CLK0
CSET dcm_clk_out5_port=CLK0
CSET dcm_clk_out6_port=CLK0
CSET dcm_clkdv_divide=2.0
CSET dcm_clkfx_divide=8
CSET dcm_clkfx_multiply=5
CSET dcm_clkgen_clk_out1_port=CLKFX
CSET dcm_clkgen_clk_out2_port=CLKFX
CSET dcm_clkgen_clk_out3_port=CLKFX
CSET dcm_clkgen_clkfx_divide=1
CSET dcm_clkgen_clkfx_md_max=0.000
CSET dcm_clkgen_clkfx_multiply=4
CSET dcm_clkgen_clkfxdv_divide=2
CSET dcm_clkgen_clkin_period=10.000
CSET dcm_clkgen_notes=None
CSET dcm_clkgen_spread_spectrum=NONE
CSET dcm_clkgen_startup_wait=false
CSET dcm_clkin_divide_by_2=false
CSET dcm_clkin_period=5.000
CSET dcm_clkout_phase_shift=NONE
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
CSET dcm_notes=None
CSET dcm_phase_shift=0
CSET dcm_pll_cascade=NONE
CSET dcm_startup_wait=false
CSET den_port=DEN
CSET din_port=DIN
CSET dout_port=DOUT
CSET drdy_port=DRDY
CSET dwe_port=DWE
CSET feedback_source=FDBK_AUTO
CSET in_freq_units=Units_MHz
CSET in_jitter_units=Units_UI
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
CSET jitter_options=UI
CSET jitter_sel=No_Jitter
CSET locked_port=LOCKED
CSET mmcm_bandwidth=OPTIMIZED
CSET mmcm_clkfbout_mult_f=4.000
CSET mmcm_clkfbout_phase=0.000
CSET mmcm_clkfbout_use_fine_ps=false
CSET mmcm_clkin1_period=10.000
CSET mmcm_clkin2_period=10.000
CSET mmcm_clkout0_divide_f=4.000
CSET mmcm_clkout0_duty_cycle=0.500
CSET mmcm_clkout0_phase=0.000
CSET mmcm_clkout0_use_fine_ps=false
CSET mmcm_clkout1_divide=1
CSET mmcm_clkout1_duty_cycle=0.500
CSET mmcm_clkout1_phase=0.000
CSET mmcm_clkout1_use_fine_ps=false
CSET mmcm_clkout2_divide=1
CSET mmcm_clkout2_duty_cycle=0.500
CSET mmcm_clkout2_phase=0.000
CSET mmcm_clkout2_use_fine_ps=false
CSET mmcm_clkout3_divide=1
CSET mmcm_clkout3_duty_cycle=0.500
CSET mmcm_clkout3_phase=0.000
CSET mmcm_clkout3_use_fine_ps=false
CSET mmcm_clkout4_cascade=false
CSET mmcm_clkout4_divide=1
CSET mmcm_clkout4_duty_cycle=0.500
CSET mmcm_clkout4_phase=0.000
CSET mmcm_clkout4_use_fine_ps=false
CSET mmcm_clkout5_divide=1
CSET mmcm_clkout5_duty_cycle=0.500
CSET mmcm_clkout5_phase=0.000
CSET mmcm_clkout5_use_fine_ps=false
CSET mmcm_clkout6_divide=1
CSET mmcm_clkout6_duty_cycle=0.500
CSET mmcm_clkout6_phase=0.000
CSET mmcm_clkout6_use_fine_ps=false
CSET mmcm_clock_hold=false
CSET mmcm_compensation=ZHOLD
CSET mmcm_divclk_divide=1
CSET mmcm_notes=None
CSET mmcm_ref_jitter1=0.010
CSET mmcm_ref_jitter2=0.010
CSET mmcm_startup_wait=false
CSET num_out_clks=3
CSET override_dcm=false
CSET override_dcm_clkgen=false
CSET override_mmcm=false
CSET override_pll=false
CSET platform=lin64
CSET pll_bandwidth=OPTIMIZED
CSET pll_clk_feedback=CLKFBOUT
CSET pll_clkfbout_mult=5
CSET pll_clkfbout_phase=0.000
CSET pll_clkin_period=5.000
CSET pll_clkout0_divide=4
CSET pll_clkout0_duty_cycle=0.500
CSET pll_clkout0_phase=0.000
CSET pll_clkout1_divide=8
CSET pll_clkout1_duty_cycle=0.500
CSET pll_clkout1_phase=0.000
CSET pll_clkout2_divide=8
CSET pll_clkout2_duty_cycle=0.500
CSET pll_clkout2_phase=0.000
CSET pll_clkout3_divide=1
CSET pll_clkout3_duty_cycle=0.500
CSET pll_clkout3_phase=0.000
CSET pll_clkout4_divide=1
CSET pll_clkout4_duty_cycle=0.500
CSET pll_clkout4_phase=0.000
CSET pll_clkout5_divide=1
CSET pll_clkout5_duty_cycle=0.500
CSET pll_clkout5_phase=0.000
CSET pll_compensation=SYSTEM_SYNCHRONOUS
CSET pll_divclk_divide=2
CSET pll_notes=None
CSET pll_ref_jitter=0.010
CSET power_down_port=POWER_DOWN
CSET prim_in_freq=200.000
CSET prim_in_jitter=0.010
CSET prim_source=Differential_clock_capable_pin
CSET primary_port=CLK_IN1
CSET primitive=MMCM
CSET primtype_sel=PLL_BASE
CSET psclk_port=PSCLK
CSET psdone_port=PSDONE
CSET psen_port=PSEN
CSET psincdec_port=PSINCDEC
CSET relative_inclk=REL_PRIMARY
CSET reset_port=RESET
CSET secondary_in_freq=100.000
CSET secondary_in_jitter=0.010
CSET secondary_port=CLK_IN2
CSET secondary_source=Single_ended_clock_capable_pin
CSET status_port=STATUS
CSET summary_strings=empty
CSET use_clk_valid=false
CSET use_clkfb_stopped=false
CSET use_dyn_phase_shift=false
CSET use_dyn_reconfig=false
CSET use_freeze=false
CSET use_freq_synth=true
CSET use_inclk_stopped=false
CSET use_inclk_switchover=false
CSET use_locked=true
CSET use_max_i_jitter=false
CSET use_min_o_jitter=false
CSET use_min_power=false
CSET use_phase_alignment=true
CSET use_power_down=false
CSET use_reset=true
CSET use_spread_spectrum=false
CSET use_status=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-09T17:33:40Z
# END Extra information
GENERATE
# CRC: aacd51df
SHAR_EOF
(set 20 12 08 29 23 33 33 'FPGA/sp601/dcm1.xco'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/dcm1.xco'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/dcm1.xco failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/dcm1.xco': 'MD5 check failed'
) << \SHAR_EOF
24754d1bfcff546cb5a2a0ea8eec0a89 FPGA/sp601/dcm1.xco
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/dcm1.xco'` -ne 7864 && \
${echo} "restoration warning: size of 'FPGA/sp601/dcm1.xco' is not 7864"
fi
fi
# ============= FPGA/sp601/ack_fifo.xco ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/ack_fifo.xco'
then
${echo} "x - SKIPPING FPGA/sp601/ack_fifo.xco (file already exists)"
else
${echo} "x - extracting FPGA/sp601/ack_fifo.xco (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/ack_fifo.xco' &&
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Mon Apr 16 20:47:28 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=ack_fifo
CSET data_count=false
CSET data_count_width=11
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1023
CSET full_threshold_negate_value=1022
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=1024
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-01-07T15:29:19Z
# END Extra information
GENERATE
# CRC: 2e8c307d
SHAR_EOF
(set 20 12 04 16 22 47 28 'FPGA/sp601/ack_fifo.xco'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/ack_fifo.xco'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/ack_fifo.xco failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/ack_fifo.xco': 'MD5 check failed'
) << \SHAR_EOF
5a0c6ac677a5f13c69869c3f69386bb9 FPGA/sp601/ack_fifo.xco
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/ack_fifo.xco'` -ne 2715 && \
${echo} "restoration warning: size of 'FPGA/sp601/ack_fifo.xco' is not 2715"
fi
fi
# ============= FPGA/sp601/sp601_eth.ucf ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/sp601_eth.ucf'
then
${echo} "x - SKIPPING FPGA/sp601/sp601_eth.ucf (file already exists)"
else
${echo} "x - extracting FPGA/sp601/sp601_eth.ucf (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/sp601_eth.ucf' &&
NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10
NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10
NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10
NET "GPIO_LED<0>" LOC = "E13"; ## 2 on DS11 LED
NET "GPIO_LED<1>" LOC = "C14"; ## 2 on DS12 LED
NET "GPIO_LED<2>" LOC = "C4"; ## 2 on DS13 LED
NET "GPIO_LED<3>" LOC = "A4"; ## 2 on DS14 LED
X
NET "SWITCHES<0>" LOC = "D14";
NET "SWITCHES<1>" LOC = "E12";
NET "SWITCHES<2>" LOC = "F12";
NET "SWITCHES<3>" LOC = "V13";
X
##
NET "CPU_RESET" LOC = "N4"; ## 2 on SW9 pushbutton
##
NET "PHY_COL" LOC = "L14"; ## 114 on U3
NET "PHY_CRS" LOC = "M13"; ## 115 on U3
NET "PHY_INT" LOC = "J13"; ## 32 on U3
NET "PHY_MDC" LOC = "N14"; ## 35 on U3
NET "PHY_MDIO" LOC = "P16"; ## 33 on U3
NET "PHY_RESET" LOC = "L13"; ## 36 on U3
NET "PHY_RXCLK" LOC = "L16"; ## 7 on U3
NET "PHY_RXCTL_RXDV" LOC = "N18"; ## 4 on U3
NET "PHY_RXD<0>" LOC = "M14"; ## 3 on U3
NET "PHY_RXD<1>" LOC = "U18"; ## 128 on U3
NET "PHY_RXD<2>" LOC = "U17"; ## 126 on U3
NET "PHY_RXD<3>" LOC = "T18"; ## 125 on U3
NET "PHY_RXD<4>" LOC = "T17"; ## 124 on U3
NET "PHY_RXD<5>" LOC = "N16"; ## 123 on U3
NET "PHY_RXD<6>" LOC = "N15"; ## 121 on U3
NET "PHY_RXD<7>" LOC = "P18"; ## 120 on U3
NET "PHY_RXER" LOC = "P17"; ## 8 on U3
NET "PHY_TXCLK" LOC = "B9"; ## 10 on U3
NET "PHY_TXCTL_TXEN" LOC = "B8"; ## 16 on U3
NET "PHY_TXC_GTXCLK" LOC = "A9"; ## 14 on U3
NET "PHY_TXD<0>" LOC = "F8"; ## 18 on U3
NET "PHY_TXD<1>" LOC = "G8"; ## 19 on U3
NET "PHY_TXD<2>" LOC = "A6"; ## 20 on U3
NET "PHY_TXD<3>" LOC = "B6"; ## 24 on U3
NET "PHY_TXD<4>" LOC = "E6"; ## 25 on U3
NET "PHY_TXD<5>" LOC = "F7"; ## 26 on U3
NET "PHY_TXD<6>" LOC = "A5"; ## 28 on U3
NET "PHY_TXD<7>" LOC = "C5"; ## 29 on U3
NET "PHY_TXER" LOC = "A8"; ## 13 on U3
##
NET "SYSCLK_N" LOC = "K16"; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP)
NET "SYSCLK_P" LOC = "K15"; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP)
##
#NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
#NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
#NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
#NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
#NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
#NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
#NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
#NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
#
NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
#
NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
#
PIN "dcm1_1/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
X
#Created by Constraints Editor (xc6slx16-csg324-2) - 2010/08/04
NET "sysclk_p" TNM_NET = sysclk_p;
TIMESPEC TS_sysclk_p = PERIOD "sysclk_p" 5 ns HIGH 50%;
NET "sysclk_n" TNM_NET = sysclk_n;
TIMESPEC TS_sysclk_n = PERIOD "sysclk_n" 5 ns HIGH 50%;
#Created by Constraints Editor (xc6slx16-csg324-2) - 2012/04/30
NET "phy_rxclk" TNM_NET = phy_rxclk;
TIMESPEC TS_phy_rxclk = PERIOD "phy_rxclk" 8 ns HIGH 50%;
NET "phy_txclk" TNM_NET = phy_txclk;
TIMESPEC TS_phy_txclk = PERIOD "phy_txclk" 40 ns HIGH 50%;
NET "phy_txc_gtxclk" TNM_NET = phy_txc_gtxclk;
TIMESPEC TS_phy_txc_gtxclk = PERIOD "phy_txc_gtx_clk" 8 ns HIGH 50%;
SHAR_EOF
(set 20 12 05 03 21 15 08 'FPGA/sp601/sp601_eth.ucf'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/sp601_eth.ucf'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/sp601_eth.ucf failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/sp601_eth.ucf': 'MD5 check failed'
) << \SHAR_EOF
bd23ca8a49b4a690e8d863939c542029 FPGA/sp601/sp601_eth.ucf
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/sp601_eth.ucf'` -ne 4827 && \
${echo} "restoration warning: size of 'FPGA/sp601/sp601_eth.ucf' is not 4827"
fi
fi
# ============= FPGA/sp601/sp601_eth_top.vhd ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/sp601_eth_top.vhd'
then
${echo} "x - SKIPPING FPGA/sp601/sp601_eth_top.vhd (file already exists)"
else
${echo} "x - extracting FPGA/sp601/sp601_eth_top.vhd (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/sp601_eth_top.vhd' &&
-------------------------------------------------------------------------------
-- Title : L3 FADE protocol demo for SP601 board
-- Project :
-------------------------------------------------------------------------------
-- File : sp601_eth_top.vhd
-- Author : Wojciech M. Zabolotny <w...@ise.pw.edu.pl>
-- License : BSD License
-- Company :
-- Created : 2010-08-03
-- Last update: 2012-05-03
-- Platform :
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- This file implements the top entity, integrating all component
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-- This is public domain code!!!
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-08-03 1.0 wzab Created
-------------------------------------------------------------------------------
X
X
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkt_ack_pkg.all;
use work.desc_mgr_pkg.all;
X
entity sp601_eth is
X
X port (
X cpu_reset : in std_logic;
-- -- DDR2 interface
-- ddr2_a : out std_logic_vector(12 downto 0);
-- ddr2_ba : out std_logic_vector(2 downto 0);
-- ddr2_cas_b : out std_logic;
-- ddr2_cke : out std_logic;
-- ddr2_clk_n : out std_logic;
-- ddr2_clk_p : out std_logic;
-- ddr2_dq : inout std_logic_vector(15 downto 0);
-- ddr2_ldm : out std_logic;
-- ddr2_ldqs_n : out std_logic;
-- ddr2_ldqs_p : out std_logic;
-- ddr2_odt : out std_logic;
-- ddr2_ras_b : out std_logic;
-- ddr2_udm : out std_logic;
-- ddr2_udqs_n : out std_logic;
-- ddr2_udqs_p : out std_logic;
-- ddr2_we_b : out std_logic;
-- -- FLASH interface
-- flash_a : out std_logic_vector(24 downto 0);
X flash_ce_b : out std_logic;
-- flash_d : inout std_logic_vector(7 downto 0);
X flash_oe_b : out std_logic;
X flash_we_b : out std_logic;
-- -- FMC interface
-- fmc_la28_n : out std_logic;
-- fmc_la28_p : out std_logic;
-- fmc_la29_n : out std_logic;
-- fmc_la29_p : out std_logic;
-- fmc_la30_n : out std_logic;
-- fmc_la30_p : out std_logic;
-- fmc_la31_n : out std_logic;
-- fmc_la31_p : out std_logic;
X iic_scl_main : out std_logic;
X iic_sda_main : out std_logic;
X
X gpio_hdr0 : in std_logic;
X gpio_hdr1 : in std_logic;
X gpio_hdr2 : in std_logic;
X gpio_hdr3 : in std_logic;
X gpio_hdr4 : in std_logic;
X gpio_hdr5 : in std_logic;
X gpio_hdr6 : in std_logic;
X gpio_hdr7 : in std_logic;
X
-- fmc_clk0_m2c_n : out std_logic;
-- fmc_clk0_m2c_p : out std_logic;
-- fmc_clk1_m2c_n : out std_logic;
-- fmc_clk1_m2c_p : out std_logic;
-- fmc_la00_cc_n : out std_logic;
-- fmc_la00_cc_p : out std_logic;
-- fmc_la01_cc_n : out std_logic;
-- fmc_la01_cc_p : out std_logic;
-- fmc_la02_n : out std_logic;
-- fmc_la02_p : out std_logic;
-- fmc_la03_n : out std_logic;
-- fmc_la03_p : out std_logic;
-- fmc_la04_n : out std_logic;
-- fmc_la04_p : out std_logic;
-- led : out std_logic_vector(3 downto 0);
X switches : in std_logic_vector(3 downto 0);
-- flash_oen : out std_logic;
-- flash_wen : out std_logic;
-- flash_cen : out std_logic;
X gpio_led : out std_logic_vector(3 downto 0);
X -- PHY interface
X phy_col : in std_logic;
X phy_crs : in std_logic;
X phy_int : in std_logic;
X phy_mdc : out std_logic;
X phy_mdio : inout std_logic;
X phy_reset : out std_logic;
X phy_rxclk : in std_logic;
X phy_rxctl_rxdv : in std_logic;
X phy_rxd : in std_logic_vector(7 downto 0);
X phy_rxer : in std_logic;
X phy_txclk : in std_logic;
X phy_txctl_txen : out std_logic;
X phy_txc_gtxclk : out std_logic;
X phy_txd : out std_logic_vector(7 downto 0);
X phy_txer : out std_logic;
X sysclk_n : in std_logic;
X sysclk_p : in std_logic
X );
X
end sp601_eth;
X
architecture beh of sp601_eth is
X
X component dp_ram_scl
X generic (
X DATA_WIDTH : integer;
X ADDR_WIDTH : integer);
X port (
X clk : in std_logic;
X we_a : in std_logic;
X addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
X data_a : in std_logic_vector(DATA_WIDTH-1 downto 0);
X q_a : out std_logic_vector(DATA_WIDTH-1 downto 0);
X we_b : in std_logic;
X addr_b : in std_logic_vector(ADDR_WIDTH-1 downto 0);
X data_b : in std_logic_vector(DATA_WIDTH-1 downto 0);
X q_b : out std_logic_vector(DATA_WIDTH-1 downto 0));
X end component;
X
X component ack_fifo
X port (
X clk : in std_logic;
X rst : in std_logic;
X din : in std_logic_vector(pkt_ack_width-1 downto 0);
X wr_en : in std_logic;
X rd_en : in std_logic;
X dout : out std_logic_vector(pkt_ack_width-1 downto 0);
X full : out std_logic;
X empty : out std_logic);
X end component;
X
X component dcm1
X port
X ( -- Clock in ports
X CLK_IN1_P : in std_logic;
X CLK_IN1_N : in std_logic;
X -- Clock out ports
X CLK_OUT1 : out std_logic;
X CLK_OUT2 : out std_logic;
X CLK_OUT3 : out std_logic;
X -- Status and control signals
X RESET : in std_logic;
X LOCKED : out std_logic
X );
X end component;
X
X component desc_manager
X generic (
X N_OF_PKTS : integer);
X port (
X dta : in std_logic_vector(31 downto 0);
X dta_we : in std_logic;
X dta_ready : out std_logic;
X set_number : out unsigned(15 downto 0);
X pkt_number : out unsigned(15 downto 0);
X snd_start : out std_logic;
X snd_ready : in std_logic;
X dmem_addr : out std_logic_vector(13 downto 0);
X dmem_dta : out std_logic_vector(31 downto 0);
X dmem_we : out std_logic;
X ack_fifo_empty : in std_logic;
X ack_fifo_rd_en : out std_logic;
X ack_fifo_dout : in std_logic_vector(pkt_ack_width-1 downto 0);
X transmit_data : in std_logic;
X transm_delay : out unsigned(31 downto 0);
X clk : in std_logic;
X rst_n : in std_logic);
X end component;
X
X component eth_sender
X port (
X peer_mac : in std_logic_vector(47 downto 0);
X my_mac : in std_logic_vector(47 downto 0);
X my_ether_type : in std_logic_vector(15 downto 0);
X set_number : in unsigned(15 downto 0);
X pkt_number : in unsigned(15 downto 0);
X retry_number : in unsigned(15 downto 0);
X transm_delay : in unsigned(31 downto 0);
X clk : in std_logic;
X rst_n : in std_logic;
X ready : out std_logic;
X start : in std_logic;
X tx_mem_addr : out std_logic_vector(13 downto 0);
X tx_mem_data : in std_logic_vector(31 downto 0);
X Tx_mac_wa : in std_logic;
X Tx_mac_wr : out std_logic;
X Tx_mac_data : out std_logic_vector(31 downto 0);
X Tx_mac_BE : out std_logic_vector(1 downto 0);
X Tx_mac_sop : out std_logic;
X Tx_mac_eop : out std_logic);
X end component;
X
X component eth_receiver
X port (
X peer_mac : out std_logic_vector(47 downto 0);
X my_mac : in std_logic_vector(47 downto 0);
X my_ether_type : in std_logic_vector(15 downto 0);
X transmit_data : out std_logic;
X restart : out std_logic;
X ack_fifo_full : in std_logic;
X ack_fifo_wr_en : out std_logic;
X ack_fifo_din : out std_logic_vector(pkt_ack_width-1 downto 0);
X clk : in std_logic;
X rst_n : in std_logic;
X Rx_mac_pa : in std_logic;
X Rx_mac_ra : in std_logic;
X Rx_mac_rd : out std_logic;
X Rx_mac_data : in std_logic_vector(31 downto 0);
X Rx_mac_BE : in std_logic_vector(1 downto 0);
X Rx_mac_sop : in std_logic;
X Rx_mac_eop : in std_logic);
X end component;
X
X component jtag_bus_ctl
X generic (
X d_width : integer;
X a_width : integer);
X port (
X din : in std_logic_vector((d_width-1) downto 0);
X dout : out std_logic_vector((d_width-1) downto 0);
X addr : out std_logic_vector((a_width-1) downto 0);
X nwr : out std_logic;
X nrd : out std_logic);
X end component;
X
X component MAC_top
X port (
X --system signals
X Reset : in std_logic;
X Clk_125M : in std_logic;
X Clk_user : in std_logic;
X Clk_reg : in std_logic;
X Speed : out std_logic_vector(2 downto 0);
X --user interface
X Rx_mac_ra : out std_logic;
X Rx_mac_rd : in std_logic;
X Rx_mac_data : out std_logic_vector(31 downto 0);
X Rx_mac_BE : out std_logic_vector(1 downto 0);
X Rx_mac_pa : out std_logic;
X Rx_mac_sop : out std_logic;
X Rx_mac_eop : out std_logic;
X --user interface
X Tx_mac_wa : out std_logic;
X Tx_mac_wr : in std_logic;
X Tx_mac_data : in std_logic_vector(31 downto 0);
X Tx_mac_BE : in std_logic_vector(1 downto 0);
X Tx_mac_sop : in std_logic;
X Tx_mac_eop : in std_logic;
X -- pkg_lgth fifo
X Pkg_lgth_fifo_rd : in std_logic;
X Pkg_lgth_fifo_ra : out std_logic;
X Pkg_lgth_fifo_data : out std_logic_vector(15 downto 0);
X --Phy interface
X Gtx_clk : out std_logic; -- used only in GMII mode
X Rx_clk : in std_logic;
X Tx_clk : in std_logic; -- used only in MII mode
X Tx_er : out std_logic;
X Tx_en : out std_logic;
X Txd : out std_logic_vector(7 downto 0);
X Rx_er : in std_logic;
X Rx_dv : in std_logic;
X Rxd : in std_logic_vector(7 downto 0);
X Crs : in std_logic;
X Col : in std_logic;
X -- host interface
X CSB : in std_logic;
X WRB : in std_logic;
X CD_in : in std_logic_vector(15 downto 0);
X CD_out : out std_logic_vector(15 downto 0);
X CA : in std_logic_vector(7 downto 0);
X -- mdx
X Mdo : out std_logic; -- MII Management Data Output
X MdoEn : out std_logic; -- MII Management Data Output Enable
X Mdi : in std_logic;
X Mdc : out std_logic -- MII Management Data Clock
X );
X end component;
X
X signal my_mac : std_logic_vector(47 downto 0);
X constant my_ether_type : std_logic_vector(15 downto 0) := x"fade";
X signal transm_delay : unsigned(31 downto 0);
X signal restart : std_logic;
X signal dta : std_logic_vector(31 downto 0);
X signal dta_we : std_logic := '0';
X signal dta_ready : std_logic;
X signal snd_start : std_logic;
X signal snd_ready : std_logic;
X signal dmem_addr : std_logic_vector(13 downto 0);
X signal dmem_dta : std_logic_vector(31 downto 0);
X signal dmem_we : std_logic;
X signal addr_a, addr_b : integer;
X signal test_dta : unsigned(31 downto 0);
X signal tx_mem_addr : std_logic_vector(13 downto 0);
X signal tx_mem_data : std_logic_vector(31 downto 0);
X
X signal arg1, arg2, res1 : unsigned(7 downto 0);
X signal res2 : unsigned(15 downto 0);
X signal sender : std_logic_vector(47 downto 0);
X signal peer_mac : std_logic_vector(47 downto 0);
X signal inputs, din, dout : std_logic_vector(7 downto 0);
X signal addr, leds : std_logic_vector(3 downto 0);
X signal nwr, nrd, rst_p, rst_n, dcm_locked : std_logic;
X signal not_cpu_reset, rst_del : std_logic;
X
X signal set_number : unsigned(15 downto 0);
X signal pkt_number : unsigned(15 downto 0);
X signal retry_number : unsigned(15 downto 0) := (others => '0');
X signal start_pkt, stop_pkt : unsigned(7 downto 0) := (others => '0');
X
X
X signal ack_fifo_din, ack_fifo_dout : std_logic_vector(pkt_ack_width-1 downto 0);
X signal ack_fifo_wr_en, ack_fifo_rd_en, ack_fifo_empty, ack_fifo_full : std_logic;
X signal transmit_data : std_logic := '0';
X
X signal read_addr : std_logic_vector(15 downto 0);
X signal read_data : std_logic_vector(15 downto 0);
X signal read_done, read_in_progress : std_logic;
X
X
X signal led_counter : integer := 0;
X signal tx_counter : integer := 10000;
X signal sysclk : std_logic;
X signal Reset : std_logic;
X signal Clk_125M : std_logic;
X signal Clk_user : std_logic;
X signal Clk_reg : std_logic;
X signal Speed : std_logic_vector(2 downto 0);
X signal Rx_mac_ra : std_logic;
X signal Rx_mac_rd : std_logic;
X signal Rx_mac_data : std_logic_vector(31 downto 0);
X signal Rx_mac_BE : std_logic_vector(1 downto 0);
X signal Rx_mac_pa : std_logic;
X signal Rx_mac_sop : std_logic;
X signal Rx_mac_eop : std_logic;
X signal Tx_mac_wa : std_logic;
X signal Tx_mac_wr : std_logic;
X signal Tx_mac_data : std_logic_vector(31 downto 0);
X signal Tx_mac_BE : std_logic_vector(1 downto 0);
X signal Tx_mac_sop : std_logic;
X signal Tx_mac_eop : std_logic;
X signal Pkg_lgth_fifo_rd : std_logic;
X signal Pkg_lgth_fifo_ra : std_logic;
X signal Pkg_lgth_fifo_data : std_logic_vector(15 downto 0);
X signal Gtx_clk : std_logic;
X signal Rx_clk : std_logic;
X signal Tx_clk : std_logic;
X signal Tx_er : std_logic;
X signal Tx_en : std_logic;
X signal Txd : std_logic_vector(7 downto 0);
X signal Rx_er : std_logic;
X signal Rx_dv : std_logic;
X signal Rxd : std_logic_vector(7 downto 0);
X signal Crs : std_logic;
X signal Col : std_logic;
X signal CSB : std_logic := '1';
X signal WRB : std_logic := '1';
X signal CD_in : std_logic_vector(15 downto 0) := (others => '0');
X signal CD_out : std_logic_vector(15 downto 0) := (others => '0');
X signal CA : std_logic_vector(7 downto 0) := (others => '0');
X signal s_Mdo : std_logic;
X signal s_MdoEn : std_logic;
X signal s_Mdi : std_logic;
X
X signal s_dta_we : std_logic;
X
begin -- beh
X
X -- Allow selection of MAC with the DIP switch to allow testing
X -- with multiple boards!
X with switches(1 downto 0) select
X my_mac <=
X x"de_ad_ba_be_be_ef" when "00",
X x"de_ad_ba_be_be_e1" when "01",
X x"de_ad_ba_be_be_e2" when "10",
X x"de_ad_ba_be_be_e3" when "11";
X
X
X iic_sda_main <= 'Z';
X iic_scl_main <= 'Z';
X
X not_cpu_reset <= not cpu_reset;
X rst_p <= not rst_n;
X
X flash_oe_b <= '1';
X flash_we_b <= '1';
X flash_ce_b <= '1';
X
X MAC_top_1 : MAC_top
X port map (
X Reset => rst_p,
X Clk_125M => Clk_125M,
X Clk_user => Clk_user,
X Clk_reg => Clk_user, -- was Clk_reg
X Speed => Speed,
X Rx_mac_ra => Rx_mac_ra,
X Rx_mac_rd => Rx_mac_rd,
X Rx_mac_data => Rx_mac_data,
X Rx_mac_BE => Rx_mac_BE,
X Rx_mac_pa => Rx_mac_pa,
X Rx_mac_sop => Rx_mac_sop,
X Rx_mac_eop => Rx_mac_eop,
X Tx_mac_wa => Tx_mac_wa,
X Tx_mac_wr => Tx_mac_wr,
X Tx_mac_data => Tx_mac_data,
X Tx_mac_BE => Tx_mac_BE,
X Tx_mac_sop => Tx_mac_sop,
X Tx_mac_eop => Tx_mac_eop,
X Pkg_lgth_fifo_rd => Pkg_lgth_fifo_rd,
X Pkg_lgth_fifo_ra => Pkg_lgth_fifo_ra,
X Pkg_lgth_fifo_data => Pkg_lgth_fifo_data,
X Gtx_clk => PHY_TXC_Gtxclk,
X Rx_clk => PHY_Rxclk,
X Tx_clk => PHY_Txclk,
X Tx_er => PHY_Txer,
X Tx_en => PHY_TXCTL_Txen,
X Txd => PHY_Txd,
X Rx_er => PHY_Rxer,
X Rx_dv => PHY_RXCTL_Rxdv,
X Rxd => PHY_Rxd,
X Crs => PHY_Crs,
X Col => PHY_Col,
X -- Host interface
X CSB => CSB,
X WRB => WRB,
X CD_in => CD_in,
X CD_out => CD_out,
X CA => CA,
X -- MDI interface
X Mdo => s_Mdo,
X MdoEn => s_MdoEn,
X Mdi => s_Mdi,
X Mdc => PHY_Mdc);
X
X Pkg_lgth_fifo_rd <= Pkg_lgth_fifo_ra;
X
X addr_a <= to_integer(unsigned(dmem_addr));
X addr_b <= to_integer(unsigned(tx_mem_addr));
X
X dp_ram_scl_1 : dp_ram_scl
X generic map (
X DATA_WIDTH => 32,
X ADDR_WIDTH => 13)
X port map (
X clk => clk_user,
X we_a => dmem_we,
X addr_a => dmem_addr(12 downto 0),
X data_a => dmem_dta,
X q_a => open,
X we_b => '0',
X addr_b => tx_mem_addr(12 downto 0),
X data_b => (others => '0'),
X q_b => tx_mem_data);
X
X desc_manager_1 : desc_manager
X generic map (
X N_OF_PKTS => N_OF_PKTS)
X port map (
X dta => dta,
X dta_we => dta_we,
X dta_ready => dta_ready,
X set_number => set_number,
X pkt_number => pkt_number,
X snd_start => snd_start,
X snd_ready => snd_ready,
X dmem_addr => dmem_addr,
X dmem_dta => dmem_dta,
X dmem_we => dmem_we,
X ack_fifo_empty => ack_fifo_empty,
X ack_fifo_rd_en => ack_fifo_rd_en,
X ack_fifo_dout => ack_fifo_dout,
X transmit_data => transmit_data,
X transm_delay => transm_delay,
X clk => clk_user,
X rst_n => rst_n);
X
X eth_sender_1 : eth_sender
X port map (
X peer_mac => peer_mac,
X my_mac => my_mac,
X my_ether_type => my_ether_type,
X transm_delay => transm_delay,
X set_number => set_number,
X pkt_number => pkt_number,
X retry_number => retry_number,
X clk => clk_user,
X rst_n => rst_n,
X ready => snd_ready,
X start => snd_start,
X tx_mem_addr => tx_mem_addr,
X tx_mem_data => tx_mem_data,
X Tx_mac_wa => Tx_mac_wa,
X Tx_mac_wr => Tx_mac_wr,
X Tx_mac_data => Tx_mac_data,
X Tx_mac_BE => Tx_mac_BE,
X Tx_mac_sop => Tx_mac_sop,
X Tx_mac_eop => Tx_mac_eop);
X
X eth_receiver_1 : eth_receiver
X port map (
X peer_mac => peer_mac,
X my_mac => my_mac,
X my_ether_type => my_ether_type,
X restart => restart,
X transmit_data => transmit_data,
X ack_fifo_full => ack_fifo_full,
X ack_fifo_wr_en => ack_fifo_wr_en,
X ack_fifo_din => ack_fifo_din,
X clk => clk_user,
X rst_n => rst_n,
X Rx_mac_pa => Rx_mac_pa,
X Rx_mac_ra => Rx_mac_ra,
X Rx_mac_rd => Rx_mac_rd,
X Rx_mac_data => Rx_mac_data,
X Rx_mac_BE => Rx_mac_BE,
X Rx_mac_sop => Rx_mac_sop,
X Rx_mac_eop => Rx_mac_eop);
X
X dcm1_1 : dcm1
X port map (
X CLK_IN1_P => sysclk_P,
X CLK_IN1_N => sysclk_N,
X CLK_OUT1 => Clk_125M,
X CLK_OUT2 => Clk_user,
X CLK_OUT3 => Clk_reg,
X RESET => cpu_reset,
X LOCKED => dcm_locked);
X
X process (Clk_user, cpu_reset)
X begin -- process
X if cpu_reset = '1' then -- asynchronous reset (active low)
X rst_n <= '0';
X rst_del <= '0';
X elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
X if restart = '1' then
X rst_n <= '0';
X rst_del <= '0';
X else
X if dcm_locked = '1' then
X rst_del <= '1';
X rst_n <= rst_del;
X end if;
X end if;
X end if;
X end process;
X
X -- reset
X
X phy_reset <= rst_n;
X
X -- Connection of MDI
X s_Mdi <= PHY_MDIO;
X PHY_MDIO <= 'Z' when s_MdoEn = '0' else s_Mdo;
X ack_fifo_1 : ack_fifo
X port map (
X clk => Clk_user,
X rst => rst_p,
X din => ack_fifo_din,
X wr_en => ack_fifo_wr_en,
X rd_en => ack_fifo_rd_en,
X dout => ack_fifo_dout,
X full => ack_fifo_full,
X empty => ack_fifo_empty);
X
X --E_TXD <= s_Txd(3 downto 0);
X --s_Rxd <= "0000" & E_RXD;
X
X -- signal generator
X
X dta <= std_logic_vector(test_dta);
X s_dta_we <= '1' when dta_ready = '1' and transmit_data = '1' else '0';
X dta_we <= s_dta_we;
X
X process (Clk_user, rst_n)
X begin -- process
X if rst_n = '0' then -- asynchronous reset (active low)
X test_dta <= (others => '0');
X elsif Clk_user'event and Clk_user = '1' then -- rising clock edge
X if s_dta_we = '1' then
X test_dta <= test_dta + 1;
X end if;
X end if;
X end process;
X
X -- gpio_led(1 downto 0) <= std_logic_vector(to_unsigned(led_counter, 2));
X gpio_led(0) <= snd_ready;
X gpio_led(1) <= transmit_data;
X gpio_led(2) <= cpu_reset;
X gpio_led(3) <= Tx_mac_wa;
end beh;
SHAR_EOF
(set 20 12 05 03 21 03 31 'FPGA/sp601/sp601_eth_top.vhd'
eval "${shar_touch}") && \
chmod 0644 'FPGA/sp601/sp601_eth_top.vhd'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/sp601_eth_top.vhd failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/sp601_eth_top.vhd': 'MD5 check failed'
) << \SHAR_EOF
2d4dfe95b3a1b410b532b794c8859add FPGA/sp601/sp601_eth_top.vhd
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/sp601_eth_top.vhd'` -ne 22288 && \
${echo} "restoration warning: size of 'FPGA/sp601/sp601_eth_top.vhd' is not 22288"
fi
fi
# ============= FPGA/sp601/build.sh ==============
if test -n "${keep_file}" && test -f 'FPGA/sp601/build.sh'
then
${echo} "x - SKIPPING FPGA/sp601/build.sh (file already exists)"
else
${echo} "x - extracting FPGA/sp601/build.sh (text)"
sed 's/^X//' << 'SHAR_EOF' > 'FPGA/sp601/build.sh' &&
#!/bin/bash
coregen -r -b dcm1.xco -p coregen.cgp
coregen -r -b ack_fifo.xco -p coregen.cgp
xtclsh sp601_eth.tcl rebuild_project
X
SHAR_EOF
(set 20 12 08 29 13 35 36 'FPGA/sp601/build.sh'
eval "${shar_touch}") && \
chmod 0744 'FPGA/sp601/build.sh'
if test $? -ne 0
then ${echo} "restore of FPGA/sp601/build.sh failed"
fi
if ${md5check}
then (
${MD5SUM} -c >/dev/null 2>&1 || ${echo} 'FPGA/sp601/build.sh': 'MD5 check failed'
) << \SHAR_EOF
984df06c679ba1c7e7bbe9382c9b165e FPGA/sp601/build.sh
SHAR_EOF
else
test `LC_ALL=C wc -c < 'FPGA/sp601/build.sh'` -ne 130 && \
${echo} "restoration warning: size of 'FPGA/sp601/build.sh' is not 130"
fi
fi
if rm -fr ${lock_dir}
then ${echo} "x - removed lock directory ${lock_dir}."
else ${echo} "x - failed to remove lock directory ${lock_dir}."
exit 1
fi
exit 0
Message from discussion L3 protocol for data transmission from low resource FPGA to Linux embedded system [5/6]
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