What "Parallel Hz" Really Is
Radium
Below is an example of "parallel hz"
http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
If each clock signal is 1 hz, and you have a billion of them, staggered
such that every 1ns part of the CPU can start, and finish, an
instruction - making the effective 'clock rate' 1 Ghz.
There is no real benefit to using a billion 1 hz clocks to make a clock
rate of 1Ghz and setting up such a system would be a large mess to CPU
designers. However, I find it fun to think about.
Regards,
Radium
Paul
"Radium" <gluc...@excite.com> wrote:
The image can be safely seen here, and is hardly worth the effort:
http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
Using the OPs link above crashed my browser. Naughty boy.
Shields up.
Paul
kony
<gluc...@excite.com> wrote:
Fun or just silly?
It's about as much fun as having 500 cans of beer with only
half a sip in each.
daytripper
>On 11 May 2006 13:45:38 -0700, "Radium"
><gluc...@excite.com> wrote:
>
>>Hi:
>>
>>Below is an example of "parallel hz"
>>
>>http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
>>
>>If each clock signal is 1 hz, and you have a billion of them, staggered
>>such that every 1ns part of the CPU can start, and finish, an
>>instruction - making the effective 'clock rate' 1 Ghz.
>>
>>There is no real benefit to using a billion 1 hz clocks to make a clock
>>rate of 1Ghz and setting up such a system would be a large mess to CPU
>>designers. However, I find it fun to think about.
>
>
>Fun or just silly?
"stupid silly"
>It's about as much fun as having 500 cans of beer with only
>half a sip in each.
you could actually accomplish something with 500 half-sips of beer ;-)
Radium
kony wrote:
> Fun or just silly?
Fun. Like a hobby, an interest, etc.
David Maynard
It's silly in the quantities he mentioned but the technique is already in
use, on a more practical scale.
Radium
David Maynard wrote:
> It's silly in the quantities he mentioned but the technique is already in
> use, on a more practical scale.
What equipment is it used in?
ghe...@lycos.com
I used that clocking scheme in an FPGA design years ago. I'm sure
others have also.
Terje Mathisen
There was a /. or Register note about 'Square Clocking' a few days ago:
Effectively running each quadrant of a chip 90 degrees out of phase from
the next, allowing electric power to rotate around the chip.
This would supposedly allow up 75% reduction in the total power budget,
which only makes sense if the process is nearly lossless.
Terje
--
- <Terje.M...@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"
John Fields
wrote:
---
Digital Oscilloscopes, for one.
The technique is useful for capturing high-speed analog data where
the bandwidth of a aingle ADC is insufficient.
--
John Fields
Professional Circuit Designer
Rich Grise
> kony wrote:
>> On 11 May 2006 13:45:38 -0700, "Radium"
>>
>>>
>>>Below is an example of "parallel hz"
>>>
>>>http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
>>>
>>>If each clock signal is 1 hz, and you have a billion of them, staggered
>>>such that every 1ns part of the CPU can start, and finish, an
>>>instruction - making the effective 'clock rate' 1 Ghz.
>>>
>>>There is no real benefit to using a billion 1 hz clocks to make a clock
>>>rate of 1Ghz and setting up such a system would be a large mess to CPU
>>>designers. However, I find it fun to think about.
>>
>> Fun or just silly?
>>
>> It's about as much fun as having 500 cans of beer with only
>> half a sip in each.
>
> It's silly in the quantities he mentioned but the technique is already in
> use, on a more practical scale.
I once built a "TV Typewriter" that used pipelining in the video data
path. :-)
Cheers!
Rich
Don Lancaster
I once built a TV Typewriter, too.
--
Many thanks,
Don Lancaster voice phone: (928)428-4073
Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552
rss: http://www.tinaja.com/whtnu.xml email: d...@tinaja.com
Please visit my GURU's LAIR web site at http://www.tinaja.com
Evgenij Barsukov
Not all problems can be paralelized. Most of the linear logic
type of problems are fundamentaly not paralelizeable.
The CPU you are talking about does exist. It is human brain.
Frequency 10 Hz, number of parallel units 10^10.
It works great for paralelizeable problems such as data-base
search and 3d navigation.
But it sucks at serial only problemes such as arithmetics and
boolean logic.
Regards,
Yevgen
Spehro Pefhany
<d...@tinaja.com> wrote:
>Rich Grise wrote:
>> I once built a "TV Typewriter" that used pipelining in the video data
>> path. :-)
>>
>> Cheers!
>> Rich
>>
>Funny.
>I once built a TV Typewriter, too.
Only once? ;-)
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Keith
> Rich Grise wrote:
> > On Thu, 11 May 2006 18:28:30 -0500, David Maynard wrote:
> >
> >>kony wrote:
> >>
> >>>On 11 May 2006 13:45:38 -0700, "Radium"
> >>>
> >>>
> >>>>Hi:
> >>>>
> >>>>Below is an example of "parallel hz"
> >>>>
> >>>>http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
> >>>>
> >>>>If each clock signal is 1 hz, and you have a billion of them, staggered
> >>>>such that every 1ns part of the CPU can start, and finish, an
> >>>>instruction - making the effective 'clock rate' 1 Ghz.
> >>>>
> >>>>There is no real benefit to using a billion 1 hz clocks to make a clock
> >>>>rate of 1Ghz and setting up such a system would be a large mess to CPU
> >>>>designers. However, I find it fun to think about.
> >>>
> >>>Fun or just silly?
> >>>
> >>>It's about as much fun as having 500 cans of beer with only
> >>>half a sip in each.
> >>
> >>It's silly in the quantities he mentioned but the technique is already in
> >>use, on a more practical scale.
> >
> >
> > I once built a "TV Typewriter" that used pipelining in the video data
> > path. :-)
Did you copy Grease? ;-)
--
Keith
The little lost angel
Isn't this like taking double/quadruple pumped bus and pipelining to
the extreme?
--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself
Radium
In a "parallel Hz" device the bits maybe completely in serial and the
algorithms and tasks maybe totally non-parallelizable. However, the
frequency is still parallel.
The device I am proposing is completely serial except for the clock
rate.
Radium
The little lost angel wrote:
> Isn't this like taking double/quadruple pumped bus and pipelining to
> the extreme?
No. Not at all. As I said in another post, my proposed device is
completely serial except for the frequency. It uses "parallel hz" but
in terms of everything other than frequency, it is totally serial and
non-parallel. Only the clock rate is parallel.
John Fields
a?n?g?e?l...@lovergirl.lrigrevol.moc.com (The little lost angel) wrote:
>On 11 May 2006 13:45:38 -0700, "Radium" <gluc...@excite.com> wrote:
>
>>Below is an example of "parallel hz"
>>
>>http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
>>
>>If each clock signal is 1 hz, and you have a billion of them, staggered
>>such that every 1ns part of the CPU can start, and finish, an
>>instruction - making the effective 'clock rate' 1 Ghz.
>>
>>There is no real benefit to using a billion 1 hz clocks to make a clock
>>rate of 1Ghz and setting up such a system would be a large mess to CPU
>>designers. However, I find it fun to think about.
>
>Isn't this like taking double/quadruple pumped bus and pipelining to
>the extreme?
---
Sounds like it, doesn't it?
I've got a feeling he doesn't know what he's talking about, tho...
Hey, little lost angel, welcome back. Where ya been?
Jack
: The CPU you are talking about does exist. It is human brain.
: Frequency 10 Hz, number of parallel units 10^10.
Brain brain!! What is brain??
<Star Trek, circa 1967>
HAHAHAHAHAHAHAHAHAHA!!
j.
redbelly
John Fields wrote:
> On 11 May 2006 17:30:10 -0700, "Radium" <gluc...@excite.com>
> wrote:
>
> >
> >David Maynard wrote:
> >
> >> It's silly in the quantities he mentioned but the technique is already in
> >> use, on a more practical scale.
> >
> >What equipment is it used in?
>
> ---
> Digital Oscilloscopes, for one.
>
> The technique is useful for capturing high-speed analog data where
> the bandwidth of a aingle ADC is insufficient.
>
Do you mean bandwidth or sample rate?
Mark
David Maynard
It is... 'controller'.
David Maynard
Going back a year or two there, eh?
Rich Grise
> Rich Grise wrote:
>> On Thu, 11 May 2006 18:28:30 -0500, David Maynard wrote:
>>>It's silly in the quantities he mentioned but the technique is already
>>>in use, on a more practical scale.
>>
>> I once built a "TV Typewriter" that used pipelining in the video data
>> path. :-)
>
Yeah, or 10 or 20. ;-)
<anecdote>
I was working for a video game outfit, repairing video games, like
Pac-Man, and Asteroids, and so on. Some outfit called "Universal"
came up with a game: "Mr. Do!", which they sold in PCB form. At
this time, a new game was about $3,000.00, but "Space Invaders"
and "Pong" and "Asteroids" weren't making the kind of money they
used to, so owner/operators wanted to upgrade their games. "Universal"
sold a kit where you could completely turn a game into a new game
for about $300.00. Plus the monitor, if they were converting a B&W
game.
So, we converted a lot of games, and the owner of the refurbished/
converted game would just throw away the stuff that got replaced,
notably the motherboard, essentially the whole game. So for awhile,
I had a virtually unlimited supply of CPUs, RAMs, EPROMS, all of the
stuff it takes to put a video game on a PCB. I used a Z80 and 6845 for
the memory, I/O, and video control, and a 6502 for the keyboard.
Boy, those were the days! <sigh>
</anecdote>
Cheers!
Rich
krw
gluc...@excite.com says...
Ah, a PDP-8i. (Serial ALU in a parallel computer). <yawn> You do
realize that we can do more than a thousand transistors on a chip
these days (forget the number in a system).
--
Keith
krw
jfi...@austininstruments.com says...
She's the patron L'Angel of .chips and only got x-posted here. ;-)
--
Keith
Radium
krw wrote:
> In article <1147466523.2...@i40g2000cwc.googlegroups.com>,
> gluc...@excite.com says...
> >
> > The little lost angel wrote:
> >
> > > Isn't this like taking double/quadruple pumped bus and pipelining to
> > > the extreme?
> >
> > No. Not at all. As I said in another post, my proposed device is
> > completely serial except for the frequency. It uses "parallel hz" but
> > in terms of everything other than frequency, it is totally serial and
> > non-parallel. Only the clock rate is parallel.
> Ah, a PDP-8i.
Did PDP-8i use "parallel hz"?
> (Serial ALU in a parallel computer). <yawn>
Actually my proposed device is more like a massively-serial one with
clock-rate being the only parallel entity. A billions 1 hz clocks
somehow result in an effective 1 Ghz clock rate.
N number of 1 hz clocks = clock rate of N hz
Everything else is serial
> You do
> realize that we can do more than a thousand transistors on a chip
> these days (forget the number in a system).
Yes.
> --
> Keith
krw
gluc...@excite.com says...
>
> krw wrote:
> > In article <1147466523.2...@i40g2000cwc.googlegroups.com>,
> > gluc...@excite.com says...
> > >
> > > The little lost angel wrote:
> > >
> > > > Isn't this like taking double/quadruple pumped bus and pipelining to
> > > > the extreme?
> > >
> > > No. Not at all. As I said in another post, my proposed device is
> > > completely serial except for the frequency. It uses "parallel hz" but
> > > in terms of everything other than frequency, it is totally serial and
> > > non-parallel. Only the clock rate is parallel.
>
> > Ah, a PDP-8i.
>
> Did PDP-8i use "parallel hz"?
I don't even know what "parallel Hz" (Hz is capitalized to honor
the person, BTW) is. It (I believe it was the 'I' was a parallel
processor that had a serial ALU.
>
> > (Serial ALU in a parallel computer). <yawn>
>
> Actually my proposed device is more like a massively-serial one with
> clock-rate being the only parallel entity. A billions 1 hz clocks
> somehow result in an effective 1 Ghz clock rate.
Key word: "somehow". In other words, you're clueless.
> N number of 1 hz clocks = clock rate of N hz
>
> Everything else is serial
And you would want to do this, why? (forgetting for a moment that
I don't even know what it is that you're proposing - I doubt you do
either).
> > You do
> > realize that we can do more than a thousand transistors on a chip
> > these days (forget the number in a system).
>
> Yes.
Ok, now before you answer this next question, think. What are you
going on about?
--
Keith
Radium
krw wrote:
> In article <1147491844.1...@u72g2000cwu.googlegroups.com>,
> gluc...@excite.com says...
> >
> > krw wrote:
> > > In article <1147466523.2...@i40g2000cwc.googlegroups.com>,
> > > gluc...@excite.com says...
> > > >
> > > > The little lost angel wrote:
> > > >
> > > > > Isn't this like taking double/quadruple pumped bus and pipelining to
> > > > > the extreme?
> > > >
> > > > No. Not at all. As I said in another post, my proposed device is
> > > > completely serial except for the frequency. It uses "parallel hz" but
> > > > in terms of everything other than frequency, it is totally serial and
> > > > non-parallel. Only the clock rate is parallel.
> >
> > > Ah, a PDP-8i.
> >
> > Did PDP-8i use "parallel hz"?
> I don't even know what "parallel Hz" (Hz is capitalized to honor
> the person, BTW) is. It (I believe it was the 'I' was a parallel
> processor that had a serial ALU.
Parallel Hz = method using N number of 1 hz clocks to gain a clock rate
of N hz.
> > > (Serial ALU in a parallel computer). <yawn>
> >
> > Actually my proposed device is more like a massively-serial one with
> > clock-rate being the only parallel entity. A billions 1 hz clocks
> > somehow result in an effective 1 Ghz clock rate.
> Key word: "somehow". In other words, you're clueless.
http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
If each clock signal is 1 hz, and you have a billion of them, staggered
such that every 1ns part of the CPU can start, and finish, an
instruction - making the effective 'clock rate' 1 Ghz.
> > N number of 1 hz clocks = clock rate of N hz
> >
> > Everything else is serial
> And you would want to do this, why?
For fun.
> (forgetting for a moment that
> I don't even know what it is that you're proposing - I doubt you do
> either).
>
> > > You do
> > > realize that we can do more than a thousand transistors on a chip
> > > these days (forget the number in a system).
> >
> > Yes.
> Ok, now before you answer this next question, think. What are you
> going on about?
A computer that is totally serial except for the frequency aspect. It
has a clock rate of 4 Ghz that is obtained by using 4 billion 1 hz
clocks. But otherwise, it is completely serial.
> --
> Keith
krw
>
> krw wrote:
> > In article <1147491844.1...@u72g2000cwu.googlegroups.com>,
> > gluc...@excite.com says...
> > >
> > > krw wrote:
> > > > In article <1147466523.2...@i40g2000cwc.googlegroups.com>,
> > > > gluc...@excite.com says...
> > > > >
> > > > > The little lost angel wrote:
> > > > >
> > > > > > Isn't this like taking double/quadruple pumped bus and pipelining to
> > > > > > the extreme?
> > > > >
> > > > > No. Not at all. As I said in another post, my proposed device is
> > > > > completely serial except for the frequency. It uses "parallel hz" but
> > > > > in terms of everything other than frequency, it is totally serial and
> > > > > non-parallel. Only the clock rate is parallel.
> > >
> > > > Ah, a PDP-8i.
> > >
> > > Did PDP-8i use "parallel hz"?
>
> > I don't even know what "parallel Hz" (Hz is capitalized to honor
> > the person, BTW) is. It (I believe it was the 'I' was a parallel
> > processor that had a serial ALU.
>
> Parallel Hz = method using N number of 1 hz clocks to gain a clock rate
> of N hz.
You repeat yourself. You still don't say how you're proposing to
*USE* this to some advantage.
> > > > (Serial ALU in a parallel computer). <yawn>
> > >
> > > Actually my proposed device is more like a massively-serial one with
> > > clock-rate being the only parallel entity. A billions 1 hz clocks
> > > somehow result in an effective 1 Ghz clock rate.
>
> > Key word: "somehow". In other words, you're clueless.
>
> http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>
> If each clock signal is 1 hz, and you have a billion of them, staggered
> such that every 1ns part of the CPU can start, and finish, an
> instruction - making the effective 'clock rate' 1 Ghz.
Ans this is good why? What is your proposed gain? You now have a
billion clocks to route (and time), as well as signals. You're
gaining nothing and increasing complexity. Why don't you think up
a new (and workable) way of getting rid of the clocks.
> > > N number of 1 hz clocks = clock rate of N hz
> > >
> > > Everything else is serial
>
> > And you would want to do this, why?
>
> For fun.
Ah, so it was never intended to have a practical use. ...just so
much more mental masturbation. Try the binary groups.
> > (forgetting for a moment that
> > I don't even know what it is that you're proposing - I doubt you do
> > either).
> >
> > > > You do
> > > > realize that we can do more than a thousand transistors on a chip
> > > > these days (forget the number in a system).
> > >
> > > Yes.
>
> > Ok, now before you answer this next question, think. What are you
> > going on about?
>
> A computer that is totally serial except for the frequency aspect. It
> has a clock rate of 4 Ghz that is obtained by using 4 billion 1 hz
> clocks. But otherwise, it is completely serial.
So you have four billion latches sitting around doing nothing but
leaking for 3999999999/4000000000ths of the time?
--
Keith
Radium
krw wrote:
> So you have four billion latches sitting around doing nothing but
> leaking for 3999999999/4000000000ths of the time?
Why would they leak anymore than normal clocks?
daytripper
>In article <1147543144.8...@v46g2000cwv.googlegroups.com>,
>gluc...@excite.com says...
[...]
>>
>> > And you would want to do this, why?
>>
>> For fun.
>
>Ah, so it was never intended to have a practical use. ...just so
>much more mental masturbation.
not even. this has *much* less value than that...
John Fields
DevilsPGD
"Radium" <gluc...@excite.com> wrote:
You've got a hell of a lot more of them leaking...
--
Power corrupts. Absolute power is kind of neat.
Radium
DevilsPGD wrote:
> In message <1147551051.2...@v46g2000cwv.googlegroups.com>
> "Radium" <gluc...@excite.com> wrote:
>
> >
> >krw wrote:
> >
> >> So you have four billion latches sitting around doing nothing but
> >> leaking for 3999999999/4000000000ths of the time?
> >
> >Why would they leak anymore than normal clocks?
> You've got a hell of a lot more of them leaking...
What causes them to leak?
John Fields
wrote:
>
>DevilsPGD wrote:
>> In message <1147551051.2...@v46g2000cwv.googlegroups.com>
>> "Radium" <gluc...@excite.com> wrote:
>>
>> >
>> >krw wrote:
>> >
>> >> So you have four billion latches sitting around doing nothing but
>> >> leaking for 3999999999/4000000000ths of the time?
>> >
>> >Why would they leak anymore than normal clocks?
>
>> You've got a hell of a lot more of them leaking...
>
>What causes them to leak?
---
If you have to ask, then you don't know what you're talking about.
If you need some fundamental information it would probably be best
if you posted to sci.electronics.basics, where there are no stupid
questions.
Rob Warnock
+---------------
| gluc...@excite.com says...
| > The little lost angel wrote:
| > > Isn't this like taking double/quadruple pumped bus and pipelining to
| > > the extreme?
| >
| > No. Not at all. As I said in another post, my proposed device is
| > completely serial except for the frequency. It uses "parallel hz" but
| > in terms of everything other than frequency, it is totally serial and
| > non-parallel. Only the clock rate is parallel.
|
| Ah, a PDP-8i. (Serial ALU in a parallel computer).
You're thinking of the PDP-8/S ["S" for "Serial"].
*Horribly* slow, its main claim to fame was being the first
general-purpose computer to sell for $10,000. The PDP-8/I,
introduced just a couple of years later, had all the speed
of the "Classic" PDP-8 with a price only slightly higher
than the -8/S [and the PDP-8/L was even cheaper]. See:
http://www.faqs.org/faqs/dec-faq/pdp8-models/
The PDP-8/I was fully-parallel, just like the PDP-8, except
that it was the first of the "-8" line to use TTL logic levels
(+3V & 0) instead of the negative ones (-3V & 0) used in the
Classic -8. [It was built out of "M-Series" modules, rather
than the "R/S/T/B-Series".]
Note that the PDP-8 series *did* have a multi-phase clock --
four "TS1-4" clocks (or phases) and four much-shorter "TP1-4"
pulses that overlapped the transitions between the TSn phases.
The TSn phases were generally used as "enables" of some kind,
and the TPn clock pulse that terminated the phase of the same
number were generally used to clock the results of the phase
into some register. In the PDP-8/E (another TTL machine) at least,
the TSn/TPn clocks were generated from a ring or "Johnson" counter,
what today we'd call a "one-hot state machine", running at 20 MHz.
[And, yes, I know the difference between a ring counter and a
Johnson counter -- ISTR that some members of the PDP-8 family
used one and some used the other.] In the PDP-8/E, a normal
instruction took 1.2us or 24 ticks of the ring counter, but
the ring had alterate "sidings", if you will, that permitted
read/modify/write memory cycles to take 28 ticks, or 1.4us, and
extended one of the phases (TS3? TS4?) so that the incremented
[or otherwise modified] results had time to propagate to the bus.
So in a sense, it's probably legitimate to say that the PDP-8
series did use a simple form of the OP's "parallel Hz" clocking.
-Rob
-----
Rob Warnock <rp...@rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607
Tarjei T. Jensen
> The PDP-8/I was fully-parallel, just like the PDP-8, except
> that it was the first of the "-8" line to use TTL logic levels
> (+3V & 0) instead of the negative ones (-3V & 0) used in the
> Classic -8. [It was built out of "M-Series" modules, rather
> than the "R/S/T/B-Series".]
Hi,
I thought TTL was +5V and 0. Or was this a later development?
greetings,
Keith
> Rob Warnock wrote:
>> The PDP-8/I was fully-parallel, just like the PDP-8, except
>> that it was the first of the "-8" line to use TTL logic levels
>> (+3V & 0) instead of the negative ones (-3V & 0) used in the
>> Classic -8. [It was built out of "M-Series" modules, rather
>> than the "R/S/T/B-Series".]
Interesting stuff, indeed. I'm certainly not a DECie, so remembered
wrongly. ;-)
> I thought TTL was +5V and 0. Or was this a later development?
The TI 74xx TTL series had a power supply of 5V and gnd (signal levels of
~3.6V and .8V), but that wasn't the only TTL ever to be done. IBM's
TTL, used in the 3080s, was +1.25/-3V with a signal level of gnd to -1.5V,
IIRC. TTL is a circuit topology, rather then a specific product.
BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F', and even
'LS' were actually SDTL). My bet is that the DECs were DTL too, though
I'd love to hear more from Rob. ...maybe continue thos over on AFC.
--
Keith
Pooh Bear
Keith wrote:
Weren't the shottky ( and derived ) parts DTL input and TTL output ?
Graham
Scott Alfter
Hash: SHA1
In article <nospam-1105...@192.168.1.179>,
Paul <nos...@needed.com> wrote:
>In article <1147380338....@v46g2000cwv.googlegroups.com>,
>"Radium" <gluc...@excite.com> wrote:
>> Below is an example of "parallel hz"
>>
>> http://img56.imageshack.us/my.php?image=clocksignalexample8is.gif
>
>The image can be safely seen here, and is hardly worth the effort:
>
>http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
>
>Using the OPs link above crashed my browser. Naughty boy.
>Shields up.
The OP is a troll. You should see the flamewar it ignited in comp.sys.apple2.
_/_
/ v \ Scott Alfter (remove the obvious to send mail)
(IIGS( http://alfter.us/ Top-posting!
\_^_/ rm -rf /bin/laden >What's the most annoying thing on Usenet?
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Keith
Shottky diode logic (thus properly DTL) with a shottky clamped totem-pole
output (not part of "TTL"). IIRC, the origonal 74S series was still TTL
(multiple emitter inputs). It's been too long to remember where the
split was made though. ;-)
--
Keith
Rob Warnock
+---------------
| Tarjei T. Jensen wrote:
| > Rob Warnock wrote:
| >> The PDP-8/I was fully-parallel, just like the PDP-8, except
| >> that it was the first of the "-8" line to use TTL logic levels
| >> (+3V & 0) instead of the negative ones (-3V & 0) used in the
| >> Classic -8. [It was built out of "M-Series" modules, rather
| >> than the "R/S/T/B-Series".]
| > I thought TTL was +5V and 0. Or was this a later development?
|
| The TI 74xx TTL series had a power supply of 5V and gnd (signal
+---------------
Technically, yes. I was just rounding off for simplicity. And your
3.6V/0.8V aren't quite correct, either. The 3.6 was a "typical"
high output; the minimum guaranteed output voltage was less. IIRC,
the actual 74xx levels were these:
Power supply: +5.0 V +/- 0.25 V [4.75 - 5.25]
Maximum high output level: 5.0 V [actually, ~5.6 or so.]
"Typical" high output level: 3.6 V
Minimum high output level: 2.4 V
Maximum high input level: 2.0 V
"Typical" input threshold: ~1.5 V
Minimum low input level: 0.8 V
Maximum low output level: 0.4 V
Minimum low output level: 0.0 V [actually, ~-0.6 or so.]
As you can see, there's about 0.4 "noise margin" between what an
output driver must drive and what a receiver input must accept.
Also, when driven low, TTL inputs sourced substantial current
(typ. -1.6 mA per "unit load") which had to be sinked by the
outputs. [When driven high, inputs sinked a much smaller current,
~100 uA, IIRC, so a fairly-light static current source ("pullup
resistor") was needed on "open-collector" or "tri-state" busses.]
+---------------
| BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F',
| and even 'LS' were actually SDTL). My bet is that the DECs were
| DTL too, though I'd love to hear more from Rob.
+---------------
Nope, the original M-Series boards were indeed classic 74xx TTL,
*very* low density, e.g., IIRC, an M206 card comprised only two
7474 chips -- only four flip-flops! Later cards may have used
some 'LS or 'S chips, and definitely added more MSI parts to the
earlier SSI-only mix.
Keith
says...
> Keith <k...@att.bizzzz> wrote:
> +---------------
> | Tarjei T. Jensen wrote:
> | > Rob Warnock wrote:
> | >> The PDP-8/I was fully-parallel, just like the PDP-8, except
> | >> that it was the first of the "-8" line to use TTL logic levels
> | >> (+3V & 0) instead of the negative ones (-3V & 0) used in the
> | >> Classic -8. [It was built out of "M-Series" modules, rather
> | >> than the "R/S/T/B-Series".]
> ...
> | > I thought TTL was +5V and 0. Or was this a later development?
> |
> | The TI 74xx TTL series had a power supply of 5V and gnd (signal
> | levels of ~3.6V and .8V)...
> +---------------
>
> Technically, yes. I was just rounding off for simplicity. And your
> 3.6V/0.8V aren't quite correct, either. The 3.6 was a "typical"
> high output; the minimum guaranteed output voltage was less. IIRC,
As was I, thought pointing out that TTL covered a lot more than the
TI 74xx series.
<detail snipped>
> Also, when driven low, TTL inputs sourced substantial current
> (typ. -1.6 mA per "unit load") which had to be sinked by the
> outputs. [When driven high, inputs sinked a much smaller current,
> ~100 uA, IIRC, so a fairly-light static current source ("pullup
> resistor") was needed on "open-collector" or "tri-state" busses.]
Yes, the output of true TTL is an NPN emitter. In the low state
there is an emitter current out of the input (negative input
current). As you state, in the high state the emitter is reverese-
biased so there is only leakage current. The DTL variants were
similar, but with a shottky diode replacing the NPN emitter.
> +---------------
> | BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F',
> | and even 'LS' were actually SDTL). My bet is that the DECs were
> | DTL too, though I'd love to hear more from Rob.
> +---------------
>
> Nope, the original M-Series boards were indeed classic 74xx TTL,
> *very* low density, e.g., IIRC, an M206 card comprised only two
> 7474 chips -- only four flip-flops! Later cards may have used
> some 'LS or 'S chips, and definitely added more MSI parts to the
> earlier SSI-only mix.
Didn't know DEC used simple standard 74XX TTL that far back.
Thanks.
--
Keith
GregS
Lets make sure to call those "Modules" not boards.
Certainly was present when I started working there in 69. The 8/I
integrated series, started ?? I was first trained on the PDP-15 in 1969.
I worked in an PDP- 8/I section, once a very tiny division, "displays and
data communication" !
greg
Rich Grise
> Rich Grise wrote:
>> On Thu, 11 May 2006 18:28:30 -0500, David Maynard wrote:
>>>
>>>>Fun or just silly?
>>>>
>>>>It's about as much fun as having 500 cans of beer with only
>>>>half a sip in each.
>>>
>>>use, on a more practical scale.
>>
>> path. :-)
>>
> I once built a TV Typewriter, too.
Well, I _did_ put "TV Typewriter" in quotes - I used a 6845, controlled
by a Z80, and they shared the RAM - that was only interleaved clocks;
the pipelining was from the screen RAM to the character ROM to the
shift register.
For the keyboard, I had a raw keyboard - 64 keys with 64 ea. SPST switches,
so I scanned it with a 6502. Way cool chip, for small projects. :-)
Cheers!
Rich
Radium
Okay. But I still don't understand what causes leaking. What would
cause the circuits of my design to leak?
Keith
Your design? Everything leaks, make more of 'em and they leak more.
You've added a billion more leakers. You can look at David Wang's
excellent "garden hose" analogy in this thread
comp.sys.ibm.pc.hardware.chips.
--
Keith
Keith
Physics and arithemetic.
--
Keith
Keith
I don't see either word in the above. We always called the TTL widgets
"modules", and the things they were mounted to, "cards". Cards
then plugged into "boards", boards mounted to "gates", and gates into
"frames", until the 3080 when multiple logic chips were added to
the top level package (module).
> Certainly was present when I started working there in 69. The 8/I
> integrated series, started ?? I was first trained on the PDP-15 in 1969.
> I worked in an PDP- 8/I section, once a very tiny division, "displays
> and data communication" !
I'm not quite that old. I graduated in '74 and until then I only saw an
8/E (now I'm grasping at straws) in college. A few years later '76ish I
bought a Tektronix Signal Processing System with a PDP-11/35 (in dress
blues, rather than reds ;-). That was certainly chock-full of 74xx TTL
(and 56K of core <yikes>).
Come to think of it, the Unibus was 74xx sorts of levels.
--
Keith
Radium
Please show me where there is a "David Wang" in this thread. There is a
"David Maynard" but I did see any "David Wang"
krw
gluc...@excite.com says...
Try googeling this thread in the newsgroup I indicated (CSIPHC).
--
Keith
Rob Warnock
+---------------
| Come to think of it, the Unibus was 74xx sorts of levels.
Except that the required drive current was *very* high -- for drivers
you were supposed to use TI 7438 open-collector NANDs, which could
sink 48 mA -- and the required input leakage was *very* low -- for
bus receivers you were supposed to use National SP380 NORs [or when
those got hard to find, 8T380 NORs], which had PNP emitter-follower
inputs, and sourced only ~10 uA, IIRC.
These same drivers/receivers were required for the PDP-8/E Omnibus, too.
-Rob
p.s. Back at DCA [the comms company, not the agency], we once
had a terrible race condition in one of our Omnibus products,
because we had substituted 8T380s for SP380s. The former was dog
slow, ~70 ns, while the latter was *blazingly* fast [for the day],
somewhere in the 6-8 ns range! Turns out this exposed a "hold time"
issue elsewhere in the address decoder that had been covered up
by the 8T380's slow prop time. (Oops.)
Rob Warnock
+---------------
| Don Lancaster wrote:
| > Rich Grise wrote:
| >> I once built a "TV Typewriter" that used pipelining in the
| >> video data path. :-)
| >>
| > Funny.
| > I once built a TV Typewriter, too.
|
+---------------
Uh... I suspect Don was referring to the *original* "TV Typewriter": ;-}
http://www.swtpc.com/mholley/RadioElectronics/TV_Typewriter.htm
-Rob
Michael A. Terrell
If Rich built it, it was a "TV Trypewriter". :(
--
Service to my country? Been there, Done that, and I've got my DD214 to
prove it.
Member of DAV #85.
Michael A. Terrell
Central Florida
The little lost angel
>Okay. But I still don't understand what causes leaking. What would
>cause the circuits of my design to leak?
Erm, pure law of physics?
--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself
George Macdonald
>
>Keith wrote:
>> On Mon, 15 May 2006 15:46:43 -0700, Radium wrote:
<<snip>>
>> Your design? Everything leaks, make more of 'em and they leak more.
>> You've added a billion more leakers. You can look at David Wang's
>> excellent "garden hose" analogy in this thread
>> comp.sys.ibm.pc.hardware.chips.
>>
>> --
>> Keith
>
>Please show me where there is a "David Wang" in this thread. There is a
>"David Maynard" but I did see any "David Wang"
e4a7m6$mdf$1...@grapevine.wam.umd.edu - different thread.
--
Rgds, George Macdonald
GregS
When DEC started they just made modules.
greg
Radium
Thanks
chrisv
I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were
just enhancements with shottky transitors (i.e. shottky clamped
transistors) but they are still TTL.
Keith
chr...@nospam.invalid says...
No, the later versions have schottky diode logic with schottky
clamped amplifier rather than transistor (emitter) logic (74S
series also had the schottky clamped amplifier).
Circuit diagrams (note: from rusty memory)
TTL (74xx and 74Sxx): Vcc
|
.-.
Vcc | | Vcc
| | |
.-. '-' |
| | | |/
| | +---+-| Q3
'_' | |>
| | |
----- |/ V
A1 0----vv \-----| Q2 -
A1 o----/ Q1 |> +-------o O
| |/
+----+| Q4
| |>
.-. |
| | GND
| |
'-' created by Andy´s ASCII-Circuit
| v1.22.310103 Beta www.tech-chat.de
GND
Schottky clamped TTL has schottky diodes from base to collector on
Q2 and Q4 (IIRC) to prevent saturation.
SDTL (74LSxx, 74ASxx, 74ALSxx, etc.):
VCC VCC
| .-. VCC
.-. | |
| | | | |
| | '-' |/
'-' + -|
| | |>
| | |
A1 o-S<--+ |/ V
+--->S-----| -
A2 o-S<--+ |> +--- O
| |/
+--|
| |>
.-. |
| | GND
| |
'-'
|
GND
Again, Q2 and Q4 are schottky clamped.
--
Keith
Spehro Pefhany
Compare the schematics on page 2 of this PDF:
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls00.pdf
The '00 and S00 are TTL; the LS00 is DTL.
Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
Rich Grise
> Rich Grise <rich...@example.net> wrote:
> +---------------
> | Don Lancaster wrote:
> | > Rich Grise wrote:
> | >> I once built a "TV Typewriter" that used pipelining in the
> | >> video data path. :-)
> | >>
> | > Funny.
> | > I once built a TV Typewriter, too.
> |
> | Well, I _did_ put "TV Typewriter" in quotes - I used a 6845...
> +---------------
>
> Uh... I suspect Don was referring to the *original* "TV Typewriter": ;-}
>
> http://www.swtpc.com/mholley/RadioElectronics/TV_Typewriter.htm
>
Uh, yeah, I think that's why Don chimed in with his quip. :-)
Mine had an 80 x 25 display; I did it with black characters on a white
background, which is really only an inverter. Don's did it all with
discrete TTL, as I remember, so when I did mine all the hard parts
were already done. :-)
(I don't exactly remember if I got the pipelining idea from Don, or from
some AMD data book. ;-) )
Cheers!
Rich
Rich Grise
> Rob Warnock wrote:
>>
>> Rich Grise <rich...@example.net> wrote:
>> +---------------
>> | Don Lancaster wrote:
>> | > Rich Grise wrote:
>> | >> I once built a "TV Typewriter" that used pipelining in the
>> | >> video data path. :-)
>> | >>
>> | > Funny.
>> | > I once built a TV Typewriter, too.
>> |
>> | Well, I _did_ put "TV Typewriter" in quotes - I used a 6845...
>> +---------------
>>
>> Uh... I suspect Don was referring to the *original* "TV Typewriter": ;-}
>>
>> http://www.swtpc.com/mholley/RadioElectronics/TV_Typewriter.htm
>>
>> -Rob
>>
>> -----
>> Rob Warnock <rp...@rpw3.org>
>> 627 26th Avenue <URL:http://rpw3.org/>
>> San Mateo, CA 94403 (650)572-2607
>
>
>
> If Rich built it, it was a "TV Trypewriter". :(
Screw you.
chrisv
>Again, Q2 and Q4 are schottky clamped.
That does not make it not TTL...
chrisv
>On Tue, 16 May 2006 10:59:26 -0500, the renowned chrisv
><chr...@nospam.invalid> wrote:
>
>>Keith wrote:
>>
>>>On Mon, 15 May 2006 00:29:08 +0100, Pooh Bear wrote:
>>>>
>>>> Weren't the shottky ( and derived ) parts DTL input and TTL output ?
>>>
>>>Shottky diode logic (thus properly DTL) with a shottky clamped totem-pole
>>>output (not part of "TTL"). IIRC, the origonal 74S series was still TTL
>>>(multiple emitter inputs). It's been too long to remember where the
>>>split was made though. ;-)
>>
>>I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were
>>just enhancements with shottky transitors (i.e. shottky clamped
>>transistors) but they are still TTL.
>
>Compare the schematics on page 2 of this PDF:
>http://www.ee.washington.edu/stores/DataSheets/74ls/74ls00.pdf
>
>The '00 and S00 are TTL; the LS00 is DTL.
No. DTL was an older type of logic. 'S00 and 'LS00 are both newer
than '00.
Keith
chr...@nospam.invalid says...
> Keith wrote:
>
> >Again, Q2 and Q4 are schottky clamped.
>
> That does not make it not TTL...
No, there I was responding to the point about schottky clamps,
there. You've snipped out the part that makes it *NOT* TTL. The
input logic *TRANSISTOR* makes the 74xx series "Transistor-
Transistor Logic". Replace the input transistors with *DIODES* and
it becomes Diode-Transistor Logic, or DTL.
--
Keith
Keith
chr...@nospam.invalid says...
and later families were DTL, no matter what TI called them on the
databook cover.
--
Keith
Spehro Pefhany
<chr...@nospam.invalid> wrote:
"If you call a tail a leg, how many legs does a dog have? Answer:
Four. Calling a tail a leg doesn't make it a leg."
-- Abraham Lincoln
chrisv
The transistors were not replaced with diodes in S and LS logic. S
and LS is still TTL, schottky clamps and all.
chrisv
I'll dig out my old TI book tonight and look at the schemos.
Keith
--
Keith
Radium
Okay. I read it. I understand leaking a bit more. I understand that
using 4 billion 1 hz clocks to gain a clock rate of 4 Ghz would leak
[well, any electronic mechanism "leaks" to some extent]. What I don't
understand is why would it leak 3999999999/4000000000ths of the time?
Keith
Each one of your clocks is doing nothing for 3999999999/4000000000ths of
the time. Whether it is doing anything or not, it's leaking. Since it's
not doing anything, it's not producing anything for that time. Of course
1/4000000000ths of the time that clock circuit is doing something useful.
Now, wouldn't it be nice to up the percentage of useful time?
--
Keith
Rob Warnock
+---------------
| Schottky clamped TTL has schottky diodes from base to collector
| on Q2 and Q4 (IIRC) to prevent saturation.
The TI 54/74Sxx series [and competitors] also used Schottky
clamping on Q1 [the input transistor] as well -- yes, even
those with multiple-emitter inputs. They also used Schottkys
for the Darlington driver of the upper output stage [which
you didn't show -- it would have driven your Q3's base] and
for the anti-overdrive transistor [also not shown] clamped
on the base of Q4. In fact, of the six transistors in the
small 54/74Sxx series, only the one matching your Q3 was
*not* Schottky-clamped. ;-}
Rob Warnock
+---------------
| chr...@nospam.invalid says...
| > Keith wrote:
| > >The input logic *TRANSISTOR* makes the 74xx series "Transistor-
| > >Transistor Logic". Replace the input transistors with *DIODES* and
| > >it becomes Diode-Transistor Logic, or DTL.
| >
| > The transistors were not replaced with diodes in S and LS logic.
| > S and LS is still TTL, schottky clamps and all.
|
| Please read what I've written again. You're simply wrong.
Actually, he's exactly half-right! ;-} I just looked it up
in an old TI 54/74 Data Book. The 'S series still had true TTL
inputs (albeit Schotty-clamped), but the 'LS series had DTL inputs
(using Schotty diodes) feeding a Schotty-clamped phase-splitter.
chrisv
>chr...@nospam.invalid says...
>>
>> The transistors were not replaced with diodes in S and LS logic. S
>> and LS is still TTL, schottky clamps and all.
>>
>Please read what I've written again. You're simply wrong.
I checked "the reference", and I was correct regarding S logic, but
incorrect regarding LS logic. The former has the emitter inputs, the
later has the diode inputs. So I guess it was a split decision. 8)
Keith
@rpw3.org says...
> Keith <k...@att.bizzzz> wrote:
> +---------------
> | chr...@nospam.invalid says...
> | > Keith wrote:
> | > >The input logic *TRANSISTOR* makes the 74xx series "Transistor-
> | > >Transistor Logic". Replace the input transistors with *DIODES* and
> | > >it becomes Diode-Transistor Logic, or DTL.
> | >
> | > The transistors were not replaced with diodes in S and LS logic.
> | > S and LS is still TTL, schottky clamps and all.
> |
> | Please read what I've written again. You're simply wrong.
> +---------------
>
> Actually, he's exactly half-right! ;-} I just looked it up
> in an old TI 54/74 Data Book. The 'S series still had true TTL
> inputs (albeit Schotty-clamped), but the 'LS series had DTL inputs
> (using Schotty diodes) feeding a Schotty-clamped phase-splitter.
No, he's not. Go back and read the thread again (where the
transition was made has been discussed at length).
--
Keith
Keith
chr...@nospam.invalid says...
74Sxx clearly in the TTL category (though some S is DTL according
to one poster) and LS and newer in the DTL category.
<from somewhere up there>:
Circuit diagrams (note: from rusty memory)
TTL (74xx and 74Sxx): Vcc
^^^^^ |
.-.
Vcc | | Vcc
| | |
.-. '-' |
| | | |/
| | +---+-| Q3
'_' | |>
| | |
----- |/ V
A1 0----vv \-----| Q2 -
A1 o----/ Q1 |> +-------o O
| |/
+----+| Q4
| |>
.-. |
| | GND
| |
'-' created by Andy´s ASCII-Circuit
| v1.22.310103 Beta www.tech-chat.de
GND
Schottky clamped TTL has schottky diodes from base to collector on
Q2 and Q4 (IIRC) to prevent saturation.
SDTL (74LSxx, 74ASxx, 74ALSxx, etc.):
^^^^^^^^^^^^^^^^^^^^^^^
VCC VCC
| .-. VCC
.-. | |
| | | | |
| | '-' |/
'-' + -|
| | |>
| | |
A1 o-S<--+ |/ V
+--->S-----| -
A2 o-S<--+ |> +--- O
| |/
+--|
| |>
.-. |
| | GND
| |
'-'
|
GND
--
Keith
chrisv
>In article <ue6m629aq7b9828ps...@4ax.com>,
>chr...@nospam.invalid says...
>> Keith wrote:
>>
>> >chr...@nospam.invalid says...
>> >>
>> >> The transistors were not replaced with diodes in S and LS logic. S
>> >> and LS is still TTL, schottky clamps and all.
>> >>
>> >Please read what I've written again. You're simply wrong.
>>
>> I checked "the reference", and I was correct regarding S logic, but
>> incorrect regarding LS logic. The former has the emitter inputs, the
>> later has the diode inputs. So I guess it was a split decision. 8)
>>
>NO, the drawing I included (up there somewhere) had the 74xx and
>74Sxx clearly in the TTL category (though some S is DTL according
>to one poster) and LS and newer in the DTL category.
Okay, I missed that detail in your post. But that doesn't make my
statement above "simply wrong". Half of my assertions were correct.
Keith
> Keith wrote:
>
> >In article <ue6m629aq7b9828ps...@4ax.com>,
> >chr...@nospam.invalid says...
> >> Keith wrote:
> >>
> >> >chr...@nospam.invalid says...
> >> >>
> >> >> The transistors were not replaced with diodes in S and LS logic. S
> >> >> and LS is still TTL, schottky clamps and all.
> >> >>
> >> >Please read what I've written again. You're simply wrong.
> >>
> >> I checked "the reference", and I was correct regarding S logic, but
> >> incorrect regarding LS logic. The former has the emitter inputs, the
> >> later has the diode inputs. So I guess it was a split decision. 8)
> >>
> >NO, the drawing I included (up there somewhere) had the 74xx and
> >74Sxx clearly in the TTL category (though some S is DTL according
> >to one poster) and LS and newer in the DTL category.
>
> Okay, I missed that detail in your post. But that doesn't make my
> statement above "simply wrong". Half of my assertions were correct.
The sun rises in the East too but that wasn't be discussed either.
--
Keith
chrisv
"wasn't be discussed"? I don't know what that means. Of course, I
realize that communications errors will sometimes occur on both the
send and receive ends.
I believe that my comments were on-topic, if imperfect. Astronomical
events are not on-topic, and cannot be compared to any of my comments.
Keith
> Keith wrote:
>
> >In article <admm62d7e8sfpppsp...@4ax.com>,
> >chr...@nospam.invalid says...
> >> Keith wrote:
> >>
> >> >In article <ue6m629aq7b9828ps...@4ax.com>,
> >> >chr...@nospam.invalid says...
> >> >> Keith wrote:
> >> >>
> >> >> >chr...@nospam.invalid says...
> >> >> >>
> >> >> >> The transistors were not replaced with diodes in S and LS logic. S
> >> >> >> and LS is still TTL, schottky clamps and all.
> >> >> >>
> >> >> >Please read what I've written again. You're simply wrong.
> >> >>
> >> >> I checked "the reference", and I was correct regarding S logic, but
> >> >> incorrect regarding LS logic. The former has the emitter inputs, the
> >> >> later has the diode inputs. So I guess it was a split decision. 8)
> >> >>
> >> >NO, the drawing I included (up there somewhere) had the 74xx and
> >> >74Sxx clearly in the TTL category (though some S is DTL according
> >> >to one poster) and LS and newer in the DTL category.
> >>
> >> Okay, I missed that detail in your post. But that doesn't make my
> >> statement above "simply wrong". Half of my assertions were correct.
> >
> >The sun rises in the East too but that wasn't be discussed either.
>
> "wasn't be discussed"? I don't know what that means. Of course, I
> realize that communications errors will sometimes occur on both the
> send and receive ends.
Fingle-fumber with an over-edit thrown on for good measure. ;-\
Try: "The sun rises in the East too but that wasn't being discussed
either"
> I believe that my comments were on-topic, if imperfect. Astronomical
> events are not on-topic, and cannot be compared to any of my comments.
I never said that the schottky clamps somehow made TTL into DTL,
which was what you tried to force into my mouth by your editing and
response (hence my strong objections to your articles). My point
was always about the *LOGIC* part of the circuit rather than the
amplifier clamps being the key to TTL vs. DTL). You maintained
that it was *ALL* TTL, which it is clearly not and I called you on
that statement.
I said several times that the 74Sxx line was TTL, at least in the
beginning but couldn't remember exactly when/where the switch-over
took place. Others pointed out that the 74Sxx line wasn't all TTL
(complex functions are DTL) and the 74LSxx was (all DTL).
--
Keith