hopcode wrote:
>> The theory is of course obvious, but as long as you're writing for a
>> 32-bit platform I would simplify this a _lot_:
>> cmp eax,edx
>> cmovb eax,edx
>> I.e. "eax = edx IF (eax < edx)"
>> This is 2-3 cycles on all those cpus which implements CMOVcc.
Oops!
You asked for minimum, not max, so that CMOV should be CMOVA instead of
CMOVB!
The main step of algorithms that don't use CMOV is of course the CMP/SBB
combo:
This leaves a full-register flag value, at which point you can either
use it twice, as-is and after inversion, on both inputs, or you can use
it on the difference between the two values, and add/sub that:
cmp edx,eax
sbb ebx,ebx ; -1 IFF EDX < EAX
sub edx,eax ; Negative difference...
and edx,ebx
add eax,edx
The alternative:
cmp edx,eax
sbb ebx,ebx ; -1 IFF EDX < EAX
and edx,ebx
xor ebx,-1
and eax,ebx
or eax,edx
This is one more instruction and one more cycle of minimum latency!
If I calculate the flag twice...
cmp edx,eax
sbb ebx,ebx ; -1 IFF EDX < EAX
cmp eax,edx
sbb ecx,ecx
and edx,ebx
and eax,ecx
or eax,edx
then I end up with yet another instruction (7), but the absolute minimum
latency is actually just 4 cycles if both of the CMP/SBB combinations
can execute in parallel!