> z196 (next machine after z10) peak I/O benchmark doing 2M IOPS with 104
> FICON (ficon is mainframe channel paradigm layer built on top of FCS
> that significantly reduces throughput compared to base FCS)
> .... compared to recently announced FCS for e5-2600 blade claiming over
> million IOPS for single FCS
>
http://en.wikipedia.org/wiki/FICON
Fibre Channel (FCS)
http://en.wikipedia.org/wiki/Fibre_Channel
Scalable Coherent Interface
http://en.wikipedia.org/wiki/Scalable_Coherent_Interface
some recent refs (including mainframe ESCON was obsolete by the time it
was released in early 90s with ES/9000)
http://www.garlic.com/~lynn/2013g.html#14 Tech Time Warp of the Week: The 50-Pound Portable PC, 1977
http://www.garlic.com/~lynn/2013g.html#23 Old data storage or data base
http://www.garlic.com/~lynn/2013g.html#41 A History Of Mainframe Computing
In 1988, I had been asked to help LLNL standardized FCS. In 1990, I was
also pulled into SCI (scalable coherent interface, another fiber-optic
serial standard, was being pushed for higher I/O than FCS as well as
memory bus operation) ... being pushed by Gustavson out of SLAC. SCI
then shows up in memory bus for Convex (HP risc), SGI (MIPS risc),
Sequent (i486), and Data General (i486). Later we do some consulting at
Convex, SGI, and Sequent (later HP buys Convex and IBM buys Sequent)
the cluster scaleup being transfered and being told we couldn't work
on anything with more than four processors, contributed significantly
to the decision to leave later that year. recent references
http://www.garlic.com/~lynn/2013g.html#22 What Makes core storage management so cool?
http://www.garlic.com/~lynn/2013g.html#40 The Vindication of Barb
past posts mentioning ha/cmp
http://www.garlic.com/~lynn/subtopic.html#hacmp
much of my career I was told that I had no career and couldn't expect
promotions, also that top technical positions were quite political in the
corporation and I had managed to offend quite a number of executives.
In the earlier 80s, I was told that they refused to make me IBM Fellow,
but then some of the Fellows provided funding and project support
behind the scenes; I was even included in discussions about creation
of the STSM level. some of this was explained as the significant IBM
corporate culture change to "make no waves" and "syncophancy" that
occurred as FS was failing
http://www.garlic.com/~lynn/submain.html#futuresys
from annals of "truth is stranger is fiction" ... after my last day, I
get a letter at home saying I was promoted to STSM. Past posts
referencing the after-the-fact promotion
http://www.garlic.com/~lynn/2010l.html#74 CSC History
http://www.garlic.com/~lynn/2010q.html#50 I actually miss working at IBM
http://www.garlic.com/~lynn/2011c.html#87 A History of VM Performance
http://www.garlic.com/~lynn/2012k.html#26 How to Stuff a Wild Duck
from long ago and far away ... part of departing "goodby" message (my
ftp/anon had shadow of all sorts of things, lots of standards meetings
and notes as well as internet RFCs, drafts and other documents), "DSD"
refers to the mainframe division:
Date: Jul 22 18:50:37 1992
From: wheeler
Subject: departure
wheeler.losgatos.ibm.com ftp/anon repository is shutdown.
i made 3-4 postings to convex forum on chaste tools disk with respect
to sci, etc.
fyi, attached is summary/overview of DSD/executive presentation on
clustering that i gave in hudson valley a week ago monday.
+++++
Lynn Wheeler - rip 31jul92
xxxxxxxxxxxxx reference xxxxxxxxxxxx
Four Tier Asynchronous Computer Model
* super-scalar asynchronous operation
* tightly-coupled SMP operation with weakly-ordered or relaxed memory
consistency
* loosely-coupled multiprocessing with high-performance, light-weight
I/O programming model
* networked clusters
. information contained here-in is non-proprietary and taken from
widely available public domain literature
------------------------
... snip lots of detail ...
------------------------
1Q93 Design Point
* single board 4-way SMP
* super-scaler 400mips aggregate
* shared L2-cache, 1meg or larger
* hardware SMP parallelism assists
* interleaved 500mbyte memory
* multiple Fibre Channel Standard full-duplex attachments
* I/O processing off-loaded and pipelined
* FCS-switch fully-meshed interconnect for inter-processor
communication as well as I/O device attachment
* IO.INTensive = 520mbyte/400mips
. 3-4 1gbit FCS links (@200mbyte) per board
. for 25% IO.INTensive substitute quarter-speed FCS
* between one and 24-32 4-way SMP boards in a box
. 4-128 processors in a box
. 400 to 12,800 mips in a box
. SMP boards interconnected with FCS in LCMP-cluster
* one or more boxes in a LCMP-cluster
. FCS interconnect, I/O attachment and switches
* no-single-point-of-failure
* high-performance configurable intelligent RAID controllers
------------------------
1Q94 Design Point
* single board 4-way SMP
* super-scaler 1000mips aggregate
* shared L2-cache, 4meg or larger
* hardware SMP parallelism assists
* interleaved 1gbyte SCI memory attachment
* between one and 24-32 4-way SMP boards in a box
. 4-128 processors in a box
. 1,000 to 32,000 mips in a box
. SMP boards using multiple 1gbyte SCI connections
for n-way cache coherency across whole box
* multiple FCS full-duplex attachments
* FCS-switch for processor interconnect and device
attachment
* IO.INTensive = 1.3gbyte/1000mip
. 7-8 1gbit FCS links (@200mbyte) per board
. some combination of 1gbyte SCI IO link and 1gbit FCS links
* LCMP-clusters created with two or more SMP boxes
. LCMP box boundaries for failure isolation.
. FCS interconnect, I/O attachment and switches
. SCI I/O attachment, switches, and rings
* long distance (2km & above) gbit FCS interconnect for
geographically separated, disaster survivability operation
... snip ...