I've complied this FAQ/guide to address a lot of common issues.  First
of all, please make sure you are meeting all of the specifications.
Here is a list of the major ones..

1.  All of the inputs coming into your adder must be passed through a
buffer, a chain of two unit sized inverters (Wp/Wn = .96um/.48um).

2.  The input cap each input sees immediately following the buffer must
be less than 2 times the cap of the unit inverter.  A quick way to
check this is to make sure the sum of all of the widths of the
transistors driven by the input is smaller than 2*(.96um + .48um)

3.  Delay for both dynamic and static designs are measured from 50% of
input(after the unit sized buffer) to 50% of output.  For dynamic,
launching the inputs at different times during the eval/precharge
cycles will result in different delays; try to find the optimal time to
launch the inputs.

4.  The external load is 16 unit sized inverters(.96um/.48um).  The
best way to simulate this is to create a layout and a schematic in
cadence for a unit sized inverter, extract into HSPICE, and attach it
to the end of your adder using "m" and subcircuits.  You can build the
input buffers in the same way.

5.  In layout, all inputs: A<0:7>, B<0:7>, and Cin and outputs Sum<0:7>
and Cout must be at the outermost edge of your cell.

6.  You need to prove functionality by generating the correct outputs
using the inputs we have provided in the powerpoint template.  You need
to come up with your own inputs for the worst case delay.  Please try a
number of possible worst case inputs to verify your choice.

7. Turn in netlists from LVS (not from HSPICE).  These are
automatically generated and directions for fetching them will be
provided in a follow up post.

Please make sure you understand 1-6 right now.  If are unsure about any
of them, please ask.

A few tips for layout.

1.  Try to route using just the first two or three metal layers.

2.  Use finger to implement transistors in series.  Use multiplier to
implement large transistors, transistors in parallel, and transistors
in series.

3.  Don't forget to include ntaps and ptaps.

4.  Remeber in a real layout, many PMOS transistors should share the
same bulk (that's the large green rectangle).

5.  Use only shape pins and make sure they are the right type (input,
output, or input/output).

If Cadence cannot be open because some files are locked please see the
previous post regarding unlocking files.  I've noticed that most people
do their work late at night.  I will try to stop by in the evening
everyday (except for Monday) for half to an hour to answer some
questions and help trouble shoot.

Good Luck,